SU738101A1 - Pulse repetition frequency multiplier - Google Patents

Description

(54) MULTIDIMENTAL FREQUENCY FOLLOWING The invention relates to a pulse technique. A frequency multiplier is known that contains a generator of counting pulses, the frequency of which is higher than the frequency of the input signals, a pulse counter containing W bits, a second m-bit counter of pulses that form triggers logical elements And. The multiplier has insufficient stability at low frequencies of the input signal. The closest in technical essence is a frequency multiplier, containing a pulse generator, the output of which is connected to the first inputs of logical elements AND, the second input of the first of which is connected to the input of the first front-edge generator, the second input of the second logical element AND is connected to the input of the second Forms of the front fronts, the outputs of each logical element AND and the corresponding front-edge driver, are connected to the inputs of one of two counters, each code with one with a first input of one of the two b o- Cove comparing mi OR gate whose two inputs are connected to outputs of said leading edges formers Hi. The disadvantage of this multiplier is the insufficient installation accuracy and the small range of variation of the multiplier. The aim of the inventions is to increase the installation accuracy and to extend the range of variation of the multiplication factor. Pulse frequency multiplier, hold pulse generator, OUT: one of which is connected to the first inputs of logic gates And, the second input of the first of which is connected to the input of the first front-edge driver, second input of the second logical element I of the first front edge, outputs each of the logic element And and the corresponding front-edge driver is connected to the inputs of one of the two pulse counters, the output of each of which is connected to the first input of one and From the two blocks of comparison, and the logical element of the VDI, the two inputs of which are connected to the outputs of the fore-front drivers, are triggered, two up-. Additional pulse counters and four additional AND logic gates, the outputs of two of which are connected to the additional inputs of the OR logic element, and the first inputs are connected to the second input of one of the AND logic gates and one of the trigger outputs, the input of which is connected to the input bus, the first inputs two other additional logic elements And are connected respectively to the outputs of the form

The leading edge worlds, the outputs of these additional logical sequences AND are connected to the first inputs of additional pulse counters, the second inputs of which are connected to the outputs of the corresponding AND logic elements, and the outputs of additional pulse counters are connected to the second inputs of the comparison blocks, the output of one of which is connected to the second inputs the first and third, and the output of the second comparison unit is connected to the second inputs of the second and fourth mentioned additional logic gates And,

The structural electrical circuit of the described multiplier is shown in the drawing,

The multiplier contains a trigger 1 logic elements And 2, 3, a front-edge driver 4, 5, a pulse generator b, a logic element OR 7 ,, comparison blocks 8, 9, counters 10.11 pulses, additional counters 12,. 13 pulses, additional logic elements AND 14, .. 17, The input signal is fed to the input bus 18, the output signal is removed from the high voltage 19.

The principle of operation of the multiplier is in the following.

Let during the period following the pulses of the input sequence, the counter 11 from the pulse generator 6 received 24 pulses, i.e. the number 24 was recorded and the frequency is multiplied by 4. At the time of IQ, trigger 1 goes from state O to state 1. At the output of driver 7

Claims (2)

And 15 for resetting from the censor 13. Then, when the 12th pulse arrives at the counter 13, a pulse is formed at the output of the comparison block 9 and the whole process repeats again until the end of the input sequence period. The counter 10 at the same time counts the pulses for the period T and does not participate in the formation of the output impulses at this period. The device output only receives pulses from the comparator block 9 through the logical element AND 14, the logical element AND 17 is locked with a low voltage level of the trigger 1 coming from the inverse output to eliminate failures in the output sequence due to the false operation of the comparison block 8. In the new period , at the time t /), the trigger 1 goes from the state O, At the output of the front-edge driver 5, a short pulse is generated, coming through the OR gate to the output of the device, to the reset of the counter 11 and AND 16 on resetting the counter 12. Pulses from generator 6 through the logical element AND 3 are fed to the counting input of counter 11 and to the counting input of counter 12, the number written in (N-2) most significant bits of counter 10 is compared with the number recorded in the counter 12, the pulses of equality from the output of the comparison block 8 through the logical element AND 17 through the logical element OR 7 arrive at the output of the device and through the logical element AND 16 to reset the counter 12. The entire process, which takes place during the previous period, repeats again. 014 of the leading edge 4, a short pulse is generated, which arrives at the reset input of the counter 10, through the logic element AND 15 to the reset input of the counter 13 and through the logical element OR 7 at the output of the device, C of the generator 6 through the logical element AND 2 at the counting input of the counter 10 and the counting input counter 13 receives pulses. The block is compared to. Unit 9 compares the number recorded in (H-2) most significant bit of counter 11 with the number written in counter 13. For this example, (N -2) Most significant {counter of 11 is recorded number This means that when entering 6 pulse at the counter 13 at the output of the comparison block 9, a pulse is generated through the logic element AND 14, through the logical element OR 7 at the output of the device and through the logic element. Thus, at the output a sequence of pulses is formed, the frequency of which is four times the frequency of the input sequence imp lsov. By increasing the frequency of the pulses from generator 6, one can increase the counter size and multiply the frequency by a higher number, as well as increase the multiplication accuracy. By changing the number of bits to be compared, the multiplication factor can be changed over a wide range. The advantages of the device also include the fact that the lower the frequency of the input pulses, the more accurately the input frequency is multiplied by this multiplication factor. The described device can multiply ultra-low frequencies (fractions of a hertz). Emerging faults are automatically eliminated in the subsequent period of the input sequence, the phase of the output pulse sequence is rigidly connected with the phase of the input pulse sequence. Due to the fact that the device is fully implemented on the elements of digital technology, this makes it possible to microminiaturize the circuit, improve its performance, namely, reduce the size and weight, reduce power consumption, extend the temperature range. The invention Investigation multiplier following impulses, containing a pulse generator, the output of which is connected to the first inputs of logic gates And, the second input of the first of which is connected to the input of the first front-edge driver, the second input of the second logical element And, is connected to the input of the second front-edge generator, the output / of each logical element AND and the front-edge driver corresponding to it are connected to the inputs of one of. two pulse counters, each output connected q by the first input of one of two comparison blocks, and a logic element, an OR element whose two inputs are connected to the outputs of the fore-front drivers, characterized in that, in order to increase the accuracy of the installation and extend the range changes of the multiplication factor, a trigger, two Additional pulse counters, and four additional AND logic elements, the outputs of two of which are connected to the additional inputs of the logic element OR, and the left inputs - with the second input of one of the main logic elements AND and one of the trigger outputs, the input of which is connected to the input bus; to the first inputs of additional impulse counters, the second inputs of which are connected to the outputs of the corresponding logic elements And, and the outputs of the additional impulse counters are connected to the second and by comparison block moves, the output of one of which is connected to the second inputs of the first and third, and the second comparison block output is connected to the second inputs of the second and fourth mentioned additional logic elements 47-33978 cl. 98 (5), p. 32, 08.28.72. 2. USSR author's certificate number 484619, cl. H 03 W 19/06, 12/4/73. 738101 rs