SU849495A1 - Repetition rate scaler with 3:1 countdown ratio - Google Patents

Description

(54) THE DIVIDER OF THE FREQUENCY RATING OF PULSES FOR THREE

The invention relates to the supernumerary technique and can be computationally used in various devices. techniques for dividing the frequency of pulses by three. A frequency divider is known, based on series-connected triggers with a pulse counting control and with a feedback circuit from the high-order bit to the low-order one. The disadvantage of this frequency divider is the possibility of failures caused by the difference in speeds and thresholds of triggering of the trigger. the composition of the frequency divider pulses. The closest to the present invention is a device for dividing a pulse frequency into three, built on two counting jk-flip-flops, each of which consists of a main and auxiliary flip-flops, the first inputs of which are combined and connected to the input signal bus; the single output of the first counting trigger is connected to the third input j of the second trigger, and the zero output of the second counting trigger is connected to the third input j of the first counting trigger. The second inputs of both counting triggers are connected to the clock signal bus 2. A disadvantage of this device is low reliability due to failures that can occur at the end of the second counting pulse, when the potential at the third input j of the first counting trigger as a result of the slower response speed of the second counting trigger still equal, as well as at the end of the third counting pulse, when the potential at this input becomes different. 1. The purpose of the invention is to increase the reliability of the pulse frequency divider. three. The goal is achieved by the fact that the frequency divider

impulses for three, containing two series-connected counting triggers, each of which consists of main and auxiliary triggers, the first inputs of the counting triggers are connected to the input bus, their second inputs are connected to the clock signal bus, and the zero output of the second counting trigger is connected to the third input the first counting trigger, entered the element AND-NOT, one input of which is connected to the input bus, the second input is connected to the single output of the second counting trigger, and the output of the element AND-NOT connected to the output of It is the frequency and the third input of the second counting trigger.

1, a functional diagram of a pulse frequency divider by three is presented; in fig. 2 - time diagrams of his work.

The pulse frequency divider into three contains two counting triggers 1 and 2, each of which consists of 3 main and 4 and auxiliary 5 and 6 triggers, the element AND NOT 7, the input bus 8, the output bus 9, the bus 10 clock signal, and the main 3 and 4 and auxiliary 5 and 6 triggers of both counting triggers 1 and 2 are built on the elements AND-OR-NOT, respectively, 11-18.

The divider works as follows, ZOM.

in the initial state, at the outputs of elements 11, 13, 15, and 18, a zero potential appears, at the outputs of elements 12, 14, 16, and 17, a single potential, on the output bus 9, a zero potential. With the arrival of the first INPUT pulse (Fig. 2, a) on the input bus 8 to the first input of the counting trigger 1, its main trigger 3 changes its state and a unit potential appears at the output of element 11 (Fig. 2, c), and at the output of element 12, a zero potential (Fig. 2, According to the first clock pulse (Fig. 2, b), which came along the bus 10 to the counting input of the auxiliary trigger 5, it is set to the position at which the output of the element 13 appears the potential (Fig. 2, d) and at the output of the element 14 is the zero potential (Fig. 2, e). The unit potential from the output and element 1 is fed to the second (authorizing)

the counting input of trigger 2. The second input pulse translates the trigger 3 into a position where the potential of the output of element I1 is zero, and the output of element 12 is a single potential, and, moreover, entering the counting input of the main trigger 4, sets it to wherein at the output of the element

15 a single potential, dial (Fig. 2, g) is set, and at the output of the element

16 - zero potential (Fig. 2, h). The second clock pulse sets the auxiliary trigger 5 to the state when the output potential of the element 13 is set to zero potential at the output of the element 14 — the unit potential, and the auxiliary trigger 6 is in state, when the output of the element

18, a single potential is established (FIG. 2, i), the output potential of the element 17 is zero potential (FIG. 2, k). In this case, due to feedback from the output of the element 17 of the auxiliary trigger 6 to the third input of the main trigger 3, the prohibition of the passage of the third input pulse to the input of the divider is applied.

The presence of a single potential at the output of element 18, arriving at one of the inputs of the element AND-HE 7, allows each third input pulse, which arrives at the second input of the element AND-NE 7, to pass to the output bus 9, and through the feedback circuit to the input the main trigger 4 and set it to a state in which a unit potential is established at the output of element 16 and a zero potential at the output of element 15.

The third clock pulse arriving at the counting input of the auxiliary trigger 6 transfers it to a state in which a unit potential appears at the output of element 17 and a zero potential at the output of element 18, and the blocker is removed from the first digit of the splitter and is prohibited the passage of the input pulses through the element AND NOT 7.

There are no failures in the frequency divider, since it eliminates the influence of the response speeds and the duration of the fronts of the input signal by spacing the recording of input information into the main triggers of both divider bits and rewriting it into auxiliary triggers. Divider

It works reliably and allows you to use the output information and information about the state of the triggers of both bits directly without gating to build logic circuits.

Thus, when the input pulses arrive, the pulse frequency divider causes one output, i.e. divides by three.

Claims (2)

1. USSR author's certificate No. 535737, cl. H 03 K 23/02, 04.05.75 2.Bukreev I.N. and others. Microelectronic circuits of digital devices. 1973, Soviet Radio, p. 163. l and X output and FIG.