SU871338A1 - Pulse counter with recalculation coefficient - Google Patents

Description

(54) COUNTER COUNTERS WITH COEFFICIENT

Recalculation The invention relates to computing, can be used to count or divide the frequency of the pulses. A pulse counter is known, containing an Element I, a n-bit asynchronous binary counter, a decoder, an additional counting trigger, a delay element (C. A disadvantage of the known device is its relative complexity. A pulse counter with a division factor of 2 + 1 containing input bus, NOT element, AND-NOT element, multi-input AND-NOT element, n counting triggers, additionally 1st counting trigger containing six AND-NOT elements. Yyversny output every trigger is connected to the counting input of the subsequent trigger, bus scatter coupled to the reset input of flip-flops, straight outputs of which are connected to the inputs of multi-input AND-NO element, an additional input and output of which are respectively connected to the output of NOT circuit and from the counting input of the additional flip-flop, the corresponding output is connected to the inputs of the installation into a single-l

Claims (2)

+ 1 to the face of all the triggers and with the first input of the NAND element, the second input of which is connected to the input bus and to the input of the element NOT; the output of the element is NOT connected to the counting input of the first trigger 2. A disadvantage of the known device is its relative complexity. The aim of the invention is to simplify the device. To achieve this goal, in a pulse counter with a recalculation factor of 2 + 1, containing input width, reset bus, Ht element, AND-NOT multi-input element, five IS-NOT elements, and n counting triggers, the inverse output of each 1X is connected to the counting input subsequent trigger, reset bus soya nea With reset inputs. all triggers, the direct outputs of which are connected to the inputs of the multi-input element AND-NOT, the input cable is connected to the first input of the first AND-NOT element, the output of the first AND-NOT element is connected through the element NOT with account input of the first trigger and is connected with the first additional input of the multi-input element AND-NOT, the second additional input of which is connected to the output of the second element AND-NOT and the first input of the third element AND-NOT, the output of which is connected to the first input of the second element AND- NOT, the second input of which is connected to the direct output of the last counting flip-flop, the second input of the third NAND element is connected to the second input. The first element AND-NOT, with the first input of the fourth element AND-NOT and with the output of the first, the first and second inputs of which are connected respectively with the input bus and with the output of the fourth element AND-NOT, the second input of which | -o is connected to the output of the multi-input element ha and NAND with the third input of the first element NAND. FIG. 1 shows a structural electrical circuit of the meter with a counting factor equal to 9; in fig. 2 - time diagram of the work of the bank. A counter with a counting factor of 2 + 1, is made with p 3, i.e., a counting factor of 2 It contains counting triggers 1-3, the element AND-NO 4, the element NOT 5, the elements AND-NOT 6-10, the input threshold 11 and reset bus 12. The inverse outputs of the flip-flops 1, 2 are connected respectively to the counting inputs of the flip-flops 2, 3, the reset bus 12 is connected to the reset inputs of the flip-flops 1-3, the direct outputs of which are connected to the inputs of the 6-NAND element, the input bus 11 is connected to the first input of element 4 is NOT, the output of which is connected through element 5 NOT to the counting input of trigger I and is connected to the first additional the course of element 6 is AND-NOT, the second additional input of which is connected to the output of element 10 AND-NOT by the first input of element 9 AND-NOT, the output of which is connected to the first input of element 10 AND-NOT the second input of which is connected to the forward output of the counting trigger 3. The second input element 9 AND-NOT connected to the second input element 4 AND-NOT, with the first input element 7 AND-NOT and with the output element 8 AND-NOT, the first and second inputs of which are connected respectively to the input bus 11 and the output element 7 AND-NOT, the second input of which is connected to the output of the element 6 AND-NOT and from the third m input element 4 AND-NOT. ; FIG. 2 numbers 13–23 designate time diagrams of signals, respectively, on bus 11, on the outputs of elements 4, 5 AND – NOT, at the outputs of triggers 1-3 1 at the outputs of elements 6-10 AND – NOT. The device works as follows. Suppose that at the initial moment of time T1 triggers 1-3 are in the state O. When the first positive impulse arrives on bus 11, at moment T2, a negative impulse appears at the output of element 4 AND-NOT A positive pulse at the input), coordinating to the input of element 5, does not cause a positive pulse to its output, which sets trigger 1 to state 1. The second pulse appears on bus 11 in ment T4, and passes through elements 4 AND-NOT and 5 E, sets trigger 1 to state O, the positive is positive. Its potential at the zero output of the trigger 1 sets the trigger 2 to the state T. The third pulse at time 6. sets trigger 1 to state 1. After the seventh pulse arrives at time 14, triggers 1–3 appear to be state I. After the seventh pulse expires on OUR 11 at time T15, at the output of element 6 low potential, which causes a high potential at the output of element 7 AND-NOT. When the eighth pulse arrives on the bus, AND at the time T16, only positive potentials act at the input of element 8 AND-NOT, and a negative impulse appears at the output of element 8 AND-NOT. At the moment there is no negative pulse at the output of element 4, as the triggering of this element is blocked by a low potential at the output of element 6 AND-NOT and then a low potential at the output of element 8 AND-NOT. The low potential from element 8 AND-NOT also enters the input of elements 7 AND-NOT and 9 AND-NOT and causes a high potential at the outputs of these elements. The high potential from the output of element 9 AND-NOT is fed to the input of element 10 AND-NOT, and a low potential appears at the output of this element, which causes a high potential at the output of element 6 AND-NOT. The ninth impulse arrives at bus 11 at time T18 and sets all triggers in O. Low potential from a single output of trigger 3 enters the input of element 10 AND-NOT and causes its high potential at the output, which in turn causes a low potential output element 9 AND-NOT. When the next nine pulses arrive at the counter input, it works in a similar way. Thus, after the arrival of every ninth pulse, a leading edge of a positive pulse appears at bus 11 at the output of AND-NOT element 10. The invention The pulse counter with a recalculation factor + I containing an input bus, a reset bus, a NOT element, a multiple-input AND-NOT element, five AND-NOT elements and five counting triggers, the inverse output of each of which is connected to the counting input of a subsequent counting trigger, the reset bus is connected to the reset inputs of all counting triggers, the forward outputs of which are connected to the inputs of the multi-input AND-NOT element, the input bus is connected to the first input of the first AND-NOT element, characterized in that, for the sake of simplicity, the output Element I connected through a NOT element with a counting input of the first counting trigger is connected with the first auxiliary input of the multi-input element AND-NON, the second additional input of which is connected to the output of the second AND element and NAND and the first input of the third NAND element, the output of which is connected to the first input of the second NAND element, the second input of which is connected to the direct output of the last8 6 no counting trigger, the second input of the third AND NAND element is connected to the second input of the first AND NAND element, to the first input of the fourth AND NAND element and output of the fifth element IS-NOT, the first and second inputs of which are connected respectively with the input thickness and with the output of the fourth element AND-NOT whose second input is connected to the output of the multi-input element AND-NOT n with the third, the input of the first AND element. Sources and formations taken into account during the examination 1, USSR author's certificate Jf 281545, cl. H 03 K 23/00, 1970. 2. USSR author's certificate N 455494, cl. H 03 K 23/00, 1974 (prototype). ff T J n 13 ffL ff  f .. IS r., 17 f Id j 19 6 go 7 r1 in n w / J s (YIG. /