SU1167730A1 - Pulse counter-multiplier - Google Patents

Abstract

1. COUNTER-MULTIPLE. PULSES containing the triggers, the outputs of which are connected to the corresponding output tires, and the counting input of the first trigger trigger is connected to the input bus, the OR element, the first input of which is connected to the trigger output of the n-th digit, and two And, the first input of which is connected to the output of the OR element, characterized in that, in order to extend the functionality by providing multiplication factors equal to one or, where n is the number of the natural number, a control region and the NAND element, the first input of which is connected to the first input of the OR element, the output to the second input of the first element AND, the second input to the second input of the OR element and to the output of the second AND element, the first input of which is connected to the input thickness, the second input the control unit, the triggers from the first to the nth digit, and starting from (n + 1) -th, are connected in series, and the counting input of the trigger (nf 1) -th bit is connected to the output of the first element I. 2. A device according to claim 1, characterized in that, in order to exclude the selection of i elements according to the delay time signal propagation, a delay element is inserted in it, which is connected between the output of the c (L nth trigger and the first input of the OR element). 6 v

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to expand the functionality of the multiplier counter by providing multiplication factors equal to one or where n is the number of natural numbers, and also excluding the selection of elements according to the propagation delay time.

FIG. 1 shows the block diagram of the multiplier counter; in fig. 2 - time diagrams that show his work.

The multiplier counter (by example) contains triggers 1-5, the outputs of which are connected to the corresponding output buses 6, and the counting input of the first trigger 1 is connected to the input bus 7, the OR element 8, the first input of which is connected to the trigger output 2 rt- ro bit, and two elements AND 9 and 10, the first input of the first of which is connected to the output of the element OR 8, the control bar 11 and the element AND NOT 12, the first input of which is connected to the first input of the element OR 8, the output to the second input the first element And 9, the second input - with the second input of the element OR 8 and with the output of VT element 10, the first input of which is connected to the input bus 7, the second input - with a control thickness of 11, and triggers 1 and 2 from the first to the “th digit and triggers 3-5, beginning with the discharge), are connected sequentially, and the counting input of the trigger 3 (n + 1) -th bit is connected to the output of the first element And 9, in addition, in series with the triggers 1 and 2 may be included a delay element 13, made, for example, in the form of a resistive-capacitive circuit .

The device operates as follows (when the multiplier counter has a multiplication factor of 1 or 2 - f 1 5).

In the multiplication mode by "1, the bus 11 is supplied with the level" O (logical), while the output of the element 10 is set to the level "O and the element 12 -" 1. In this case, the output of flip-flop 2 is connected (via elements 8 and 9) with the counting input of flip-flop 3, i.e. a conventional pulse counter is formed. In the multiplication mode by 5, the level 11 is applied to the slit 11, while the pulses arriving at the slit 7 (Fig. 2a) pass through elements 10 and 8 (Fig. 2e, e) to the first input of element 9 and through element 10 - to the second input element 12.

Suppose that all the triggers of the multiplier counter (Fig. 2b, b, k, l, m) are set to “O, then at the output of element 9

(Fig. 2i) there is also an "O. Positive pulses coming to bus 7 switch simultaneously triggers I and 3. The first and second input pulses through 5 elements 10, 8 and 9 arrive at the counting input of trigger 3 without changing polarity, because element 12 is blocked by the level "O from the output of trigger 2 ( through the delay element 13), and its output is set to level “1.

0 After the passage of the first pulse, the triggers 1 and 3 are set to the state "1, in women 6 of the multiplier counter, the code 00101 is set (the younger bit on the right), the corresponding one; after the second pulse passes, the triggers 2 and 4 are set to the state 1 and 3 - the code 01010 corresponding to 2X5 is set to the state "O and on the bits of the multiplier counter. After the second pulse passes, the output of element 9 is set to level" 1, since at its inputs the levels "1 from the output of trigger 2 are set through element 8 and from the output element 12.

Third and fourth input pulses

5 through elements 10, 12 and 9 arrive at the counting input of trigger 3 with a changed polarity, i.e. negative polarity, and trigger 3 is triggered from the front of these pulses. After the passage of the third pulse, the triggers 1-4 are set to the state "1" and the code 01111 is set on the women of the 6 multiplier counter.

With the passage of the fourth pulse

from its front, trigger 3 is set to the "Oh, causing the setting

trigger 4 and 5 to the state of "O and" 1

respectively.

From the fall of the fourth pulse, trigger 1 is set to state "O", causing trigger 2 to also be set to state "O, and a negative differential is generated at the output of trigger 2 (Fig. 2c). This negative differential through element 13 (FIG. 2d) and element 8 (FIG. 2e) 5 arrives at the first input of element 9 and causes a negative differential (FIG. 2i) at its output, delayed relative to the decay of the fourth pulse. From this negative differential, the trigger 3 is set to the state "1, and thus the fourth pulse changes the state of the trigger 3 twice.

After the passage of the fourth pulse, a corresponding code 10100 is set at the pulse multiplier. Subsequently, every fourth pulse from the sequence of pulses on bus 7 causes a double triggering of trigger 3, with the second

the triggering is transferred to the most significant bit when the binary counter consisting of triggers 1 and 2 is overflowed.

Thus, each input pulse records in the multiplier counter the number “5, i.e., multiplying the number of input pulses by“ 5.

In order for the device to function properly, two conditions must be met:

t, (tn + t, 3 + t8-ft9) - (t | o + t, 2 + t9), i, (tn-f tis + tg + tg) - (tlO + ts + te),

tj is the switching delay of trigger 3; tn is the switching delay time of the flip-flops 1 and 2;

io, ti2, ti3 are the signal propagation delay times, respectively, in elements 8-10, 12, and 13. If the above conditions are met, then element 13 can be excluded from the device.

Claims (2)

1. COUNTER-MULTIPLIER PULSES, containing triggers, the outputs of which are connected to the corresponding output buses, and the counting input of the trigger of the first category is connected to the input bus, an OR element, the first input of which is connected to the output of the trigger of the 1st category, and two elements And, the first the input of the first of which is connected to the output of the OR element, characterized in that, in order to expand functionality by providing multiplication factors equal to unity or 2 * 4-1, where n is the number of the natural series, a control bus and an electric bus are introduced into it the AND-NOT ment, the first input of which is connected to the first input of the OR element, the output - to the second input of the first AND element, the second input - to the second input of the OR element and the output of the second AND element, the first input of which is connected to the input bus, the second input - with the control bus, and the triggers from the first to the ηth digits, and starting from the (n + 1) th, are connected in series, and the counting input of the trigger of the (n + 1) th bit is connected to the output of the first element I. 2. The device according to π. 1, characterized in that, in order to exclude the selection of elements according to the propagation delay time of the signals, a delay element is inserted into it, included between the output from the ηth trigger and the first input of the OR element. FIG. / I 167730