SU1195437A1 - Device for selecting first and last pulses in pulse burst - Google Patents

Abstract

CONSTRUCTING THE FIRST AND LAST PACKAGE PULSE SELECTION containing the inverter five elements AND, two triggers, delay element, pulse counter, driver of the pulses on the front, the device input connected to the first input of the first element AND, and through the inverter to the first input of the second element And To the second input of which the output of the delay element is connected, the first output of the first trigger is connected to the second input of the first element I, the output of the second trigger is connected to the first input of the third element I, which is o, in order to increase reliability and enhance functionality by providing work with a varying period of pulses in a pack, a clock pulse generator, a second pulse generator, an OR element, a sixth, seventh and eighth AND elements, a pulse shaper were introduced: downward , while the device input is connected to the first input of the fourth element I, the output of which through the pulse shaper but the front is connected to the second pulse counter, the first output of which. connected to the first input n of that. element I, the second output to the second input of the fourth element I and the first input of the sixth element I, the output of the clock generator is connected to the second inputs of the fifth and sixth elements I, the outputs of which are respectively connected to the first input of the first pulse counter and to the first input of the 1g delay element , the group of outputs of the first screw is connected to the group of inputs of the delay element, the output of the first element AND is connected to the first input of the first trigger ((the second output of which is connected to the first input of the seventh element AND, you The second one is connected to the first input of the second trigger, the output of the second element I is connected to the second input of the seventh element I and to the first input of the eighth element I, the second input of which is connected to the first output of the first trigger, and the first input of the OR element, the second input of which is connected to the output of the first pulse counter, the output of the support element is connected to the third input of the first element AND and the second input of the third element AND whose output is connected to the second input of the first trigger through the driver pulses in decay to the second input of the second trigger and through the third input of the OR element to the installation inputs of the pulse counters.

Description

one ...

This invention relates to pulsed tech. nickname and can be used in information processing devices ..

The aim of the invention is to increase the reliability of the device in operation and to expand its functionality by providing work with a varying period of pulses in the packet due to automatic tuning.

Fig. 1 shows a block diagram of a device for isolating the first and last pulses in a packet; 2, time diagrams of the operation of its elements.

The device contains evil And. 1-8, an inverter 9, a delay element 10 made on the basis of a frequency divider, counters 11 and .12 pulses, a generator of 13 clock pulses, triggers 14 and 15, a driver of 16 pulses at the front, a driver of decay pulses and a IL 18 element.

The device input is connected to the first inputs of the AND 1 and 2 elements and through the inverter 9 to the first input of the AND 3 element. The output of the AND 2 element is the first output of the device and connected to the first input of the trigger 14, the first output of which is connected to the second input of the 2 element And the first input element 8 And, and the second output with the first input element And 6, the output of which is connected to the first input of the trigger 15. The output of the trigger 15 is connected to the first input of the element And 7, the output of which is connected to the second input of the trigger 14 and the second output of the device.

The output of the element 3 is connected to the second inputs of the elements 8 and 6. The output of the element 1 through the driver 16 is connected to the first input of the counter 12, the first output of which is connected to the first input of the element 4 and the second is connected to the second input of the element 1 and 1 the input element And 5. The output of the generator 13 is connected to the second inputs of the elements 4 and 5, the outputs of which are respectively connected. to the first inputs of the counter 11 and the delay element 10.

The output groups of the counter 11 are connected to the corresponding group of inputs of the delay element 10. The outputs of the element AND 8 and counting 11 are respectively connected to the first and second inputs of the element OR 18. The output of the element AND 7 through the third input of the element OR 18 is connected to the installation inputs of the counters 11 and 12 and through the driver 17 to the second input of the trigger 15.

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The device operates as follows: The impulse arriving at the input of the device enters through the element I 1, which is open with potential from the output of counter 12 to

5 to the inverse input, to the input of the imager 16, which forms a short pulse along the front of the input pulse. The pulse from the output of the imager 16 is stored in the counter 12, and on the first output of the counter 12

10, a single potential appears, opening up-. And 4, through which the input of the counter 11 receives pulses from the generator 12. The counter And works until the second pulse arrives at the device input, and

15, the number of pulses corresponding to the period of the input pulse sequence is entered into counter 11. If, before the device arrives at the input of the second pulse (Fig. 2a), the counter

20 11 overflows, the first Pulse is perceived as single, and the overflow pulse of counter 11 through the OR 18 element resets counter 12 to the initial state. Thus, at the outputs of the device is not

25, a single pulse at its input appears.

If the second pulse arrives before the counter overflows 11 (Fig. 28), the shaper 16 is started, the pulse from the output of which is entered into the counter 12, and the unit potential from its first output disappears, closing element 4, but appearing the second output, opening the element And 5. At the same time, the unit potential at the second output of the counter 12 closes the element And 1. Through the element 5, the pulses from the generator 13 begin to arrive at the input of the element 10 delay. The delay time is defined by a code from the outputs of the counter I. After a time corresponding to the follow-up period of the input pulses, a pulse appears at the output of the delay element 10, which is fed to the inputs of the And 2 and 3 elements. The And. 3 element is at this time a fixed zero potential the output of the inverter 9, and the element AND 2 - an open potential from the output of the trigger 14 one at a time and one input, a pulse through the other inputs resulting in the third pulse of the sequence passing to the output of the element AND 2, which is the first output of the device, as e of the first pulse sequence, - and also input to the flip-flop 14, it knocks than relieves permitting al potentsi55 with AND elements 2 and 8 and the element 6 opens I.

If the third pulse is not fed to the input of the device (Fig. 2, B) then the pulse with

five

the output of the delay element 10 passes through the AND 3 element, the unit potential opened at that time from the output of the inverter 9, the AND 8 element opened by the trigger 14, and the OR 18 element to the installation inputs of the counters 11 and 12, resetting them to the initial state.

If, after the third pulse, the device continues to receive pulses (Fig. 28), the sequence of which has not changed, they are perceived by the device as belonging to the input sequence.

At the end of the input pulse sequence, the element And 3 remains open potential from the output of the inverter 9 to the time of the occurrence of the pulses from the output of the 54.

delay 10 (fig. 2fi). This impulse, having passed through elements 3 and 6, acts on trigger 15 in such a way that, as this impulse decays, trigger 15 turns over, opening element 7. The next impulse from the output of delay element 10 passes through element 7, which The second output of the device, as the last pulse, the input of the 0 sequence, simultaneously this pulse resets the trigger 14, and through the OR element 18 - counters 11 and 12 to the decay through the driver 17, the trigger 15. Thus, the device selects first and last dny pulses in a pack and is ready for re-use.

figure 1

5 Vut.Z

Claims (1)

DEVICE FOR ISOLATING THE FIRST AND LAST PULSE IN A PACK, containing an inverter of five AND elements, two triggers, a delay element, a pulse counter, a pulse shaper along the edge, and the device input is connected to the first input of the first AND element and through the inverter to the first input of the second AND element, to to the second input of which the output of the delay element is connected, the first output of the first trigger is connected to the second input of the first element And, the output of the second trigger is connected to the first input of the third element And, because of the fact that, with c In order to increase the reliability of work and expand the functionality by providing work with a changing pulse repetition period in a packet, a clock pulse generator, a second pulse counter, an OR element, sixth, seventh and eighth AND elements, a pulse shaper on the decline are introduced into it, and the device input connected to the first input of the fourth element And, the output of which is through the pulse shaper along the edge, connected to the second pulse counter, the first output of which. . connected to the first input of the fifth element And, the second output 'to the second input of the fourth element And and the first input of the sixth element And, the output of the clock generator is connected to the second inputs of the fifth and sixth elements And, the outputs of which are respectively connected to the first input of the first pulse counter and to the first input of the delay element, the group of outputs of the first counter is connected to the group of inputs of the delay element, the output of the first element And the keys to the first input of the first trigger, the second output of which is connected to the first the seventh element And, the output of which is connected to the first input of the second trigger, the output of the second element And is connected to the second input of the seventh element And to the first input of the eighth element And, the second input of which is connected to the first output of the first trigger, and the output - to the first input OR element, the second input of which is connected to the output of the first pulse counter, the output of the delay element is connected to the third input of the first element And and the second input of the third element And, the output of which is connected to the second input of the first trigger, the decay of the pulse shaper to the second input of the second flip-flop, and via the third input of the OR member to the locating pulse counter inputs. . SU1195437 * - 1195437