SU375651A1 - FREQUENCY-PULSE MULTIPLE-PERFORMANCE DEVICE- ^ - Google Patents

Description

one

The invention relates to the field of computer technology and can be used to perform multiplying-dividing operations on variables represented by a pulse repetition frequency, as well as a device for generating a unitary code for the ratio of two frequency sequences.

A pulse-frequency multiplying-separating device is known, which contains two triggers and impulse-potential coincidence circuits.

Obtaining a pulse sequence at the output, formed from the frequency FI, only after the arrival of the pulse frequency FZ increases the variance of the error of the output signal as a result of the ripple “pulse packet at the output by the value of the period frequency p2.

The purpose of the invention is to receive at the output of the device pulses formed from the FI frequency immediately after the arrival of the FS frequency pulse due to the preliminary memorization of the number of FI pulses in the FZ period and their write off with the PI frequency with the arrival of the FS frequency pulse.

This is achieved in that the device further comprises a third, fourth, fifth, and sixth coincidence circuit, a differential chain, and a reversible counter.

A memory ratio of frequencies in each period of the frequency FZ. The output of the reversible counter through the coincidence circuit is connected to a trigger, the output of which controls the passage of the frequencies FZ and FI.

The drawing shows a diagram of the device. The device contains triggers 1 p 2, reversible counter 3, schemes 4-9,

differentiating chain 10.

The input frequency bus Fi is connected to the output of the trigger unit installation /, the single output of which is connected to the inputs of the matching circuit 7 and 9. The second input of the latter is connected to the input frequency bus FZ and the input of the matching circuit 8, another input connected to the zero output of the trigger / and the input of the matching circuit 6, whose second input is connected to the input frequency bus

FS and the input of circuit 7 are matches. The output of the coincidence circuit 6 is connected to the summing input of the reversible counter 3, and the zero outputs of its triggers are connected to the input of the coincidence circuit 4, the output through the differentiating

chain 10 connected to the input of the zero setting trigger.

The zero setting bus of the reversible counter 3 is connected to the output of the coincidence circuit 8 and to the installation input of the trigger 2,

another setup input of which is connected 3 to the output of the coincidence circuit 9. The output of the trigger 2 is connected to the input of the matching circuit 5, connected by an output to the subtracting input of the reversible counter 3, and a second input connected to the output of the matching circuit 7 5 and the device output bus. Consider the operation of the device since the arrival of the FZ frequency pulse, assuming that both the flip-flops 1, 2 are in the zero state, confirms the zero state of the trigger 2 and sets the reversing counter 5 to the zero state. open circuit 6 matches arrive at the sum input of the reversing counter 3.15. If the current frequency FZ is applied to a pulse of frequency FI, then the trigger 1 is set to one, allows the passage of FS pulses to the output of the device, prohibits Driving 20 pulses of frequency Fa through a matching circuit 6 to the summing input of the reversible counter, in which tn FS frequency pulses are recorded at this time, prohibits the reset of the FZ frequency pulses of the reversing counter B25 zero, allows the passage of the FZ frequency pulse to the trigger unit installation input 2.. The incoming frequency pulse FZ (the first 30 after the frequency pulse Fi) enters through the open circuit 9 of coincidence at the installation input of the trigger unit 2, the output potential of which permits the passage of the output frequency pulses to the subtracting35 reversible counter input. During the time between the pulse Fi and the pulse FZ that arrived later, the input of the device / P is applied (- from j pulses; the next 40 output pulses, the passage of coincidence circuit 5, is removed from the reversible counter m of the stored pulses. When the reversible counter is zeroed, the pulse The 45th differentiated chain Yu, from the voltage drop at the output of the circuit 4, coincides with the trigger 1 for the zero state, prohibits the arrival of 3 frequency pulses at the output of the device, and 50 pulses of the frequency FZ for the single input of the trigger 2 and t the passage of pulses of the frequency of the relay to the summing input of the reversible counter and the pulses of the frequency FZ to the 4th input of the zero setting trigger 2 and the zero setting bus of the reversible counter. Thus, j-pulses generated from the (N-t) pulses in the gap are output to the device time T2 between the frequency pulse FI and the later arriving frequency pulse FZ, lt pulses, which arrived at the reversible counter during the time TI between the frequency pulse FZ and the frequency pulse Fi that passed in this period FZ. Moreover, m pulses are output after () pulses. The invention The pulse-frequency multiplying-dividing device contains the first trigger, one installation input of which is connected to the bus of the first input frequency, and its single output is connected to the input of the first coincidence circuit, the other input of which connected to the bus of the second input frequency, and the output to one of the setup inputs of the second trigger, and a second coincidence circuit, one of the inputs of which is connected to the bus of the third input frequency, characterized in that reduce the variance of the error of the input sitnal, the device additionally contains the third, fourth, fifth and sixth, th | coincidence circuit, differential chain and reversible counter, zero setting bus connected to another installation input of the second trigger and output of the third coincidence circuit, one input of which is connected to the second input frequency bus, and the other to the single output of the first trigger coincidence, the output of which is connected to the summing input of the reversible counter, and the other input - to the bus of the third input frequency; the other input of the second coincidence circuit is connected to the zero output of the first trigger, and its output is connected to one of the inputs of the fifth coincidence circuit, the other input of which is connected to the zero output of the second trigger, and the output of the fifth coincidence circuit is connected to the subtracting input of the reversible counter, zero outputs the flip-flops of which are connected to the inputs of the sixth coincidence circuit, the output of which through a differentiating chain is connected to another installation input of the first flip-flop.

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