SU1487179A1 - Device for counting pulses - Google Patents

Description

The invention relates to a pulse technique and can be used in measuring time intervals. Target2

retenium - improving the accuracy of the account. The device contains a “-bit subtractive counter 1, the first and second groups of m elements And 2.1 ... 2 /// and 3.1.,. 3 / n, respectively, / n + 1 frequency dividers 4.1 ... 4pg + 1, installation input of each A-go where A = 1, 2, H ... / η of which, except the first one, is connected to the output of the corresponding A — 1st element AND of the first group, and the outputs of the frequency dividers, except the last, are connected to the first the inputs of the corresponding elements And the second group. The output will be generated code approximated dependence where η-number of the next

input pulse. 1 il.

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1487179

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The invention relates to a pulse technique and can be used in measuring time intervals.

The purpose of the invention is to improve accuracy.

The drawing shows a diagram of the device.

A device for counting pulses contains an “-bit subtracting counter 1, the first and second groups of m elements 2.1-2T and 3.1 — 3m, respectively, - the output of each previous element AND of the first group is connected to the first input of the subsequent element AND of the first group. The device also contains m + 1 frequency dividers 4.1–4. M + 1, the setup input of each of which, except the first one, is connected to the output of the corresponding K — 1st element AND of the first group, the clock inputs are connected to the clock input of the detracting counter 1 and are input 5 devices, the outputs of the frequency dividers, except the last one, are connected to the first inputs of the corresponding elements And 3 of the second group, the second inputs of which are connected to the information inputs of the corresponding frequency dividers and for each previous element And the second group are connected us corresponding to the output of the subsequent element of the same group. The inverse output of the “th digit of the detracting counter is connected to the first input of the first element AND 2.1 of the first group and to the installation input of the first divider 4.1 frequency, the second input of each gth element AND of the first group is connected to the corresponding η-ΐ-t inverse output of the detracting counter, the output of the last frequency divider is connected to the second input of the t-th element of the second group, the output of the 1st element of the second group is connected to the resolution enable input of the subtractive counter, the direct outputs of which are the outputs of the device.

The drawing shows a diagram of the device for the case t = 3.

The device works as follows.

Pulse subtraction counter 1 - synchronous counter with the transfer input. Dividers of 4 frequencies can be performed each on two K – Y triggers and ensures each division of the frequency of the pulses into four. In the initial state, the code of the output number of the subtractive counter of 1 pulses is maximum - Ν. At the same time, on the inverse outputs of the subtracting counter 1 of the pulses there is a logic zero level, which keeps the dividers 4 frequencies in the state of a logical unit on the output directly, \ on the input (divider 4.1), or through the AND 2 elements. At the same time, the transfer input 1 pulses (output of element 3.1 and) there is a level sig4

pulse resolution enablement. Thus, each pulse of input 5 will decrease the output number by one. As soon as the high bit of the subtracting counter of 1 pulses is switched, the logical unit level will appear at the installation input of the frequency divider 4.1, allowing its operation, while the other dividers 4.2-4t, 5.2-5t will remain off. Thus, the resolution potential will be formed at the transfer input of pulse counter 1, every fourth pulse repetition period at input 5 and the code of deducting pulse counter 1 will decrease by one for every fourth pulse from input 5. When the code of the deducting pulse counter becomes equal to 77/4 , the second digit will also change its state on the part of the elders, which will cause the potential of the logical unit to appear at the installation input of the frequency divider 4.2. As a result, the frequency divider 4.2 will turn on and at the transfer input of the subtractive counter 1 pulses a resolution impulse will be generated, with a duration of one signal period from input 5 and a duty cycle of sixteen. Thus, the subtracting counter 1 pulses will reduce the steepness of reducing the code by another four times. Further, frequency dividers 4.3, 4.4 will be included in the work, with a corresponding change in the potential of the third and fourth discharges, from the senior, subtracting counter 1 pulses. Thus, the output will form the code of the approximate dependence Y = 1 / “, where n is the number of the next input pulse.

Claims (1)

Claim A device for counting pulses, containing an “-bit subtractive counter (“ = 2.3 ...), the first and second groups of m elements I (m <“, m = 1.2, 3 ...), the output of each previous element And the first group is connected to the first input of the subsequent element And the first group, characterized in that, in order to improve accuracy, m - (- 1 frequency dividers, the setting input of each / (- go (where / (= 1.2 , 3 ... t) of which, except the first one, is connected to the output of the corresponding K-1-th element AND of the first group, the clock inputs are connected to the clock input of the subtractive counter and are the device input, the outputs of the frequency dividers, except the last, are connected to the first inputs of the corresponding elements AND the second group, the second inputs of which are connected to the information inputs of the corresponding frequency dividers and the output of the subsequent element And the same group, the inverse output of the nth digit of the detracting counter is connected to the first entrance of the first 1487179 element of the first group and to the setup input of the first frequency divider, the second input of each ι-th element of the first group (r = 1.2 ... t) is connected to the corresponding n — r'th inverse output of the subtracting counter, the output of the last divider frequency is connected to the second input of the / lth element And the second group, the output of the first element And the second group is connected to the resolution enable input of the subtractive counter, the direct outputs of which are the device outputs.