SU1274135A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation devices and computing technology. The purpose of the invention is the expansion of functionality. To achieve this goal, two elements are introduced into the device: SPEAK 1AUTSEE OR 3 and 4. In addition, the device contains two D-flip-flops 1 and 2. The introduction of these elements with corresponding functional connections allows you to increase the functionality of the device. Moreover, the device ensures the allocation of a single pulse depending on the state of the mode selection bus, a single or zero half cycle of the clock sequence. 1 il. (L С С) 5 m to D С yD - С 4: ro О1 0 В 1 fut.f

Description

The invention relates to a pulse technique and can be used in automation devices and computing techniques.

The purpose of the invention is to expand the functionality by highlighting and depending on the state of the W1-WY mode selection, single or zero half-cycle clock sequence.

FIG. 1 shows the electrical functional diagram of the device; in fig. 2 - time diagrams, according to his work.

A device for separating a single pulse contains two triggers 1 and 2, each of which is D-type, two elements 3 and 4 EXCLUSIVE OR, the first input of the first of which is connected to the mode selection bus 5, the second input from output 6, and so on the output of the first trigger 1, the output to the first input of the second element 4 EXCLUSIVE OR, the second input of which is connected to the bus 7 clock pulses, the output to the C input of the first trigger 1, the D input of which is connected to the direct output of the second trigger, The C input of which is connected to the control bus 8, the D and R inputs are inverse th output of the first trigger 1, the R-input of which is connected to the blocking bus 9. The device works as follows. Let the bus 5 present level of logical zero (figv). The second input of the first element 3 from the direct output of the trigger 1 receives the level of logical zero (Fig. 2e). At the output of the element 3 there is a logical zero level (FIG. 2e). The polarity of the clock pulses arriving at the C input of the trigger 1 from the output of element 4 (Fig. 2g) coincides with the polarity of the pulses on the bus 7 (Fig. 2a). On the positive differential of the control signal coming from the bus 8 (Fig. 2b), the trigger 2 is set to one (Fig. 2d) and the level of the logical unit appears on the D input of the trigger 1 (Fig. 2d). According to the positive differential of the first tact after that; trigger pulse 1 is set to one (Fig. 2e). Level of logical zero, which appeared on the inverse output trigger

1 enters the R input, trigger 2, and sets it to the zero state (Fig. 2d). At the D input of trigger 1, a logic level is set

zero The level of the logical unit received from the direct output of the trigger 1 to the second input of the element, 3, causes the appearance of the level of the logical unit at its output (Fig. 2e).

The polarity of the clock pulses coming from the bus 7 through the element 4 to the C input of the trigger 1 is reversed (Fig. 2g). By the negative differential of the first clock pulse

(Fig. 2a) trigger 1 is set to the zero state. At the second input of element 3, a logical zero level appears again and the circuit returns to its initial state.

Thus, on the bus 6, a pulse is formed corresponding to the positive pulse of the input clock sequence (Fig. 2e).

Suppose now that there is a logical unit level on bus 5 (Fig. 2c). In this case, at the output of element 3, the level of a logical unit appears (Fig. 2e). The polarity of the clock pulses arriving at the C input of the trigger 1 (Fig. 2g) is reversed compared with the polarity on the bus 7 (Fig. 2a). By a positive signal differential on bus 8 (Fig. 26), trigger 2 is set to one (Fig. 2d). According to the first negative clock differential following this (Fig. 2a), trigger 1 is set to one (Fig. 2e). The second input of element 3 receives the level of the local unit, the output of this element is set to the level of logical zero (Fig. 2e). The polarity of the clock pulses at the output of element 4 is reversed (Fig. 2g). The zero level received from the inverted output of trigger 1 to the R input of trigger 2 sets the latter to the zero state (Fig. 2d). On the positive differential clock pulse with. bus 7, the first trigger I is set to 8 a zero state (Fig. 2e), the second input of element 3 receives a logic zero level (Fig. 2 e) and the circuit returns to its initial state. On tire 6, im312741 will be generated.

pulse corresponding to zero half-cycle of the input clock sequence (Fig. 2e).

Claims (1)

Claims. A device for extracting a single pulse containing two flip-flops, each of which is D-type, the D input of the first of which is connected Q to the direct output of the second trigger, the C input of which is connected to the control bus, the clock pulse bus and the output bus differing from In order to expand 54 functionality, a mode selection bus, a blocking lock, two elements are introduced. The first input of the first one is connected to the mode selection bus, the second input is connected to the output bus and the first output of the first trigger, the output is to the first input the second element of the NSKPKNAKCHCHE OR, the second input of which is connected to the clock pulse bus, the output -.c with the G-input of the first trigger, the R-input of which is connected to the blocking bus, inverse. output - with R- and D-inputs of the second trigger.