SU1338061A1 - Scale-of-ten synchronous circuit - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency synthesizers. The purpose of the invention is to increase the speed of the synchronous frequency divider. achieving the goal, the bus 9 of a logical unit has been additionally introduced into it. The proposed frequency divider for 10 is made on four 1K-triggers 1-4 and one logical element AND 5, has an input bus 6, a reset bus 7 and an output I-I (8 or transfer bus) 8. I and K are connected to bus 9 trigger inputs 1. The operation of the synchronous dividers by 10 is temporarily explained by the diagram given in the description of the invention, where the logical equations for the I and K inputs of all IK triggers are also indicated. 2 Il. t sl 8 00 oo 00 about 05 FIG.

Description

The invention relates to a pulse technique and can be used in frequency synthesizers.

The purpose of the invention is to increase speed.

Fig. 1 is an electrical functional diagram of the device; 2 shows timing diagrams for his work.

Synchronous frequency divider by 10 contains the first., The second, third and fourth 1K-triggers 1-4 and the element And 5; The C and R inputs of all 1K flip-flops are connected respectively to the input bus by a bus 7 reset; the output of the element 5 is connected to the output bus 8 (transfer bus), the first input is connected to the direct output of the first 1K trigger 1, the I and K inputs of which are connected to the bus 9 logic unit 1, the inverse output from 1 - the input of the second 1K flip-flop 2, the direct output of which is connected to the I- and K-inputs of the third 1K-flip-flop 3, the inverse output to the second input of the And 5 element and to the 1-input of the fourth 1K-flip-flop A; the inverse output of the third 1K-flip-flop 3 is connected to the 1-input of the fourth IK-flip-flop 4, the direct output of which is connected to the K-input of the second IK-flip-flop.

The logical equations for the I- and K-inputs of the 1K-flip-flops and the transfer signal to the bus 8 will be: 1. 1 "Q ,,; 1, Q

 2 4 3

P Q, Q ,,

where means that these inputs are connected to bus 9 of a logical unit.

The device works as follows.

. 1, Q ,,; 1, QJ; 1, Q: К К; Q ;; K, Q,

K4 Q7.

A synchronous frequency divider by 10, containing the element I, the output of which is connected to the output bus, and the second, third, third and fourth IK triggers, the R and C inputs of which are connected

The signal Reset, coming in the form of a pulse on the bus 7 before the start of 45, respectively, with the reset bus work ;, the device is installed with the input bus, the inverse output

to the initial zero state - all 1K triggers 1-4 are set to the logical zero state, and

The first IK flip-flop is connected to the 1-in of the second 1K-flip-flop, the K-input of which is connected to the direct output of the fourth 1K-flip-flop, the 1-kot input is connected to the inverse output of the third 1K-flip-flop, characterized in that In order to improve speed, a logical 1C1 bus was introduced into it, which is connected to the T and K inputs of the first 1K flip-flop, the direct output of which is connected to the first input of the element. And the second input of which is connected to the device's output will be zero (Fig.2 ):

Q 0; Qj 0; Q, 0; Q 0;

P Q, q ,, 0.

In this case, in accordance with the logical equations for the I, K inputs of 1K triggers 1-4, the states of the inputs will be as follows:

1.1; 1, Q. one; 1, Qj 0; I,

Qi 1;

ten

15

u

- 40

3380612

K, 1; Kj Q O; K Q 0; K,

 Qz 1.

 Since the next pulse on the bus b (Fig. 2c) 1K-flip-flop changes its state when I 1 and K I switches to the opposite state, when I 1 and K O turns into the state of logical one, and when I O and K 1 are in the state of logical zero, then the first pulse on the bus 6 1K-flip-flops 1, 2 and 4 switch to the state of logical one, and the IK-flip-flop 3 will not change its zero state. The state of the outputs will be equal (figure 2 with)

Q, I; Q, 1; Q3 0; one; n 0.

The state of the inputs is also changed except for the 1K-trigger 1):

1, I; Ij 0; lj 1; eleven; K, I; K ,, 1; Cs 1; To 0.

With the arrival of each successive impulse to the bus 6, the 1K-flip-flop states 1-4 change in accordance with the above algorithm.

When the signals coincide, Q I and Q, | I, in

thirty

35

: ,,, resulting in the output of element 5 through Wits, the signal P Q, QT 1, the value of which is held for only one clock cycle, i.e. the duration t of the transfer impulse will be equal to the duration t of the pulse follow-up period on bus 6. Then the device repeats is,

Claims (1)

Invention Formula A synchronous frequency divider by 10, containing an element And, the output of which is connected to the output bus, and the first, second, third and fourth IK-triggers, the R- and C-inputs of which connect m 45 respectively to the reset bus and the input bus, inverse output 0 five The first IK flip-flop is connected to the 1 input of the second 1K flip-flop, the K-input of which is connected to the direct output of the fourth 1K flip-flop, the 1-input of which is connected to the inverse output of the third 1K flip-flop, which is designed to improve speed A bus of logic unit 1Cz1 is inserted into it, which is connected to the T and K inputs of the first 1K-flip-flop, the direct output of which is connected to the first input of the And element, the second input of which is connected to the inverse output of the second 1K-Trigger, the direct output of which is connected to Editor A.Makovska Compiled by A.Sokolov Tehred I.Popovich Proofreader A.T. Order 4145/56 Circulation 901 Subscription VINILI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 I- and K-inputs of the third 1K-flip-flop, and with the K-input of the fourth 1K-flip-flop, 7 23US6789 (ig.2