SU1341635A1 - Frequency-multiplier - Google Patents

Abstract

The invention relates to automation and computing, in particular to specialized multiplying devices. The purpose of the present invention is to reduce hardware costs. The frequency multiplier contains two counters 1-2, two selectors 3, 4, a comparison circuit 5, a pulse shaper 6, two elements. 7.8 delays. 2 Il. / $ (L M / / V 8 U-T // oo 4 o: oo SG1 Fig. 1

Description

1134

The invention relates to automation, computing, and in particular to specialized multiplying devices.

The purpose of the invention is to reduce hardware costs.

FIG. 1 shows a functional multiplier circuit; in fig. 2 - time diagrams of work.

The frequency multiplier contains the first 1 and second 2 counters, the first 3 and second 4 selectors, the comparison circuit 5, the pulse shaper 6, the first 7 and second 8 delay elements, the input frequency bus 9, the multiplier code input 10 and the multiplier output 11.

The frequency multiplier works as follows.

In the initial state, the counters 1 and 2 are zeroed (Fig. 26, d) at the inputs of the comparison circuit 5 - the equality of potentials (). The information inputs of the selectors 3 and 4 receive the code N. When a single potential appears at the input 9 (Fig. 2a, i), the codes through the selectors 3 and 4 are recorded in counters 1 and 2 and fed to the inputs of the comparison circuit 5. At its output at the time of the inequality of the codes (N;, N, -, 2), a potential drop is formed over a period of time about. Through time C, the potentials of the codes are equal (N, N, 2), and 1 is generated at the output of the comparison circuit 5 (Fig. 2a). The counter 2 switches over with some delay o. At the moment of switching the counter 2 at the inputs of the comparison circuit 5, the potential inequality appears (,., I N;), at the output of the comparison circuit 5 the observed 52

There is a drop in potential. After some time specified by the delay element 8, the counter 1 switches and the potentials (N N ;,) appear at the inputs of the comparison circuit 5. The cycle is repeated.

When zeroing counters 1 and 2, the frequency multiplier is set to

initial state. The output frequency is Fg ,,, F, -N.

Claims (1)

Invention Formula A frequency multiplier containing two counters, characterized in that, in order to simplify the multiplier, a comparison circuit, two delay elements, a driver pulses and two selectors, the input frequency bus of the multiplier is connected to the input of the pulse generator, the output of which is connected to the input of the first delay element and the control input of the first selector, whose information input is connected to the input of the multiplier code and to the information input of the second selector, the control input of which connected to the output of the first delay element; the outputs of the first and second selectors are connected to the information inputs of the first and second counters, respectively, the outputs of which are connected to the first and second inputs of the comparison circuit, the output of which is the multiplier output and connected to the subtracting input of the second counter and the input of the second delay element whose output is connected to the subtractive input of the first counter. 0) n S)  i) e) Well 1PLS Compiled by N.Markelova editor E.Kopcha Tehred M.Didyk Proofreader N, King Order 4437/52 Circulation 672 Subscription VINILI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, ul, Proektna, 4