SU1757098A1 - Recalculation circuit in fibonaci code - Google Patents

Abstract

The invention relates to a pulse technique and can be used for multi-bit reverse conversion of pulses in a minimum Fibonacci code with P 1. The purpose of the invention is to expand the functionality and scope by providing inverse order of conversion. The scheme contains three triggers 1-3, connected to the reset input 4, six elements 5, 6, 17-20, two elements Р ЗИ-ИРИ 13,14, element 4И-OR 15, element OR 8, element NOT 10 and two elements EXCLUSIVE OR 21, 22 and has a counting input 7, control inputs 11, 24, 25, control outputs 12, 26, 27, transfer output 9, two tires 16, 23 operating mode selection. 2 ml, 2 tab.

Description

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The invention relates to a pulse technique and can be used for multi-bit reverse conversion of pulses in the minimum Fibonacci code with P 1.

A known recalculation scheme in the Fibonacci code, containing in each bit a counting trigger, AND elements, and OR elements.

The drawbacks of this scheme are the complexity and narrow functionality consisting in recalculation only in the order,

The closest in technical essence to the proposed is a Fibonacci conversion circuit containing the first, second and third triggers, the reset inputs of which are combined and connected to the reset input of the conversion circuit, the first and second elements AND, the first inputs of which and the sync inputs of all the triggers are combined and connected to the counting input of the scaling circuit, the OR element, the first and second inputs of which are connected to the outputs of the first and second And elements, respectively, and the output with the transfer output of the scaling circuit, the element NOT, the first channeling yuschy input and a first control output, and the second and third inputs of first AND gate connected respectively with the outputs of the first straight and third flip-flops, the second input of second AND - The direct output of the second flip-flop.

The disadvantages of the known scheme are the narrow functionality and the scope of application, which is in recalculation only in the right order.

The purpose of the invention is to expand the functionality and scope by providing recalculation, also in the reverse order of recalculation,

The goal is achieved by the fact that the scaling circuit in the Fibonacci code, containing the first, second and third triggers, the reset inputs of which are combined and connected to the reset input of the scaling scheme, the first and second elements AND, the first inputs and sync inputs of all the triggers are combined and connected to the counting the input of the scoring circuit, the OR element, the first and second inputs of which are connected to the outputs of the first and second elements, respectively, and the output - with the transfer output of the scaling circuit, the element NOT, the first control input and the first pack The first output and the second and third inputs of the first element I are connected respectively to the direct outputs of the first and third triggers, the second input of the second element L to the direct output of the second trigger, additionally contains the first and second elements ZI-OR, element 4I-OR The outputs of which are connected to the D inputs of the first, second and third flip-flops, respectively, the first operating mode selection bus connected to the fourth input of the first element I, the third input of the second element I, and the first inputs of the first structures and the first and second ele cops ZI-OR

0 and with the first inputs of the first and second structures AND element 4I-OR, the third, fourth, fifth and sixth elements AND, the first and second elements EXCLUSIVE OR, the second bus operating mode selection, the second and

5 the third control inputs, the second and third control outputs, the output of the third element And connected to the second input of the fourth element And, to the first input of the sixth element And, to the third control output, and to the third inputs of the third structures And the first and second element ZI-OR and the fourth structure AND element 4I-OR, the first input of the fourth element AND is connected to the counting input of the counting

5 circuits, and the output - with the third input of the OR element, the second bus mode selection is connected to the first inputs of the second and third structures And the first and second elements ZI-OR, the third and fourth structure AND element 4I-OR, and the first input of the third element And, the inverse output of the first trigger is connected to the fourth input of the third element I and to the third input to the first control element

5 output and with the second inputs (the first structure AND the second element ZI-OR) of the second structures AND the second element ZI-OR and element 4И-OR, the inverse output of the second trigger is connected to the third inputs

0 of the third element And the first structure And the first element ZI-OR, and the inverse output of the third trigger - with the second input of the third element And, with the first input of the fifth element And with the third input of the second

5 of the structure AND of the first element ZI-OR, the second input of the fifth element AND is connected to the direct output of the second trigger, and the output to the first input of the first element EXCLUSIVE OR, the fourth input of the fifth And element and the second input of the sixth element AND are connected to the second the control input of the scaling circuit, and the first control input - with the second input of the second element EXCLUSIVE OR, whose output is coherent with the input of the element NOT, with the second input of the third structure AND the second element ZI-OR, and with the second input of the first element EXCLUSIVE OR, output the first element is EXCLUSIVE OR connected to the first control output

of the scaling circuit, and the output of the element NOT is with the second inputs of the third structure AND the first element ZI-OR and the fourth structure AND element 4И-OR, the direct output of the first trigger is connected to the second inputs of the first structure AND the second element ZI-OR and the third structure AND element 4I-OR, the direct output of the second trigger is connected to the second inputs of the second structure of the first element ZI-OR, the first structure AND element 4I-OR, the direct output of the third trigger is connected to the third inputs of the first and second structures AND the second element ZI-OR, the second and third structures AND element 4I-OR, and the first control input - with the third input of the first structure AND element 4I-OR,

FIG. 1 shows a functional diagram with P 1; in fig. 2 - the order of connecting several scaling schemes for increasing the size.

The scaling circuit in the Fibonacci code contains D-flip-flops 1-3, bus input 4 reset, first 5 and second 6 elements AND, counting input 7, element OR 8, transfer output 9, element NOT 10, first control input 11, first control output exit 12, elements ZI-OR 13 and 14, element 4И-OR 15, first bus 16 of choice of operation mode, third 17, fourth 18, fifth of 19 and sixth 20 elements AND, elements EXCLUSIVE OR 21 and 22, second 23 bus mode selection, the second 24 and third 25 control inputs, the second 26 and third 27 control outputs ..

To increase the size of the overall circuit, the series of scaling circuits are combined as follows. The transfer output 9 of each scaling circuit is connected to the counting input 7 of the subsequent scaling circuit, the first 12 and second 26 control outputs, respectively, with the first 11 and second 24 controllers. the inputs of the previous scaling circuit, and the third control output 27, with the third control input 25 of the subsequent module, the first 16 and second 23 operating mode selection buses, as well as the reset inputs 4 are combined.

The recalculation scheme operates as follows.

In the initial state, the D-flip-flops 1-3 of the scaling circuit are in zero states. For its operation in the direct order of counting, a single logical potential is applied to the first mode selection bus 16, and a zero logical potential is applied to the second mode selection bus 23. At the inputs of the first structure AND the first element ZI-OR 13 there are single logical potentials from the first bus 16

the choice of operating mode in the inverse outputs of the first 1 and second 2 triggers, at the second input of the first structure AND the second element ZI-OR 14 - zero logical potential from the direct output of the first trigger 1, and at the second inputs of the first and second structure AND element 4I-OR 15 - from the direct outputs of the second 2 and third 3, respectively, triggers. Upon receipt of the first clock pulse at the output of the general circuit containing three scaling circuits, the code 100000000 is established.

Before the arrival of the second clock pulse at the output of the ZI-OR 13 element, there is a potential of logical zero, the output of the ZI-OR 14 element is the potential of a logical unit, and the output of element 4I-OR 15 is the potential of the logical zero. The second clock sets the output signal of the general circuit 010000000.

Before the arrival of the third clock pulse at the outputs of the elements ZI-OR 13 and ZI-OR 14 there is a potential of logic zero, and the output of element 4I-OR 15 is the potential of a logical unit, since the first input of its first structure And receives the unit logical potential from the first bus 16 operating mode selection, to the second input - from the direct output of the second trigger 2, and to the third input - from the first control input 11. The third clock pulse sets the code 001000000 at the output of the general circuit.

Before the arrival of the fourth clock pulse, a single logical potential is present at the output of the ZI-OR element 13, since the logical inputs from the first bus 16 of the operating mode selection and from the inverse outputs of the first 1 and second 2 triggers come to the inputs of its first structure AND.

At the output of the ZI-OR 14 element there is a zero logical potential, since the third input of its first structure is AND the zero logical potential comes from the inverse output of the third trigger 3. At the output of the ZI-OR 15 element there is a single logical potential, since its outputs structures And there are single logical potentials from the first bus 16 mode selection, from the inverse output of the first trigger and from the direct output of the third trigger 3. The fourth clock pulse sets the code 101000000 at the output of the general circuit,

Before the fifth clock pulse arrives at the second, third and fourth inputs of the first element And 5 of the first scaling circuit, there are single logic potentials from the first bus 16

mode selection, from the direct outputs of the first 1 and third 2 triggers. At the outputs of the elements ZI-OR 13 and 14 and ZI-OR 15 of the first recalculation circuit, there are zero logical potentials.

The fifth clock pulse sets the code 0001000000 at the output of the general circuit. Since the clock pulse passes through the elements AND 5, OR 8 and the output 9 of the transfer of the first conversion circuit, it enters the counting input 7 of the second conversion circuit, at the output of the ZI-OR 13 element which before entering the fifth clock pulse, there is a single logical potential. At the first control output 12 of the second scaling circuit and the first control input 11 of the first scaling circuit, a zero logic potential is established. In this case, the change in the order of recalculation of the first recalculation scheme occurs. The first recalculation scheme in the sixth and seventh cycles operates similarly to the first and second cycles. In the eighth cycle, the first scaling circuit goes to the zero state. Those. the change of the order of recalculation of this recalculation scheme in the direct counting mode occurs in case of a change in the state of the first trigger 1 of the subsequent recalculation scheme. In the future, the work of the general scheme in the forward order of recalculation is similar to that described

For the operation of the general circuit in the reverse order of recalculation mode, the zero bus potential is applied to the first operating mode selection bus 16, and the second 24 and third 25 control inputs are applied to the second operating mode selection bus 23, the second control input 25 of the first conversion circuit. the third scaling circuit - a single logical potential. In the initial state, the D-triggers 1-3 scaling circuits are in zero states and at the output of the second element EXCLUSIVE OR 22 and at the second control output 26 of the third scaling circuit there is Nya Ullevi logical potential. At the output of the second element EXCLUSIVE OR 22 of the second scaling circuit and at its second control output 26 there is a single logical potential, and at the output of the second element EXCLUSIVE OR 22 of the first scaling circuit - zero logical potential. At the output of the ZI-OR 13 element of the first scaling circuit, before the arrival of the first clock pulse, there is a single logical potential, since the first, second and third inputs of its third structure receive single logic potentials, respectively, from the second mode selection bus 23

work, from the output of the element NOT 10 and from the output of the third element I 17, to the inputs of which the unit logic potentials come from the inverse outputs of all the triggers

recalculation scheme. At the output of the second element ZI-OR 14 there is a zero logical potential, and at the output of element 4I-OR 15 there is a single logical potential, since the inputs of its fourth group AND have a single logical potential from the second bus 23 of the working mode, with output element 10 and the output of the third element And 17.

5 At the outputs of the elements ZI-OR 13 and 4I-OR 15 of the second recalculation circuit, there are zero logical potentials; at the output of the element ZI-OR 14 there is a single logical potential, since there are no inputs

0 of the third structure AND there are single logical potential l, respectively, from the second bus 23 mode selection, from the output of the second element EXCLUSIVE OR 22 and from the output of the third element AND 17

5 At the outputs of the ZI-OR 13 and 14 and 4I-OR 15 elements of the third recalculation circuit there are, respectively, single, zero and one potentials similar to the first recalculation circuit. The first clock pulse passes through the elements AND 18 and OR 8 of the first and second recalculation circuits and sets at the output of the general scheme code 101010101. Before the arrival of the second clock pulse at the outputs

5 of the first 13 and second 14 elements ZI-OR of the first recalculation circuit, there is zero logical potential, and at the output of element 4И-OR 15 - a single logical potential, since its outputs

0 of the third structure AND there are single logic potentials, respectively, from the second bus 23 mode selection, from the direct outputs of the first 1 and third 3 triggers.

5 The recalculation scheme in the course of Fibonacci with forward and reverse counts is presented in Table. 1 and 2,

The second clock pulse sets at the output of the general circuit the code 001010101.

0 The third, fourth and fifth pulses are set at the output of the general circuit, respectively, codes 010010101, 100010101 and 000010101, i.e. there is a recalculation of pulses in the Fibonacci code in the reverse order of 5,

Before the arrival of the sixth clock pulse at the first input of the AND 18 element, the third control output 26 and the second output of the second element, the EXCLUSIVE OR 22 of the first scaling circuit is present

unit logic potential, and at the second control input 24 - zero logic potential. At the third control input 25 of the second perch of the scheduling circuit, there is a unit logic potential. The sixth clock pulse passes through the elements And 17, And 18, OR 8 and the transfer output 9 of the first conversion circuit and enters the counting input 7 of the second conversion circuit, and the code 010100101 is set at the output of the overall circuit.

The seventh and eighth clock pulses set at the output of the General scheme, respectively, the codes 100100101 and 000100101.

Before the arrival of the ninth clock pulse, there is a single logical potential at the second control input 24 and the first input of the fourth element And 18 of the first scaling circuit.

The ninth clock pulse is set at the output of the general circuit code 101000101,

From the tenth to the fourteenth cycles of operation of the general circuit, its operation from the first to the fifth cycles is analogous. The fourteenth clock pulse sets at the output of the general circuit the code 000000101,

Before the arrival of the fifteenth clock pulse, on the first 24 and second 25 control inputs of the second scaling circuit, there are single logic potentials, respectively, from the second control output 26 of the third scaling circuit and from the second control output 27 of the first scaling circuit, and on the first control input 24 the first recalculation scheme - zero logical potential. Thus, the fifteenth clock pulse sets the code 010101001 at the output of the total counting circuit, as the clock pulse passes through the elements AND 18, OR 8 and the output 9 of the transfer of the first and second counting circuits and is fed to the counting input 7 of the third counting circuit.

In the future, the operation of the general recalculation scheme is similar to that described.

Thus, the state in which this recalculation scheme is to be set after zeroing is determined by the state of the previous and subsequent recalculation schemes.

Claims (1)

Invention Formula The scaling circuit in the Fibonacci code, containing the first, second and third triggers, the reset inputs of which are combined and connected to the reset input of the scaling scheme, the first and second elements AND, the first inputs of which and the synchronous inputs of all the triggers the input of the scoring circuit, the OR element, the first and second inputs of which are connected to the outputs of the first and second elements, respectively, and the output, with the transfer output of the scaling circuit, the NOT element, the first control input and the first control / the second and third inputs of the first element And are connected respectively to the direct outputs of the first and third 0 flip-flops, the second input of the second element I - to the direct output of the second flip-flop, which is so that, in order to expand the functionality and scope for ensuring the reverse 5 order recalculation, additionally contains the first and second elements ZI-OR, element 4И-OR, the outputs of which are connected to the D inputs of the first, second and third triggers, respectively, the first bus 0 mode selection, connected with the fourth input of the first element AND, with the third input of the second element ZI-OR, with the first inputs of the first structures AND of the first and second elements ZI-OR and with the first inputs of the first and second structures AND element 4I-OR, the third, fourth, fifth and sixth elements are AND, the first and second elements are EXCLUSIVE OR, the second bus is the mode selector, the second and third up is equalizing inputs, and the output of the third element is AND is connected to the second input of the fourth element AND, with the first input of the sixth element I. with a third control conductive yield and third inputs of third 5 structures And the first and second elements And the fourth structure AND element 4I-OR, the first input of the fourth element AND is connected to the counting input of the scoring circuit, and the output from the third input of the element OR, 0 the second bus mode selection connection is connected to the first inputs of the second and third structures AND the first and second elements of the ZI-OR, the third and fourth structures AND of the element 4I-OR, and the first input of the third 5 of the AND element, the inverse output of the first trigger is connected to the fourth input of the third AND element and to the third input of the fifth AND element, to the first control output and to the second inputs of the first structure AND the first ZI-OR element and 4I-IPI element, inverse output the second trigger is connected to the third inputs of the third element and the first structure and the first element of the ZI-ILY, and the inverse output of the third trigger is connected to the second input of the third element and to the third input of the second structure And first item H AND-OR, the second input of the fifth element AND is connected to the direct output of the second trigger, and the output to the first input of the first element EXCLUSIVE OR, the fourth input of the fifth element AND and the second input of the sixth element L are connected to the second control input of the scaling circuit, and the first control input is with the second pass of the second element EXCLUSIVE OR, the output of which is connected to the input of the element NO, with the second input of the third structure AND the second element of ZI-OR, and with the second input of the first element EXCLUSIVE OR, the output of the first element EXCLUSIVE OR union of a first control output of scaling circuit, and an output barely mta NOT - a second structure of the third inputs of first ele0 five mante ZI-OR and the fourth structure AND element 4I-OR, the direct output of the first trigger is connected to the second inputs of the first structure AND the second element ZI-OR and the third structure AND element 4I-IL AND, the direct output of the second trigger is connected to the second inputs of the second the structure of the first element ZI-OR and the first structure AND element 4I-IL AND, the direct output of the third trigger is connected to the third inputs of the first and second structures AND the second element ZI-OR, the second and third structures AND element 4M-OR, and the first controlling entrance - with the third entrance of the first structure ry AND element 4I-OR. For my account Countdown table 2