SU1557668A1 - Pulse distributor - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to increase reliability and speed and enhance functionality by providing an automatic start of the distributor. The pulse distributor contains an RS-flip-flop and three IS-NOT elements in each bit, the zero outputs of the RS-flip-flops are connected to the inputs of the AND-NO element, the output of which is connected to the first input of the additional IS-NOT element, the second input of which is NOT connected to a single output of the RS trigger of the last bit, the output of the additional AND-NOT element is connected to the first input of the AND-NOT element of the first digit. 1 il.

Description

The invention relates to the field of computing and can be used in valve converters for various purposes.

The aim of the invention is to increase reliability and speed and enhance functionality by providing an automatic start of the distributor.

The drawing shows the functional diagram of the device.

The pulse distributor contains RS-triggers 1-4, elements AND-NOT 5-18, element NOT 19, reset bus 20, output buses 21-24, first and second clock buses 25-26.

The pulse distributor operates as follows.

If there is a low voltage level on the reset bus 20, all the triggers 1-4 are set to the initial zero

state, and the output of the element IS-NE 14 contains level 1. In this state of the circuit, if there are pulses at the clock inputs on the output buses, there are no pulses. After a high voltage is applied to the bus 20, the first clock pulse from the bus 25 passes through the NE 9 element and sets the trigger 1 to the one state. A high voltage level from a single output, trigger 1 ensures that a pulse from a clock bus 25 passes through an IS-NE element 5 to an output bus 21. A low voltage level at the zero output of a trigger 1 forms a level 1 output element AND-NOT 14. Another impulse on the clock bus 26 passes through the element AND-NOT 10 and sets the trigger 2 in one state, after which this pulse through

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The AND-NE 15 element returns the trigger 1 to the zero state and passes to the output bus 22 through the AND-NOT element 6. The next clock pulse on the bus 25 sets the trigger 3 to one state, returns the trigger 2 to the zero state and passes to the output bus 23. The next clock pulse on bus 26 sets trigger one k, returns trigger 3 to zero state and passes to output bus 2C. In addition, a single level with 10

and a reset bus, characterized in that, in order to increase reliability and speed and enhance functionality by providing an automatic start of the distributor, the AND-NOT element, the NOT element and each bit two AND-NOT elements are added to it, The first input of the first additional NAND element of each bit, except the last one, is connected to the single output of the RS flip-flop of the subsequent. Discharge, the first input of the primary driver 4 is inverted by the element NOT 19, 15th of the Additional element AND NONE

and a reset bus, characterized in that, in order to increase reliability and speed and enhance functionality by providing an automatic start of the distributor, the AND-NOT element, the NOT element and each bit two AND-NOT elements are added to it, the first input of the first additional element AND-NOT of each bit, except the last one, is connected to the single output of the RS flip-flop of the subsequent one. The first input is

resulting in the output element AND-NOT 14 on. input element AND-NOT 9 receives a single level that allows the passage of the next clock

The impulse from bus 25 to the installation of the trigger 20 ROWS is connected respectively to pergera 1. Next, the process is repeated. When pinging on the reset voltage bus 20, all the triggers 1-4 are set to zero by the inputs of the second additional AND-NOT elements of even and odd bits and respectively with the second and first clock buses, the output of the first additional AND- element NOT of each bit is connected to the first R-input of the RS flip-flop of this bit, the second R-inputs of the RS-flip-flop are connected to the reset bus and to the third inputs of the AND-HES elements of each bit, a single output of the RS-flip-flop of each bit connected to the second input of the second will complement The main element of the NAND of this bit, the zero outputs of the RS-flip-flops are connected to the inputs of the first element of the NAND, the output of which is connected to the first input of an additional element of the NAND, the single output of the RS-trigger of the last bit is NOT connected to the second input An additional NAND element whose output is connected to the first input of an NAND element of the first bit, and the output of the second additional NAND element of each bit is connected to the corresponding output bus.

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Thus, the present invention allows for providing a single control bus with a reset and operation of a distributor. Moreover, the reset is performed simultaneously on all bits and with high reliability by connecting the reset bus 20 to the zero inputs of the RS flip-flops 1-4 and to the inputs of the AND-HE elements 9-12.

Claims (1)

Invention Formula Pulse distributor, containing in each bit an RS trigger and a NAND element whose output is connected to the S input of the RS flip-flop, a single output of which is connected to the first input of the NAND element of the subsequent discharge, the second inputs of the NAND elements of the NAND and even-numbered bits are connected respectively with the first and second clock tires, the first AND-NOT element of the last bit is connected to a single one, the output of the RS flip-flop of the first order, the second inputs of the first additional element AND – NOT odd and even numbered SERIES are connected respectively to the first five thirty 35 40 45 the primary inputs of the second additional AND-NOT elements of even and odd bits and respectively with the second and first clock tires, the output of the first additional AND-NOT element of each bit is connected to the first R-input of the RS flip-flop of this bit, the second R- RS-flip-flop inputs are connected to the reset bus and to the third inputs of the NAND elements of each bit, the single RS-flip-flop output of each bit is connected to the second input of the second additional NAND element of this bit, the zero outputs of the RS flip-flops are connected to the inputs the first element is NOT the output of which is connected to the first input of the additional NAND element, the single output of the RS trigger of the last digit is NOT connected to the second input of the additional NAND element, the output of which is connected to the first input of the NAND element of the first discharge, and the output of the second An additional NAND element of each bit is connected to the corresponding output bus. Editor 0.Speedyh Compiled by V.Vygovsky Tehred M.DidykKorrektor D.Obruchar