SU1378055A1 - Synchronous divider of frequency by 9 - Google Patents

Abstract

The invention relates to a pulse technique and can be used, for example, in frequency synthesizers. The purpose of the invention, the expansion of the field of application, is achieved by reducing the speed requirements for the subscriber. The frequency divider by nine contains four RS-flip-flops 1,2,3 and 4, item 5, clock bus b, reset bus 7, unit-level bus 8, output bus 9. Device operation, as well as logical equations for the proposed circuit connection elements are explained in the time diagrams provided in the specification. 2 Il.

Description

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The invention relates to a pulsed technique and can be used, for example, in frequency synthesizers.

The purpose of the invention is to expand the scope of application by reducing the speed of response to the subscriber.

Figure 1 shows an electrical functional diagram of the device; 2 shows timing diagrams for his work.

The device contains the first I, second 2, third 3 and fourth 4 IK-triggers and the element And 5j C- and R-inputs of 1K-flip-flops 1-4 are connected respectively to the clock bus 6 and the reset bus 7, K-input of the first 1K-trigger 1 is connected to a single-level bus 8, 1-input with an inverse output of the fourth 1K-flip-flop 4, the K-input of which is connected to the inverse output of the third 1K-flip-flop 3 and the first input of the And 5 element, the output of which is connected to the output bus 9, inverse the first output of the first 1K-flip-flop 1 is connected to the I-and K-inputs of the second IK-flip-flop 2 and to the K-input of the third IK-flip-flop 3, The second output of the second 1K flip-flop 2 is connected to the 1-input of the third 1K-flip-flop 3, the direct output is connected to the 1-input of the fourth 1K-flip-flop 4 and the second input of the And 5 element

With such a combination of elements, the logical equations for the I and K inputs of all 1K triggers of the synchronous frequency divider by 9 are as follows:

It Q4 1 1 - b 2-4 t

K, 1; ,; ,; K, Q

The device works as follows.

By the reset signal on bus 7, all 1K device triggers are reset to the initial zero state, while (i) with i o) the output states are as follows:

Q, 0; Q, 0; Qj 0; Qt Oh,

and then, based on the logical equations for the I and K inputs of 1K triggers, the states of the inputs are

I, 1; eleven; Ij 1; ten; Ki 1; Kg 1; K, 1;

K 1.

Since the 1K-trigger when and K O does not change its state, when I I and K O - switches

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5 in state 1, with I 1 and K 1 being interchanged into the opposite state and with I O and K 1 being switched to the state O (triggers respond to the front of the clock pulse), then upon arrival at the device input via bus 6 the first pulse 1K-triggers 1-3 are switched to state 1, and 1K-trigger 4 does not change its state, i.e. the output states are equal to Q, 1; Q about (figure 2, when i 1). The state of the inputs is as follows.

I, 1; I, 0; I 6; eleven; K 1; K, 0; K, 0; K + 0.

When the second pulse arrives at the device input, the 1K-flip-flops 1 and 4 change their state; 1K-flip-flop 1 switches to the O state, and the 1K-flip-flop 4 to 1, 1K-flip-flops 2 and 3 remain in the previous state (FIG. 2, with i 2). Consequently, the states of the outputs and inputs of the device are as follows: Q, 0; Q, 1; Q3 1; Qt U

I, 0; I 5 1; 1 0; ,; K, I; K, 1; Kj 1; Cd 0..

Similarly, we obtain all the values of the inputs and outputs for each i (Fig. 2).

The transfer signal on bus 9 appears when the ninth impulse P Q Qj arrives at the input of the device. . When the device arrives at the input of the device via the bus 6, the seventh pulse at the direct output of the 1K-flip-flop 2 and on the inverse output of the 1K-flip-flop 3, single levels are set, which leads to the formation of a transfer signal (Fig.2, with i 7) on the item 5 and on bus 9. After the ninth pulse arrives at the input of the device along bus 6, the device returns to its initial state, IK flip-flop 2 will have zero level at the direct output, which will result in element 5 and output 9 (figure 2, when 1 0).

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Thus, the duration of the transfer pulse is two clock periods.

Claims (1)

Invention Formula Synchronous frequency divider by 9, the first, second, third and fourth 1K-flip-flops, C- and R- inputs of which are connected to the tire and reset bus, respectively; The K-input of the first 1K-trigger is connected to the single level bus, inverse output - with 1 input of the second 1K trigger and K input of the third 1K trigger, the inverse output of which is connected to the first input of the And element, output FIG. 2 which is connected to the output bus, characterized in that, in order to expand the field of application, the inverse output of the first IK trigger is connected to the K input of the second 1K trigger, the inverse output of which is connected to the 1 input of the third IK trigger, direct output with the second input of the element I and with the 1 input of the fourth 1K-flip-flop, whose K-input is connected to the inverse output of the third 1K-flip-flop, the inverse output with the 1-input of the first 1K-flip-flop.