SU1676097A1 - Synchronous frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computer devices in frequency synthesizers. The purpose of the invention is to increase reliability by simplifying-by the introduction of the element OR 7 and the organization of new structural links. The device contains IK-triggers 1 ... 5, the element And 6, the input and output tires 10 and 11, the tire 9 reset. The division factor of the device is 25. 2 sludge.

Description

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The invention relates to a pulse technique and can be used in automation and computing devices, in frequency synthesizers as a frequency divider by 25.

The purpose of the invention is to increase reliability by simplifying.

Figure 1 shows an electrical functional diagram of the device; 2 shows timing diagrams for his work.

Synchronous frequency divider contains the first-fifth IK-triggers 1-5, the element And 6, the output of which is connected to the I-and K-inputs of the fifth IK-trigger 5, the element OR 7, the output of which is connected to the K-input of the first IK- trigger 1, bus 8 logical unit, which is connected to the 1 input of the first IK-flip-flop, reset bus 9 and input bus 10, which are connected respectively to the R- and C-inputs of the first or fifth IK-flip-flops 1-5, the first input element I 6 is connected to the direct output of the first IK trigger 1 and to the K input of the third IK grigger 3,1-input of which is connected to the direct output of the second IK -trigger 2, with the first input of the element OR 7 and with the I and K inputs of the fourth IK trigger 4, the inverse output of which is connected to the second input of the element AND 6, the direct output to the second input of the element OR 7, the third input of which is connected With the direct output of the first IK-flip-flop bis output bus 11, the inverse output of the first IK-flip-flop 1 is connected to the 1-input of the second IK-flip-flop 2, the K-input of which is connected to the inverse output of the third IK-flip-flop H, the direct output of which connected to the third input element And 6, the fourth input of which is connected to the inverse output of the second I K-trigger 2.

With such a combination of elements, the logical equations for the I and K inputs of all IK triggers of the synchronous frequency divider (by 25) will be as follows;

And 1; la 6i; s Qz: A Q2; Is 01020З04;

Ki 02 Q4vQs, Ka Oz. , K4 Og, K5 QiQ2Q3Q4.

The operation of the synchronous frequency divider is completely determined by the logical equations for the 1- and K-inputs of the IK-flip-flops 1-5.

On the Reset signal, which comes in the form of a pulse before starting work on the bus 9, all IK-triggers are set to the initial (zero) state. In this case, the states of the outputs of the IK-flip-flops 1-5 will be equal to: Cu 0; Qa 0; Oz 0; 04 0; Qs O (figure 2 with I 0).

Based on the logical equations for the I and K inputs of IK triggers 1-5, the inputs will be as follows:

h 1; 12 1: h 0; M 0; 5 0: Ki 0; K2 1; Cs 0; K4 0; Ks 0.

Since the IK flip-flop on the subsequent input pulse on bus 10 with I 0 and K 0 does not change its state, with I 1 and K 1 switches to the opposite 0 state, with I 1 and K 0 switches to the state of logical one, and at I 0 and K 1 - to the state of logical zero, then by the first input pulse on bus 10, IK-triggers 1 and 2 switch to the state of 5 logical units, and IK-triggers 3-5 do not change their state ( 2 when

1 1), In this case, the states of the outputs and the input of IK-flip-flops 1 ... 5 will become equal: Qi 1;

02 1; Oz 0; See 0; Qs 0; 11 1; g 0; 0 1з 1; M 1; Is 0; Ki 1; K2 1; Cs 1;

 Ks 0.

On the second input pulse from the bus 10, the device will transition to its second state (FIG. 2 with I 2), which

5 is characterized by the following outputs and inputs: See 0; one; 04 1; Qs - 0; h 1, 12 1; h 0; C 0; Is 0; Ki 1; K2 0; Cs 0; K «0; Ks 0. Considering the operation of the synchronous frequency divider in the same way, we get all the states of IK-flip-flops 1-5 of its outputs and inputs for all I. When a 24 pulse is received, the outputs of IK-flip-flops 1-5 have the following states: Qi one; Q2 0;

5 Oz 1: Q4 0; Qs 1, therefore the status of the inputs will be:

And 1; 12 0; h 0; l4 0; I5 1; Ki 1; Ka 0; K4 0; Ks 1. With these states, the I and K inputs are

0, the arrival of 25 input pulses per bus 10 changes its state of IK-triggers 1,3,5, and IK-triggers 2.4 does not change its state, i.e., the outputs of IK-flip-flops 1-5 take the following values: C 0; Q2

Claims (1)

50; Oz 0; Q4 0; Qs 0, i.e. the device will return to the initial state. Claims of Invention A synchronous frequency divider comprising first, second, third, fourth, and 0 Fifth IK-flip-flops, C- and R-inputs of which are connected respectively to the input bus and to the reset bus, the element I, the first and second inputs of which are connected respectively to the direct output of the first and to the in5 true output of the fourth IK-trigger, output - with I and K-inputs of the first IK-flip-flop, the direct output of which is connected to the output bus, characterized in that, in order to increase reliability by simplifying, an OR element is introduced into it, the first input of which is connected to the direct output of the second IK-flip-flop, with l-input of the third IK-flip-flop and with I-and K-inputs of four that IK-flip-flop, the direct output of which is connected to the second input of the OR element, the third input of which is connected to the direct output of the fifth JK-flip-flop, the output to the K-input of the first IK-flip-flop, the input of which is connected to the bus of the logical unit, inverse / 012345 е 1 in zyun 1213 m 15КП1В югппзг Zhishplgitpshshl / itshshshshshi  JTJTJTJnJTJ nJTJTJlJl riJ-l FIG. 2 the output is with the l-input of the second IK-flip-flop, the direct output is with the K-input of the third IK-flip-flop, the direct output of which is connected to the third input of the And element, the fourth input of which is connected to the inverse output of the second IK-flip-flop, K-input which is connected to the inverse output of the third IK-trigger.