SU1221747A1 - Synchronous frequency divider with 12:1 countdown - Google Patents

Abstract

The invention relates to digital technology and can be used in the construction of digital frequency synthesizers. The device contains four 1K-triggers 1, 2, 3, and 4, element 5 I, bus 6 logical 1, - clock bus 7, bus, 8 drops, and output buses 9 and 10. The device uses fewer blocks and connections than it improves its reliability while simplifying the device. In the description given, time diagrams of the device. 2 pe. (Lc tc to

Description

one

The invention relates to digital technology and can be used in the construction of digital frequency synthesizers, digital clocks, electronic digital calendar month counter, etc.

The purpose of the invention is to increase the reliability of the device by reducing the number of elements and chains, which at the same time leads to its simplification.

FIG. 1 shows a functional diagram of the synchronous frequency divider at 12j in FIG. 2 - time diagrams of his work.

The tacTOT synchronous divider at 12 contains four 1K-triggers 1, 2, 3, and 4, element 5, bus 6, logic 1, clock bus 7, reset bus 8, and output buses 9 and 10.

The counting inputs of all 1K flip-flops 1, 2, 3 and 4 are connected to the device clock bus 7, the inputs R of all 1K-flip-flops 1, 2, 3, and 4 are connected to the device reset bus 8, the outputs of the fourth 1K flip-flop 4 are output buses 9 and 10 of the device, I- and K-inputs of the first 1K-flip-flop 1 and K-inputs of the second and third IK-flip-flops 2 and 3 are connected to bus 6 of logic 1. Direct outputs of the first and third 1K-flip-flops. 1 and 3 are connected respectively to the first and second inputs of the element 5, the output of which is connected to the I and K inputs of the fourth 1K flip-flop 4.1-input to the trading 1K flip-flop2 connected to the inverse output of the third 1K flip-flop 3,1-input of which is connected to direct output of the second 1K flip-flop 2..

FIG. 2 is marked: a - input signal on the clock bus 7, b - Q on the direct output of the first IK trigger 1; c is the Q signal at the direct output of the second 1K flip-flop 2, d is the QJ signal at the direct output of the third 1K flip-flop 3 D is the Q signal at the direct output of the fourth 1K-flip-flop 4.

The device works as follows.

By the Reset signal, arriving as a pulse through the device reset bus 8, all 1K triggers 1, 2, 3, and 4 of the synchronous frequency divider 12 are set to the initial number 211772.

left position. The dashes of this state of the outputs are equal (Fig. 2, at):

Q, U, Q5,.

5 Based on the logical equations for the I and K inputs of 1K triggers, the states of the inputs will be as follows:

t t t t. -1-2 y -I i and- I I It. t, - 1 And, b-It III. V- -tto l

10 KI- C 3 5 0

On the first clock pulse on bus 7, the first and second triggers 1 and 2 switch to logic 1, and the third and fourth 15 1K triggers do not change their state (Fig. 2, at). In this state, the outputs are equal to:

Q tt1tl Q -IlltlI, -tint, -. -ttnll

1 h 2 h 3 44 - and

20 Changes and input states:

t tt 1 tl, Y tl (lt, -g- tl 1 It -g 1l, -itl

1, - I, ij- 1, 1, - 1, ± l- and;

V- M 1 It, V- tl 1 It v- -tlilt. ir.

- - one ; one ; 0

as a result, the next, second, clock pulse, received via clock bus 7, synchronously divides the frequency to 12 in the second state (Fig. 2, at), which will characterize 30 with the following values of the outputs and inputs 1K-flip-flops:

Q., Q Q, Q 1, G 5 1, 1.

. V - 1 tt. V -tl 1 It. V-tlntl, - 1; k - I; k - 1; K Oh.

3574

in the third cycle (fig. 2, with) the states of the outputs and inputs are equal to:

Q About Q Q, 40 I I, I, I,

To -It lit. w- tl 1 It, v -ttltl. T / - -tin, - 1; one ; K, - 1; K, - 0.

Consider further in the same way the work of the proposed synchronous frequency divider by 12 on IK-triggers. We obtain all the states of the inputs and outputs of each 1K trigger 1, 2, 3, and 4 for all 1 according to FIG. 2

50 ,

Thus, the proposed device performs division by 12 pulse frequency on bus 7 and at the same time contains less

55 the number of blocks and connections than the prototype device, which ensures the reliability increase while simplifying the device.

Claims (1)

Invention Formula Synchronous frequency divider for 12, containing four 1K-flip-flops and element And, the counting inputs of all 1K-flip-flops are connected to the device clock bus, the inputs R of all IK-flip-flops are connected to the device reset bus, I- and K-inputs of the first 1K-flip-flop are connected bus logical b, the outputs of the fourth IK trigger are the output buses of the device, and the forward outputs of the first and third 1K-flip-flops are connected respectively to the first and second the inputs of the element I, whose output is connected to the 1 input of the fourth IK trigger, characterized in that, in order to increase the reliability of the operation while simultaneously sticking the device, the second and third 1K flip-flops are connected to the K-input of the first 1K trigger; 1-input of the second GK-flip-flop is connected to the inverse output of the third IK-flip-flop, 1-input of which is connected to the direct output of the second 1K-flip-flop, K - input of the fourth 1K-flip-flop is connected to the output of the element. FIG 2