SU1330757A1 - Decade counter for heptasegment indicators - Google Patents

Abstract

The invention relates to pulse. technology and can be used in computing and measuring devices. The invention provides the reliability of a decade counter, made according to the proposed scheme. The counter contains 1K-trigi (L

Description

heras 1–4, elements AND 5–13, elements inn 14–16, clock bus 17, reset bus 18, bus 19 of a logical unit, transfer bus 20, exits 21 (a) - 27 (q). Elements 6-15 form an encoder for successively including elements of a seven-segment indication1

The acquisition relates to the impulse technique and can be used on the computational and measuring yc j pof iCTBax.

The purpose of the invention is to increase reliability.

FIG. Figure 1 shows a block diagram of a ten-day counter for seven-segment indicators; in fig. 2 - time diagrams of the functioning of the decade counter for seven-segment indicators.

The counter contains the first 1, second 2, third 3 and fourth 4 1K-flip-flops, first 5, second 6, third 7, fourth 8, fifth 9, sixth 10, seventh P, eighth 12 and ninth 13 elements And, the first 14, the second 15 and the third 16 elements of the FIR, the clock bus 17, which receives input (counted) pulses, the reset bus 18, the spike 9 logical unit, the 20 ne.U Hoca bus, 1-к: по; charge for control - nor the following; deca, decay, and outputs 21 (a), 22 (b), 23 (s), 24 (d), 25 (e), 26 (), 27 (q). The counting inputs of all the triggers 1-4 are connected to the clock bus 17, the reset inputs of the triggers 1-4 are connected to the reset bus 18, the I and K inputs of the first trigger are connected to the bus 19 of the logical unit, the direct output 1K of the trigger 1 is connected to K- the input of the second 1K flip-flop 2 and the first inputs of the And 13 element and the Sh1I 7, 15 and 16 elements. The inverse output of the first NS-flip-flop 1 is connected to the 1st input of the third 1K-flip-flop 3, as well as the first inputs of the And 5 and iO elements. The inverse output of the second IK-trigger 2 is connected to the first inputs of the And 8 and 14 elements. The forward output of the third 1K-flip-flop 3 is connected to the K-input of the fourth 1K-flip-flop 4,

330757

Torah. 1K-triggers 1-4 with element 5 form a frequency divider. The decrease in the number of elements and inter-element links compared to the prototype provides an increased reliability of the ten-day counter for seven-segment indicators. 1 tab. 2 Il.

0

five

0

five

0

five

0

The 1 input of the second 1K flip-flop 2, the first input of the AND 12 element and the second input of the AND 8 element, the output of which is connected to the 1st input of the fourth IK-trigger 4, the first input of the AND 9 element and the second input of the OR 16 element, whose output is output 25. The inverse output of the third 1K-flip-flop 3 is connected to the first inputs of the And 6 and 11 elements and the second input of the And 13 element. The direct output of the 1K-flip-flop 4 is connected to the second inputs of the And 11 and OR 15. 15. The inverse output of the fourth 1K-flip-flop 4 is connected to the second inputs of the elements And 5, 6 and 9 and the third input of the element And 13, the output to expensive is the transfer bus 20. The output of the AND 5 element is connected to the K input of the third 1K flip-flop 3. The output of the OR element 15 is connected to the second input of the AND 12 element, the output of which is output 26 and connected to the second input of the AND element 10, the output of which is counter output 23. The output of the AND 6 element is connected to the second input of the AND 7 element, the output of which is connected to the second input of the OR element 14, the output of which is the counter output 27, the outputs 21,24 and 22 of which are the outputs of the AND elements 9, 8 and P.

Elements 6-15 form a decoder for sequential switching on (possible through the appropriate driver) elements of the seven-segment indicator, 1K triggers J - 4 with element 5 form a frequency divider by 10. Triggers respond to changes in clock pulses from a value to.

Figure 2 indicated:

31330757

Input - input clock pulses of the clock bus 17;

i — order numbers of the states of solaceism;

direct output per1;

direct output bt2;

direct output 10

b o

in about

g

-signal trigger

-signal trigger

-signal

third trigger 3;

d - signal on the forward code of the fourth trigger A;

P - transfer signal on bus 20;

a, b, c, d, e, f, q - signals at the corresponding outputs 21, 22, 23, 24, 25, 26 and 27 of the device.

The operation of the proposed decade counter for seven-segment indicators is completely determined by the logical equations for 1: - and KJ-BXO. In the initial position, all the IK triggers 1 through 4 with the Reset signal received as a pulse through the reset bus 18 are reset to the initial state (the diagrams in Fig. 2), while

Q, 0; QI 0; Q 0.

Based on the logical equations for the I-- and Kj inputs of the state trigger, the inputs are as follows:

i, l; i, Q, 1; 14 d - QjQ, 0; K, l; to

0; K, 1; K.

Q, 0; K, 0.

 Q.Q 1; K rz

According to the logical equations for the outputs of the decoder, we determine that a dQ4 0; b Q, Q4 0; with fQ, 0; d, 0; e dvQ, 0;

f QjCQ.VQ) 0;

q Q, Q2 V Qi, Q4 1.

At the same time, the figure O is illuminated on the seven-segment indicator. Since the 1K-trigger on the input clock

to the first pulse at I 0 and not because of the 45 trigger and the first input of the ninth

changes its state, when and switches to the opposite state, when I 1 and K O switches to the state of a logical one, and when I O and - to the state of a logical zero, then the first clock pulse on the bus 17 1 and the third 3 1K-flip-flops switch to the state of a logical unit, and flip-flops 2 and 4 do not change their state (the diagrams in Fig. 2 with i 1), and the outputs of the flip-flops 1-4 are as follows: Q, - l; Q, -l. Measured 50

55

element I, the inverse output of the fourth trigger is connected to the first input of the first, second and fifth elements of I, and the inverse output of the first trigger is connected to the first input of the sixth element I, the output of which is connected to the output from the device, the second input of the sixth element And soy with the output f of the device, the investment output of the second trigger is connected to the first inputs of the third and fourth elements And, the output of the fourth element And is connected to the code d of the device and the first of the fifth elec

I) K-inputs

are and states

and will be equal to: 1, 1; eleven; 1.0;

eleven; K, 1; K 1; K, 0; on

0

five

five

0

five

0

the outputs of the decoder will be signals q l, and on the decoder number 1,

On the second clock pulse (diagrams in figure 2, at) the states of the outputs and inputs are as follows; Q, 0; Q, l; Q ;; I, l; I, l; K, l, Kj-0; K4 I; and on the seven-segment display the number 2 will light up.

Analyzing the operation of the decade counter for seven-segment indicators in the same way, we get all the values of the signals (logic functions) at the outputs of the frequency divider and decoder (diagrams in figure 2) for all 1, which are listed in the table.

The reduction in the number of elements and inter-element links provides the highest reliability of the ten-day counter for seven-segment indicators.

Claims (1)

Invention Formula A decade counter for seven-segment indicators containing four 1K-flip-flops, nine AND elements and two OR elements and having outputs a, b, c, d, e, f, q for connecting the corresponding elements of a seven-segment indicator, the counting inputs of all the trigger The R-BXOs of all the triggers are connected to the device reset bus, the 1 input of the first trigger is connected to the bus of a logical unit, the direct output of the first trigger is connected to the K input of the second trigger and the first input element And, the inverse output of the fourth trigger is connected to the first input of the first, second and fifth elements And, and the inverse output of the first trigger is connected to the first input of the sixth element And, the output of which is connected to the output from the device, and the second input of the sixth element And is connected to the output f of the device, the inverse output of the second trigger is connected to the first inputs of the third and fourth elements I, the output of the fourth element I is connected to the code d of the device and the first input of the fifth elelefirst element I, the output of which is connected to the K-in a third flip-flop, straight vkod third flip-flop is connected to the K-input of the fourth and the 1-input of the second flip-flops and a second 513307576 And, the output of which is connected to the unit and the inverse output to the first output of the device, and the output of the third flip-flop is connected to the 1-input. The first element And is connected to the output of the third trigger and the second input q of the device, the direct output of the third trigger is connected to the first input of the eighth element And, and the inverse output of the third trigger is connected to the second input of the second element And, the output of the fourth element AND, the inverse input of the first element OR, and the direct output of the third trigger is connected to the second inputs of the seventh and ninth elements AND, the inverse output of the fourth trigger is connected to the 15 third input of the ninth AND element whose output is connected n with the signal transfer bus, the output of the seventh element AND is connected to the output b of the device, the direct output of the fourth trigger of the third element OR is connected to the pr - 20 ra connected to the second input of the second mine output of the first trigger, the first OR element, the output of which is connected to the input the second and second inputs are primary to the second input of the eighth element OR, and the output is connected to an element, and the output of the eighth to the output e of the device, the K input of the primary element is connected to the output of the 1st trigger connected to the bus 25 of the device. my output of the fourth trigger is connected to the first input of the seventh element I, one of them, so that, in order to increase reliability, a third element SH is introduced into it, the first input of which is connected to the output of the fourth element AND 1-input fourth trigger, second input the first element And, the output of which is connected to the K-input of the third trigger, the direct code of the third trigger, is connected to the K-input of the fourth and 1-input of the second trigger and the second Which unit and inverse output of the first trigger is connected to the 1-input. the third trigger and the second input of the fourth And element; the inverse output of the third trigger is connected to the second inputs of the seventh and ninth And elements; the inverse output of the fourth trigger is connected to the third input of the ninth And element, the output of which is connected to the signal transfer bus; the output of the seventh element And it is connected to the output b of the device, the direct output of the fourth trigger is connected to the second input of the second OR element, the output of which is connected to the second input of the eighth element AND, and the output of the eighth element is connected to the output 1 device. VNIIPI Order 3593/57 Circulation 901 Subscription Random polygons pr-tie, Uzhgorod, st. Design, And fig.g Subscription