CN1738207B - Asynchronous decade counter IC - Google Patents
Asynchronous decade counter IC Download PDFInfo
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- CN1738207B CN1738207B CN 200510012648 CN200510012648A CN1738207B CN 1738207 B CN1738207 B CN 1738207B CN 200510012648 CN200510012648 CN 200510012648 CN 200510012648 A CN200510012648 A CN 200510012648A CN 1738207 B CN1738207 B CN 1738207B
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- flop
- flip
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Abstract
The invention relates to a asynchronous decade counter integrated circuit, which is improved on the base of present 74LS290 chip. The main improved points comprise: (1) changing the 'OR gate' of the Rends of the second and the third JK triggers as FF1 and FF2 of the logic circuit map of present 74LS290 chip into 'AND gate'; keeping the 'S' ends of the logic circuit map of the second and third JKtriggers of present 74LS290 in high voltage or hung. The advantages of said invention comprise: the invention not only has the function of binary-quinary-decade counter of former 74LS290 chip, but also has the logic function of presetting 0001 and 1001 accurately; and the functions of inventive integrated circuit has rigorous logic theory relation.
Description
Technical field
The present invention relates to a kind of asynchronous decade counter IC, belong to MSI digital circuit integrated chip.
Background technology
At present, the most frequently used asynchronous decade counter (being 74LS290) is made up of 11 binary counter and 1 asynchronous quinary counter.There is following shortcoming in this counter: (1) does not possess the Q of making
3Q
2Q
1Q
0Directly put 0000 and put 1001 logic function.(2) in its menu S has appearred
01S
02=0, R
01R
02=0 logic state, this is to allow anything but in the logical theory to occur.
Summary of the invention
Technical problem to be solved by this invention is to overcome the existing shortcoming of existing 74LS290 chip, and provides a kind of logic function more complete and meet the asynchronous decade counter IC of strict logical theory.
The technical solution adopted for the present invention to solve the technical problems:
The present invention improves to form on the basis of existing 74LS290 chip, and its main improvement is as follows:
(1) with the 2nd among the existing 74LS290 chip logic circuit figure and the 3rd JK flip-flop FF
1And FF
2The disjunction gate of R end change " with door " into.
(2) " S " end with the 2nd and the 3rd JK flip-flop among the existing 74LS290 chip logic circuit figure connects high level or unsettled (dispense but S can be held, press unsettled processing during principle analysis) all the time in process for making.
Concrete technical scheme of the present invention is as follows:
The present invention is made up of 1 binary counter and an asynchronous quinary counter; Described 1 binary counter is by the first JK flip-flop FF
0, have two first non-conjunction RF that put 0 input, have two second non-conjunction SF that put 1 input and form the first JK flip-flop FF
0The output of the R termination first non-conjunction RF, the first JK flip-flop FF
0The output of the S termination second non-conjunction SF, the first JK flip-flop FF
0Input end of clock meet CP
0, two output is respectively the first output Q
0And the second output Q
0A described asynchronous quinary counter is by second to the 4th JK flip-flop FF
1-FF
3, have two first non-conjunction RF that put 0 input, have two second non-conjunction SF that put 1 input and form the second JK flip-flop FF
1With the 4th JK flip-flop FF
3Input end of clock meet CP
1The 3rd JK flip-flop FF
2Input end of clock meet the second JK flip-flop FF
1The first output Q
1, the 4th JK flip-flop FF
3The output of the S termination second non-conjunction SF, the 4th JK flip-flop FF
3First input termination second JK flip-flop FF of " with door " of J end
1The first output Q
1, its another input termination the 3rd JK flip-flop FF
2The first output Q
2It is characterized in that the second and the 3rd JK flip-flop FF
1, FF
2Two inputs of " with door " of R end connect the output of the first non-conjunction RF and the second non-conjunction SF respectively; The second and the 3rd JK flip-flop FF
1, FF
2S end connect high level or unsettled all the time.
The menu of integrated circuit of the present invention sees attached list 1.
Beneficial effect of the present invention is as follows:
The present invention not only has two in full detail outside the function of system counter of former 74LS290 chip, presets 0000 and 1001 logic function accurately but also possess; The menu of integrated circuit of the present invention has possessed strict logical theory relation.
Description of drawings
Fig. 1 is a logical circuitry of the present invention.
Fig. 2 is an integrated circuit (IC) chip pinouts of the present invention.
Fig. 3 is binary tally function oscillogram of the present invention.
Fig. 4 is a quinary tally function oscillogram of the present invention.
Fig. 5 is a metric tally function oscillogram of the present invention.
Embodiment
By the embodiment shown in Fig. 1,2 as can be known, it is made up of 1 binary counter and an asynchronous quinary counter; Described 1 binary counter is by the first JK flip-flop FF
0, have two first non-conjunction RF that put 0 input, have two second non-conjunction SF that put 1 input and form the first JK flip-flop FF
0The output of the R termination first non-conjunction RF, the first JK flip-flop FF
0The output of the S termination second non-conjunction SF, the first JK flip-flop FF
0Input end of clock meet CP
0, two output is respectively the first output Q
0And the second output Q
0A described asynchronous quinary counter is by second to the 4th JK flip-flop FF
1-FF
3, have two first non-conjunction RF that put 0 input, have two second non-conjunction SF that put 1 input and form the second JK flip-flop FF
1With the 4th JK flip-flop FF
3Input end of clock meet CP
1The 3rd JK flip-flop FF
2Input end of clock meet the second JK flip-flop FF
1The first output Q
1, the 4th JK flip-flop FF
3The output of the S termination second non-conjunction SF, the 4th JK flip-flop FF
3First input termination second JK flip-flop FF of " with door " of J end
1The first output Q
1, its another input termination the 3rd JK flip-flop FF
2The first output Q
2It is characterized in that the second and the 3rd JK flip-flop FF
1, FF
2Two inputs of " with door " of R end connect the output of the first non-conjunction RF and the second non-conjunction SF respectively; The second and the 3rd JK flip-flop FF
1, FF
2S end connect high level or unsettled (but in process for making, the S end can be dispensed, during principle analysis by unsettled processing) all the time.
The pin of the integrated circuit (IC) chip of present embodiment is as follows:
14 pin: meet power supply V
CC
7 pin: earth terminal GND;
10 pin: be first clock pulse input terminal CP
0
11 pin: be second clock pulse input terminal CP
1
8 pin, 4 pin, 5 pin, 9 pin: for counting four output Q of 8421 conditional codes
3, Q
2, Q
1, Q
0
13 pin, 12 pin: for two of counter put 0 end R
02, R
01
1 pin, 3 pin: for two of counter put 1 end S
01, S
02
2 pin, 6 pin: be empty pin.
The described integrated circuit of present embodiment not only possesses the function of two-five-decimal addition counter, presets 0000 and 1001 logic function accurately but also had.Be analyzed as follows:
One, works as R
01R
02=1, S
01S
02, under the effect of pulse, has the function (as: initial condition is 0000, and what finish is function from the 0000-0001......1001 plus coujnt) of two-five-decimal addition counter under 10 CP impulse actions at=1 o'clock;
A, clock pulse are from CP
0The end input, output Q
0What end obtained is binary tally function, and oscillogram is seen Fig. 3 .Q
0To CP
0What realize is to meet two to advance one function.
B, clock pulse are from CP
1The end input, output Q
3Q
2Q
1Hold be quinary tally function, oscillogram Fig. 4.Q
3To CP
1What realize is to meet five to advance one function.
If c is with Q
0With CP
1Be connected by external circuit, clock pulse is by CP
0The end input, output Q
3Q
2Q
1Q
0End obtains 8421 yards decimal system tally functions, and oscillogram is seen Fig. 5.Q
3To CP
0What realize is the function of dot and carry, and count status is: 0000 → 0001 → 0010 → 0011 → 0100 → 0101 → 0110 → 0111 → 1000 → 1001 → 0000.
Two, work as R
01R
02=0, S
01S
02=1 o'clock, it is finished was asynchronous 0000 the logic function of putting, Q
3Q
2Q
1Q
0Output 0000;
Three, work as R
01R
02=1, S
01S
02=0 o'clock, it is finished was asynchronous 1001 the logic function of putting, Q
3Q
2Q
1Q
0Be output as 1001.
Subordinate list 1 (menu on the integrated road of the present invention):
Claims (1)
1. asynchronous decade counter IC, it is made up of 1 binary counter and an asynchronous quinary counter; Described 1 binary counter is by the first JK flip-flop (FF
0), have two first non-conjunctions (RF) of putting 0 input, have two second non-conjunctions (SF) of putting 1 input and form the first JK flip-flop (FF
0) the output of (R) termination first non-conjunction (RF), the first JK flip-flop (FF
0) the output of (S) termination second non-conjunction (SF), the first JK flip-flop (FF
0) input end of clock meet (CP
0), two output is respectively the first output (Q
0) and the second output (Q
0); A described asynchronous quinary counter is by second to the 4th JK flip-flop (FF
1-FF
3), have two first non-conjunctions (RF) of putting 0 input, have two second non-conjunctions (SF) of putting 1 input and form the second JK flip-flop (FF
1) and the 4th JK flip-flop (FF
3) input end of clock meet (CP
1); The 3rd JK flip-flop (FF
2) input end of clock meet the second JK flip-flop (FF
1) the first output (Q
1), the 4th JK flip-flop (FF
3) the output of (S) termination second non-conjunction (SF), the 4th JK flip-flop (FF
3) first input termination second JK flip-flop (FF of " with door " of (J) end
1) the first output (Q
1), its another input termination the 3rd JK flip-flop (FF
2) the first output (Q
2); It is characterized in that the second and the 3rd JK flip-flop (FF
1, FF
2) two inputs of " with door " of (R) end connect the output of first non-conjunction (RF) and second non-conjunction (SF) respectively; The second and the 3rd JK flip-flop (FF
1, FF
2) (S) end connect high level or unsettled all the time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510012648 CN1738207B (en) | 2005-07-06 | 2005-07-06 | Asynchronous decade counter IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510012648 CN1738207B (en) | 2005-07-06 | 2005-07-06 | Asynchronous decade counter IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1738207A CN1738207A (en) | 2006-02-22 |
| CN1738207B true CN1738207B (en) | 2010-05-05 |
Family
ID=36080887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510012648 Expired - Fee Related CN1738207B (en) | 2005-07-06 | 2005-07-06 | Asynchronous decade counter IC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1738207B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916691B (en) * | 2012-11-06 | 2015-06-24 | 南通大学 | BCD (binary-coded decimal) decimal counter based on reversible logic |
| CN104258556A (en) * | 2014-10-27 | 2015-01-07 | 成都锐奕信息技术有限公司 | Sit-up exercise counting circuit |
| CN111224662A (en) * | 2019-12-27 | 2020-06-02 | 河源广工大协同创新研究院 | Pulse neural network code conversion circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU744999A1 (en) * | 1978-01-25 | 1980-06-30 | Предприятие П/Я А-1923 | Reversible decimal counter |
| SU1330757A1 (en) * | 1985-09-26 | 1987-08-15 | Предприятие П/Я А-1001 | Decade counter for heptasegment indicators |
-
2005
- 2005-07-06 CN CN 200510012648 patent/CN1738207B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU744999A1 (en) * | 1978-01-25 | 1980-06-30 | Предприятие П/Я А-1923 | Reversible decimal counter |
| SU1330757A1 (en) * | 1985-09-26 | 1987-08-15 | Предприятие П/Я А-1001 | Decade counter for heptasegment indicators |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1738207A (en) | 2006-02-22 |
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Granted publication date: 20100505 Termination date: 20110706 |