CN105141286A

CN105141286A - Digital filter filtering single clock cycle pulses and glitches

Info

Publication number: CN105141286A
Application number: CN201510674343.0A
Authority: CN
Inventors: 刘晓云
Original assignee: CHENGDU MOYI TECHNOLOGY Co Ltd
Current assignee: CHENGDU MOYI TECHNOLOGY Co Ltd
Priority date: 2015-10-16
Filing date: 2015-10-16
Publication date: 2015-12-09
Anticipated expiration: 2035-10-16
Also published as: CN105141286B

Abstract

The invention discloses a digital filter filtering single clock cycle pulses and glitches, which comprises a voltage comparator, a first logic circuit and a second logic circuit, wherein the first input end of the voltage comparator is connected with the QN end of the second logic circuit; the second input end of the voltage comparator inputs standard clock signals; the output end of the voltage comparator is connected with the CLK end of the first logic circuit; the D end of the first logic circuit is respectively connected with the QN end of the first logic circuit and the CLK end of the second logic circuit; the D end of the second logic circuit is connected with the QN end of the second logic circuit; and the NCLK end of the first logic circuit and the NCLK end of the second logic circuit both input original digital signals. The standard fixing clock and a capacitance delay mode by current are combined, comparatively large flexibility and space are provided for system design, and system design complexity is reduced.

Description

The digital filter of filtering one clock period pulse and burr

Technical field

The present invention relates to a kind of integrated circuit, particularly relate to the digital filter of a kind of filtering one clock period pulse and burr.

Background technology

Traditional digit pulse and burr filtering have two kinds of modes:

(1) with the filtering digit pulse of simulation resistance-capacitance circuit and the burr of standard;

(2) with electric current to the delayed mode filtering digit pulse of electric capacity and burr.

But all there is following defect in above-mentioned two kinds of modes:

(1) by the digital filtering method of the Analogical Electronics of standard, because its principle more complicated is slow, effectively can not eliminate the impact of the parasitic parameter, precision, temperature etc. of device in analog circuit, thus make filtering not be stable, reduce the reliability of system.

(2) by the delayed mode digital filtering method of electric current to electric capacity, the design of system can be allowed more complicated thus increase the difficulty designed, the selection of filter capacitor also can be had any problem, effectively can not utilize the time.

Therefore above-mentioned two kinds of modes all exist not only wastes area and time and accuracy but also not high situation, just embodies significant limitation, thus limit the flexibility of design in the design of Modern New electronic system.

Summary of the invention

Object of the present invention is just the digital filter providing a kind of filtering one clock period pulse and burr in order to solve the problem.

The present invention is achieved through the following technical solutions above-mentioned purpose:

The digital filter of a kind of filtering one clock period pulse and burr, comprise voltage comparator, first logical circuit and the second logical circuit, the first input end of described voltage comparator is held with the QN of described second logical circuit and is connected, second input input standard clock signal of described voltage comparator, the output of described voltage comparator is held with the CLK of described first logical circuit and is connected, the D end of described first logical circuit is held with the QN of described first logical circuit respectively and the CLK of described second logical circuit holds and is connected, the D end on described second logic electricity ① road is held with the QN of described second logical circuit and is connected, the NCLK end of described first logical circuit all inputs raw digital signal with the NCLK end 2. stating the second logical circuit, the Q end of described second logical circuit is effective output signal negative terminal of filtering burst pulse and burr, the QN end of described second logical circuit is effective output signal anode of filtering burst pulse and burr.

Particularly, described first logical circuit and described second logical circuit are d type flip flop, and low level resets.

Beneficial effect of the present invention is:

The digital filter of a kind of filtering one clock period pulse of the present invention and burr is not when wasting area and time, by standard fixed clock and electric current, two of capacitance delays mode kinds are combined, for system provides sizable flexibility and spatiality, more system can be adapted to.Fixed clock pulse bandwidth filtering can be selected not wasting in area, time saving situation, be conducive to the complexity reducing system like this.

Accompanying drawing explanation

Fig. 1 is the circuit structure diagram of the digital filter of a kind of filtering one clock period pulse of the present invention and burr.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described:

As shown in Figure 1, the digital filter of a kind of filtering one clock period pulse of the present invention and burr, comprise voltage comparator U, first logical circuit D1 and the second logical circuit D2, the first input end IN1 of voltage comparator U holds with the QN of the second logical circuit D2 and is connected, 3. clock signal is marked in the second input IN2 input of voltage comparator U, the output OUT of voltage comparator U holds with the CLK of the first logical circuit D1 and is connected, the D end of the first logical circuit D1 is held with the QN of the first logical circuit D1 respectively and the CLK of the second logical circuit D2 holds and is connected, the D end of the second logical circuit D2 is held with the QN of the second logical circuit D2 and is connected, the NCLK end of the first logical circuit D1 and the NCLK end of the second logical circuit D2 all input raw digital signal, the Q end of the second logical circuit D2 is effective output signal negative terminal OUTN of filtering burst pulse and burr, the QN end of the second logical circuit D2 is effective output signal anode OUT of filtering burst pulse and burr, first logical circuit D1 and the second logical circuit D2 is d type flip flop, and low level resets.

When not wasting area and time, by standard fixed clock recurrent pulse and electric current to the delayed mode of electric capacity by together with two kinds of method integration, by selecting a kind of filtering mode to carry out filtering to one clock period pulse and burr after carrying out comprehensive descision to standard fixed clock recurrent pulse, wherein comprehensive judging method is realized by circuit structure provided by the invention, and specific works principle is as follows:

The present invention will input the clear terminal as two logical circuits (D1/D2), to control the filtering of burst pulse and burr, logical circuit (D1/D2) shown in Fig. 1 is low level and resets, so can the burst pulse of filtering high level and burr (being namely input as low level situation under normal circumstances), because circuit is after initialization, export as high level " 1 ", and itself and standard fixed clock recurrent pulse are done NAND operation, now, get non-by this clock, as the clock of the first logical circuit D1.

When being input as high level " 1 ", due to the impact of logical circuit and NAND gate, one to two clock cycle are needed to export corresponding level, i.e. low level " 0 ", now exports and does with non-with standard fixed clock recurrent pulse, standard fixed clock recurrent pulse shielded, in this case, if input has low level burst pulse, then logical circuit is cleared, and exports and puts 1; When being namely input as high level, low level burst pulse can not be shielded.

When being input as low level " 0 ", logical circuit is reset always, then export as high level " 1 ", when there is high level burst pulse, need through two to three clock cycle because logical circuit bears results, so the high level burst pulse and the burr that are less than two clock cycle can by filterings.So this circuit can realize the function of filtering lower than a clock period pulse and burr.

Technical scheme of the present invention is not limited to the restriction of above-mentioned specific embodiment, the technology distortion that every technical scheme according to the present invention is made, and all falls within protection scope of the present invention.

Claims

1. the digital filter of a filtering one clock period pulse and burr, it is characterized in that: comprise voltage comparator, first logical circuit and the second logical circuit, the first input end of described voltage comparator is held with the QN of described second logical circuit and is connected, second input input standard clock signal of described voltage comparator, the output of described voltage comparator is held with the CLK of described first logical circuit and is connected, the D end of described first logical circuit is held with the QN of described first logical circuit respectively and the CLK of described second logical circuit holds and is connected, the D end of described second logical circuit is held with the QN of described second logical circuit and is connected, the NCLK end of described first logical circuit and the NCLK end of described second logical circuit all input raw digital signal, the Q end of described second logical circuit is effective output signal negative terminal of filtering burst pulse and burr, the QN end of described second logical circuit is effective output signal anode of filtering burst pulse and burr.

2. the digital filter of a kind of filtering one clock period pulse according to claim 1 and burr, is characterized in that: described first logical circuit and described second logical circuit are d type flip flop, and low level resets.