CN201821267U - Circuit for detection and sampling holding of feedback voltage of switching power supply - Google Patents

Abstract

The utility model provides a circuit for detection and sampling holding of feedback voltage of switching power supply, which comprises a clock control circuit, a sampling holding circuit, a waiting state control circuit, a learning state control circuit, an increment control circuit, a system control circuit and a time delay circuit, wherein the clock control circuit controls a sampling clock; the sampling holding circuit samples input voltage in two paths in a time division way, selects and outputs a larger value; the waiting state control circuit controls sampling and waits until a wave shape is stable; the learning state control circuit controls a time sequence of a learning state; the increment control circuit controls and realizes incremental circuits which are adjacently sampled by two times; the system control circuit cooperates with other circuits to control a finite-state machine together; and the time delay circuit realizes needed time delay. In the utility model, all control circuits cooperatively work to realize the self-adaptive learning on the slope of an input signal, the detection on a demagnetization end point and the sampling holding of the value of the system feedback voltage. The sampling precision is high, the requirements on the parameters of a transformer are lower, and the material cost of the power supply and the later test cost can be reduced.

Description

A kind of circuit that is used for switch power supply feedback voltage detection and sampling maintenance

Technical field

The utility model relates to integrated circuit.In particular, the utility model relates to a kind of control circuit of switching power source chip.

Background technology

Switching Power Supply has been widely used in the various electronic equipments.For safety, Switching Power Supply adopts transformer isolation, and isolation just is provided between primary and secondary.Stable for system's output, system will be operated under the negative feedback closed loop state.Classical way is to wait with photoelectric coupled device and TL431 to realize isolated feedback.But system cost can increase much like this.In order to reduce cost, the existing now auxiliary winding of transformer that utilizes is realized the feedback that power supply is exported, and certainly, this mode is also isolated, safety.But a lot of technology are the accurately feedback voltage of measuring transformer, for example United States Patent (USP) of Randolph D.W.Shelly (US4302803) " Rectifier-converter power supply with multi-channel flybackinverter " all.Therefore, develop many primary side control technologys recently and be used for accurate measurement to transformer voltage, for example people's such as Yang United States Patent (USP) (US6853563B1) " Primary-side controlled flyback power converter "; People's such as Yang United States Patent (USP) (US7016204B2) " Close-loop PWM controller for primary-sidecontrolled power converters "; The Chinese patent of Yang Dayong (CN100508346C) " sample circuit of power supply changeover device and testing circuit ".Yet the accuracy of these prior aries is not high, and the feedback voltage error of being sampled is big, output voltage that can not accuracy-control system.And the coherence request height to transformer parameter has increased product cost.Therefore, be starved of the performance that new technology improves this type of power supply.

The utility model content

The purpose of this utility model is for the Switching Power Supply control chip provides accurate detection and sampling hold circuit to feedback voltage, and demagnetization curve that can the self adaptation transformer is to obtain Voltage Feedback value accurately.

The technical solution of the utility model is as follows:

A kind of circuit that is used for switch power supply feedback voltage detection and sampling maintenance, it is characterized in that, realization is opened the finite state machine that state, wait state, learning state, detected state and degaussing done state constitute by PWM, the state exchange and the output of control finite state machine, described circuit specifically comprises:

Clock control circuit, it produces three tunnel clock signals, wherein the first via clock signal and the second tunnel clock signal are used for the sampling to switch power supply feedback voltage, the first via clock signal and the second tunnel clock signal are controlled by the degaussing end signal simultaneously, forbid the first via clock signal and the second tunnel clock signal when degaussing finishes; The Third Road clock signal is used for the control of finite state machine; And

Sampling hold circuit, its to feedback voltage at first use the voltage follower buffer compartment from, divide two-way sampling then, the two-way sampled value is selected higher value output through getting the higher value circuit; And

The wait state control circuit enters wait state after the detection of switch power supply feedback voltage and sampling hold circuit reset, and utilizes the Third Road clock timing, control sampling and wait waveform stabilization during this, and produce the learning state clock; And

Learning state control circuit, wait state finish the laggard study state of going into, and utilize the learning state clock timing, are used to control the sequential of learning state during this, realize learning functionality to the transformer demagnetization curve in conjunction with increment control circuit and system, control circuit; And

The increment control circuit, it is at learning state, and associative learning state control circuit, system, control circuit etc. are used from the increment circuit of twice neighbouring sample of control, and the value that keeps output when sampling is during greater than real-time voltage and increment sum, increase increment, otherwise remain unchanged; And

System, control circuit, it is at wait state, learning state, detected state and degaussing done state, and collaborative other circuit are controlled the state exchange and the output of finite state machine together; And

Delay circuit is used for the rising edge and the trailing edge of supplied with digital signal are handled, and realizes the time-delay that needs.

Above-mentioned clock control circuit comprises:

Clock generation circuit, the pulse signal in its vibration generation cycle;

First trigger, it is used for the pulse signal in the cycle of clock generation circuit output is carried out frequency division;

Second trigger, it is used to control the first via clock signal and the second tunnel clock signal, opens this two-way clock signal when pwm signal is closed, and closes this two-way clock signal when entering the degaussing done state;

Clock output circuit, it is used to control the first via, the second road and the output of Third Road clock.

Above-mentioned sampling hold circuit comprises:

The input voltage follower, its be used for to the buffer compartment of transformer feedback signal from, output to the switch of two-way sample circuit, and input be provided for the increment control circuit;

First capacitor, it is used to keep the value of first via sampling;

Second capacitor, it is used to keep the value of the second tunnel sampling;

First switch, it is used to respond first via sampling clock, and the first capacitor charge or discharge are controlled in the sampling of the control first via;

Second switch, it is used to respond the second road sampling clock, controls the second tunnel sampling, controls the second capacitor charge or discharge;

Get the higher value circuit, it is used for from the first via sampled value and the second tunnel sampled value, selects higher value, produces first reference signal.

The above-mentioned higher value circuit of getting comprises:

First via voltage follower, its be used for to the buffer compartment of first via sampled signal from;

No. the second voltage follower, its be used for to the buffer compartment of the second tunnel sampled signal from;

First via inhibit signal switch, it is used for response and whether selects first via sustaining voltage value;

The second road inhibit signal switch, it is used for response and whether selects the second tunnel sustaining voltage value;

Two-way sustaining voltage comparator, it is used for the value of the comparison first via sustaining voltage and the second tunnel sustaining voltage, and when first via retention value during greater than the second road retention value, conducting first via inhibit signal switch is selected in this comparator output zero; Otherwise this comparator is output as one, selects conducting the second road inhibit signal switch.

Above-mentioned wait state control circuit comprises:

The wait state counter, it is used for the Third Road clock count, to constitute the time that wait state requires;

Study and monitoring state clock generation circuit are used to control the clock that produces learning state and monitoring state.

Above-mentioned learning state control circuit comprises:

The learning state counter, it is used for the learning state clock count, to constitute the time that learning state requires;

The detected state id signal produces circuit, is used to control the id signal that produces detected state.

Above-mentioned increment control circuit comprises:

Reference current source, it is used to provide reference current;

Current mirror, it is used for that current source is carried out ratio and duplicates, and produces the branch current based on different weight proportions;

The increment control counter, it responds learning state clock, produces the switching signal of each branch current;

The branch current switch, it is used to respond the control of each road branch current;

The detected state switch, it is used under detected state, increases electric current, improves the interference free performance of detected state;

The incremental resistance device, it is used to produce voltage increment, i.e. each branch current and the pressure drop on incremental resistance, this voltage increment adds the output of input voltage follower, produces second reference signal.

The said system control circuit comprises:

First comparator, it is used for comparison first reference signal and second reference signal, and when first reference signal during greater than second reference signal, it is output as one, otherwise is output as zero;

The 3rd trigger, it is used to latch the output of first comparator;

Increment control counter clock generation circuit, its control is created under the learning state, when the 3rd trigger for becoming for the moment, produces a pulse signal to the increment control counter;

The degaussing signal generating circuit, it is controlled under the detected state, and when the 3rd trigger becomes for the moment, detected state finishes, and enters the degaussing done state.

Above-mentioned delay circuit comprises:

The PMOS that is used to charge;

The NMOS that is used to discharge;

Delay capacitor, it produces trailing edge and rising edge slowly slowly together with PMOS that is used to charge and the NMOS that is used to discharge respectively;

Schmidt trigger, it is used for the voltage of delay capacitor is become rising edge and the steeper ordinary numbers signal of trailing edge;

Output regulation circuit, it is used to adjust the phase place and the driving force of delay circuit output.

Detection described in the utility model and sampling keep, and its signal is from the signal of transformer ancillary coil output and through electric resistance partial pressure.The signal of described transformer ancillary coil output is relevant with switch power source output voltage.

The various control circuits of the utility model are collaborative works, realize the adaptive learning to the input signal slope, and to the detection of degaussing end point, and sampling keeps the value of system feedback voltage.

The utlity model has automatic study demagnetization curve slope function, the precision height of sampling, within the specific limits, the variation of transformer parameter can not influence the precision of its sampling.Parameter request to transformer is lower, reduces power material cost and later stage testing cost.

Description of drawings

Fig. 1 is an application circuit schematic diagram of using switch power controller of the present utility model;

Fig. 2 is an internal structure schematic diagram of using switch power controller of the present utility model;

Fig. 3 is the handling process schematic diagram of finite state machine of the present utility model;

Fig. 4 is that the utility model is used for the detection of switch power supply feedback voltage and the preferential embodiment schematic diagram of sampling hold circuit;

Fig. 5 be embodiment of the present utility model get the higher value circuit diagram;

Fig. 6 is the increment control circuit schematic diagram of embodiment of the present utility model;

Fig. 7 is the clock control circuit schematic diagram of embodiment of the present utility model;

Fig. 8 is the wait state control circuit schematic diagram of embodiment of the present utility model;

Fig. 9 is the learning state control circuit schematic diagram of embodiment of the present utility model;

Figure 10 is the delay circuit schematic diagram of embodiment of the present utility model;

Figure 11 is the part signal waveform schematic diagram of the utility model embodiment.

Embodiment

Below by example the utility model is described further, but it should be noted that, the purpose of publicizing and implementing example is to help further to understand the utility model, but it will be appreciated by those skilled in the art that: in the spirit and scope that do not break away from the utility model and appended claim, various substitutions and modifications all are possible.Therefore, the utility model should not be limited to the disclosed content of embodiment, and the claimed scope of the utility model is as the criterion with the scope that claims define.

Fig. 1 is a Switching Power Supply typical case schematic diagram of using the auxiliary winding feedback of transformer.As shown in the figure, transformer 10 has three windings among the figure, is respectively primary coil, secondary coil and ancillary coil, and is corresponding, and Np is the number of turn of primary coil, and Ns is the number of turn of secondary coil, and Na is the number of turn of ancillary coil.

For the stable regulation output voltage VO, switch power controller is realized by the switch of power controlling pipe 40.When opening power tube 40, transformer 10 beginning energy storage are just magnetized, and input voltage VIN is coupled to elementary winding, the electric current that magnetizes flow through primary coil, power tube 40 and the resistor 45 of transformer 10, this electric current is input to switch power controller 80 through resistor 45 with voltage signal CS; When switch-off power pipe 40, transformer 10 beginning degaussings, output voltage is provided by secondary winding, gives capacitor 25 chargings and output VO through rectifier diode 20, and after rectifier diode 20 electric currents were zero, output voltage was just provided by capacitor 25.The feedback voltage of Switching Power Supply is exported by ancillary coil, is input to switch power controller 80 as the VS signal after voltage process resistor 30 and 35 dividing potential drops; Simultaneously, the voltage of ancillary coil gives capacitor 60 chargings through rectifier diode 55, and gives chip controller 80 power supplies, imports by VDD; When rectifier diode 55 electric currents were zero, the chip operation electric current was mainly provided by capacitor 60; In system starting process, mainly finish to switch power controller 80 power supplies by resistor 50 and capacitor 60.Capacitor 70 is error amplifiers of compensated switching power supply controller inside.

In the degaussing end point, rectifier diode 20 electric currents are zero, and at this time VO just equals the secondary coil output voltage of transformer 10, and then according to the characteristic of transformer, the output voltage that can draw ancillary coil is

$V_{\mathrm{AUX}}=\frac{\mathrm{Na}}{\mathrm{Ns}}\×\mathrm{VO}---\left(1\right)$

Wherein Na and Ns are respectively the number of turn of ancillary coil of transformer 10 and the number of turn of secondary coil.

Because the dividing potential drop of resistor 30 and 35 is so the VS signal voltage is

$V_{\mathrm{VS}}=\frac{R35}{R30+R35}\×V_{\mathrm{AUX}}---\left(2\right)$

Wherein, R30 and R35 are respectively the resistance value of resistor 30 and 35.

Can be got by (1) and (2), the VS signal voltage is that output voltage VO multiply by a coefficient, promptly

$V_{\mathrm{VS}}=\frac{R35}{R30+R35}\×\frac{\mathrm{Na}}{\mathrm{Ns}}\×\mathrm{VO}---\left(3\right)$

Should be realized that Fig. 1 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.

Fig. 2 is the schematic diagram of the switch power controller 80 among Fig. 1.As shown in the figure, 100 is the detection and the sampling hold circuit of switch power supply feedback voltage among the figure, and its input comprises pwm switching signal S_PWM and power-on reset signal POR, and from the output signal V of the ancillary coil of transformer 10 _AUXVoltage division signal VS, output is exactly VSDET, is input to error amplifier 84 with reference voltage 83, the compensation of the output COMV CSET of error amplifier.The output of error amplifier input and another input signal of device 85 is as a comparison compared, and this signal is from the output of adder 82.The CS signal is through after rising edge removes interfered circuit 81, is input to the negative input end that is input to comparator 85 after adder 82 and the sawtooth signal RAMP addition.When comparator 85 was output as zero, the S_PWM signal was with regard to vanishing, switch-off power pipe 40.Simultaneously, after the CS signal removed interfered circuit 81 through rising edge, another road is input to comparator 87 and reference voltage 86 compares, and realizes overcurrent protection (OCP) function, and when promptly comparator 87 was output as zero, S_PWM exported also vanishing, switch-off power pipe 40.Comparator 85 and comparator 87 output to NAND gate 88, and its result outputs to NOR gate 91.Signal generator 89 produces periodic signal CK_PWM and outputs to NOR gate 90, with opening of control S_PWM signal period.NOR gate 90 and 91 is formed rest-set flip-flop.The serrated signal RAMP that signal generator 89 also produces the cycle simultaneously makes current compensation and uses.Thermal-shutdown circuit 92 produces the excess temperature signal, and when temperature surpassed preset temperature, OTP was one just, closes the S_PWM signal.Electric power management circuit 93 produces power-on reset signal POR and internal electric source signal VCC, produces overvoltage protection signal OVP simultaneously, and when voltage surpassed predeterminated voltage, OVP just was one, turn-offs the S_PWM signal.The output of NOR gate 94 is the S_PWM signal.After the S_PWM signal outputed to drive circuit 95, output GATE signal driving power pipe 40 was to realize regulating the purpose of output.

Should be realized that Fig. 2 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.Such as, use according to some, be operated in duty ratio less than 50% DCM pattern, then do not need the sawtooth waveforms compensation, system will revise accordingly as required.

Fig. 3 is the handling process schematic diagram of the finite state machine of the detection of switch power supply feedback voltage and sampling hold circuit 100.As shown in the figure, a complete Switching Power Supply switch periods is divided into five states, is followed successively by PWM and opens state, wait state, learning state, detected state and degaussing done state.These five states constitute finite state machine, by the state exchange and the output of control finite state machine, realize the detection and the sampling of feedback voltage are kept.This finite state machine operation is as follows: at first, in the PWM cycle, system enters PWM and opens state; After PWM closes, after promptly switch power supply power tube is closed, enter wait state, wait for waveform stabilization, begin two-way time sharing sampling feedback voltage, and export with higher value; Then, enter learning state, the slope of study demagnetization curve, when first reference signal during greater than second reference signal, increment increases a step-length, otherwise increment remains unchanged, and each study clock signal period is all judged once in learning state, finish up to learning state, and final adaptive learning goes out the increment of adjacent sampling; Then, enter detected state, when detecting first reference signal greater than second reference signal, detected state finishes; At last, enter the degaussing done state, stop sampling, keep feedback voltage until till the next switching signal end-of-pulsing of Switching Power Supply; Behind the PWM end cycle, the degaussing done state finishes, and system enters PWM automatically and opens state; Circulation successively.In order to simplify circuit, reduce chip area, the state that has is not established the status indicator signal, just according to the circuit needs corresponding signal is set.

Fig. 4 is that the utility model is used for the detection of switch power supply feedback voltage and the preferential embodiment schematic diagram of sampling hold circuit.As shown in the figure, the VS signal is input to sampling hold circuit.Amplifier 130 is formed the input voltage follower, exports the VSBUFF signal then.The VSBUFF signal is divided into three the tunnel, wherein one the tunnel outputs to increment control circuit 300; Two-way outputs to the switch of sample circuit in addition.This sample circuit is with the two-way time-sharing work, and first routing switch 110 (first switch) and capacitor 115 (first electric capacity) are formed; Secondary route switch 120 (second switch) and capacitor 125 (second electric capacity) are formed.Switch 110 and 120 control end are one effective, and promptly control end is a switch conduction for the moment.This two paths of signals is input to CHA and CHB respectively and gets in the higher value circuit 200, output higher value VSDET (first reference signal).

Control clock SCKA, the SCKB of two-way sampled signal and system clock SYSCK are by clock control circuit 400 outputs, clock control circuit 400 is input as the RSTN signal and degaussing finishes id signal S_DEMAG_END, and wherein the RSTN signal is the output of power-on reset signal POR and PWM status signal S_PWM process NOR gate 140.

The SYSCK signal is input to wait state control circuit 500, waits for the degaussing signal stabilization, finishes back clock signal CK_LRN_DET in wait state.This signal divides two-way: the one tunnel is input to learning state control circuit 600; Another road is input to inverter 150.In learning state control circuit 600, the control learning state, and after learning state finishes, enter detected state.The output of inverter 150 divides two-way, and the first via outputs to d type flip flop 180 (the 3rd trigger) clock end; The second tunnel output outputs to and door 155 through delay circuit 700, with two other input of door 155 be the output of S_DETECTB and d type flip flop 180, be output as signal CK_LRN with door 155, clock is provided for increment control circuit 300.Delay circuit 700 and constitute increment control counter clock generation circuits with door 155.The increment control circuit when learning state, the increment of twice neighbouring sample of adaptive learning.VSBUFF voltage of signals value adds that the increment of twice neighbouring sample of adaptive learning constitutes VSPDLT signal (second reference signal).When VSDET signal during greater than the VSPDLT signal, when promptly first reference signal was greater than second reference signal, d type flip flop 180 was output as one, simultaneously because be learning state, so S_DETECTB is one, then clock CK_LRN signal produces a pulse, increases existing increment; When the VSDET signal is less than or equal to the VSPDLT signal, when promptly first reference signal is less than or equal to second reference signal, represent that current the needs increases.Each clock signal C K_LRN_DET of learning state can compare VSDET signal and VSPDLT signal, and according to comparative result decision whether increasing increment.Like this, though during degaussing once very big external interference signal, its error maximum is an increment step-length just.Finish when learning time, after promptly learning state finishes, enter detected state, then CK_LRN is zero, and expression can not adjusted increment, promptly uses the increment of learning state adaptive learning under detected state.By comparator 160 (first comparator) or door 170, and and trigger 180 and judge whether that with door 190 degaussing finishes.Wherein or door 170 and constitute the degaussing signal generating circuits with door 190.At detected state, when VSDET signal during greater than the VSPDLT signal, when promptly first reference signal is greater than second reference signal, the expression degaussing finishes, S_DEMAG_END is one, closing the SCKA and the SCKB two-way sampling clock of clock control circuit 400, stop sampling, is that wait state just begins sampling after the PWM to next system cycle opens state.It is exactly the value of the VS of degaussing end point that VSDET opens under the state at degaussing done state and PWM.

Should be realized that Fig. 4 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.

Fig. 5 is the schematic diagram of getting higher value circuit 200 among Fig. 4.As shown in the figure, CHA is input to the voltage follower of forming with amplifier 210 (first via voltage follower), passes through switch 220 (first via inhibit signal switch) then; CHB is input to the voltage follower of forming with amplifier 230 (No. the second voltage follower), passes through switch 240 (the second road inhibit signal switch) then.Switch 220 and 240 control end are one effective, and promptly control end is a switch conduction for the moment.CHA and CHB receive the negative input end and the positive input terminal of comparator 250 (two-way sustaining voltage comparator) respectively, and its comparative result is input to control switch 240 and process inverter 260 back control switchs 220.One end of switch 220 and switch 240 directly links to each other, and its value is exactly VSDET.As CHA during greater than CHB, VSDET equals CHA; Otherwise VSDET equals CHB.

Should be realized that Fig. 5 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.

Fig. 6 is the schematic diagram of the increment control circuit 300 among Fig. 4.As shown in the figure, the voltage that the voltage of VSPDLT equals VSBUFF adds the voltage at resistor 360 (incremental resistance device) two ends, that is:

VSPDLT＝VSBUFF+I360×R360?(4)

Wherein I360 is the current value on the resistor 360, and R360 is the resistance value of resistor 360.

This increment control circuit is exactly the electric current of regulating on the resistor 360 of flowing through.This electric current is the summation of four road electric currents.PMOS pipe 310,320,330,340 and 350 constitutes current mirror, the source-drain electrode electric current of PMOS pipe 320,330,340 and 350 all is that source-drain electrode electric current with PMOS pipe 310 is a ratio, and the source-drain electrode electric current of PMOS pipe 310 equals the electric current of current source 315 (reference current source), characteristic and each PMOS pipe 310,320,330 according to current mirror, 340, the proportionate relationship of 350 W/L is when each electric current is effective

I320＝4×I315；I330＝2×I315；I340＝1×I315；I350＝0.5×I315；(5)

Wherein I320, I330, I340 and I350 are respectively the source-drain electrode electric current of the PMOS pipe 320,330,340 and 350 of flowing through, and I315 is the electric current of current source 315.

PMOS pipe 325,335,345,355 is formed the branch current switch, the source-drain electrode electric current of the PMOS that flows through pipe 320,330,340 and 350 is branched current switch control respectively, wherein the control signal of PMOS pipe 355 (detected state switches) is the S_DETECTB signal, expression has only when S_DETECTB is zero this electric current just effectively, promptly just effective when limited state machine is in detected state, in order that increase the noise margin that detects the degaussing end point.The source-drain electrode current ratio of other three road PMOS pipe 320,330,340 is 4: 2: 1, three's sum be 7 times to the I315 electric current.Constitute the increment control counter by d type flip flop 370,380,390, the clock signal of this counter is CK_LRN.Control signal B2B, B1B, B0B come the high, medium and low position of independent increment control counter respectively.

Should be realized that Fig. 6 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.Such as, the current mirror that can substitute with the current mirror of cascodes as scheme to show; Can realize increment control with more or less increment control counter, rather than just in time use three to realize, thereby make the adaptive expanded range of slope or dwindle.

Fig. 7 is the schematic diagram of the clock control circuit 400 among Fig. 4.As shown in the figure, periodic signal generator 410 (clock generation circuit) produces periodic signal, and this signal divides two-way, one tunnel frequency dividing circuit through d type flip flop 420 (first trigger) composition, output frequency division signal; Another road is through delay circuit 430, and this delay circuit is the same with delay circuit 700 structures among Fig. 4.Be input to and door 440 and 445 through the signal of d type flip flop 420 frequency divisions with through the signal that delay circuit is delayed time, reformulate clock signal C KA and CKB that two-way does not have burr.CKA and CKB is input to or door 450, clock signal SYSCK simultaneously.CKA and CKB are input to and door 490 and 495 with signal S_WAIT_LEARN_DETECT respectively, output sampling clock SCKA and SCKB.Delay circuit 430, with door 440,445,490,495 and or door 450 form clock output circuits.The S_PWM signal is through delay circuit 460, and this delay circuit is the same with delay circuit 700 structures among Fig. 4; Be input to inverter 470 then, its output is as the clock signal of d type flip flop 480 (second trigger), and the trailing edge that is illustrated in the S_PWM signal is after time-delay a period of time, and the S_WAIT_LEARN_DETECT signal becomes one; The reset signal of trigger 480 is RSTN, is the output of NOR gate 140 among Fig. 4, expression when system powers on or PWM reset when opening, S_WAIT_LEARN_DETECT is zero.

Should be realized that Fig. 7 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.Such as, replace d type flip flop 480 with rest-set flip-flop.

Fig. 8 is the schematic diagram of the wait state control circuit 500 among Fig. 4.Mainly be made of wait state counter, study and monitoring state clock generation circuit, wherein the wait state counter comprises that d type flip flop 520,530,540 or door 510 reach and door 550; Study and monitoring state clock generation circuit are by forming with door 560 and delay circuit 570.Be output as zero with door 550 when resetting as shown in the figure; After the end that resets, the SYSCK clock begins to the wait state rolling counters forward, when being output as for the moment with door 550, then stop counting, and hold mode is constant.When being output as for the moment with door 550 and SYSCK is input to and door 560, its output is removed burr, final output signal CK_LRN_DET through delay circuit 570.This delay circuit 570 is the same with delay circuit 700 structures among Fig. 4.

Should be realized that Fig. 8 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.Such as the wait state counter is not just in time to use three d type flip flops to realize, and is to use more or less d type flip flop, thereby revises the time of wait state.

Fig. 9 is the schematic diagram of the learning state control circuit 600 among Fig. 4.Mainly produce circuit by learning state counter and detected state id signal and constitute, wherein the learning state counter comprises that d type flip flop 610,620,630 reaches and door 640; Detected state id signal generation circuit comprises or door 650 and d type flip flop 660.As shown in the figure, clock signal C K_LRN_DET process is by three d type flip flops 610,620 and 630, the output of these three d type flip flops connects and door 640, when the output of three triggers all is for the moment, then be output as one with door 640, because of connecing with the output of door 640 or the input of door 650, so when being output as for the moment with door 640, or door 650 output also is one, then at next CK_LRN_DET rising edge, and d type flip flop 660 counter-rotatings, S_DETECT is one, S_DETECTB is zero, and the expression learning state finishes, and enters detected state.When S_DETECT is that the D input of d type flip flop 660 remains one for the moment, keep S_DETECT to be until reset signal RSTN is zero.

Should be realized that Fig. 9 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.Such as the learning state counter is not just in time to use three d type flip flops to realize, and is to use more or less d type flip flop, thereby revises the time of learning state.

Figure 10 is the schematic diagram of the delay circuit 700 among Fig. 4.As shown in the figure, signal is input to the inverter of being made up of PMOS pipe 710 (PMOS that are used to charge) and NMOS pipe 715 (NMOS that are used to discharge), and the output of its inverter connects capacitor 720 (delay capacitor), capacitor 720 other end ground connection.Be provided with capacitor 720 charging currents by the W/L that PMOS pipe 710 is set like this; By the W/L that NMOS pipe 715 is set discharging current to capacitor 720 is set.In conjunction with the capacitance of capacitor 720, just can reach purpose like this to signal waveform rising edge and trailing edge time-delay.The input of Schmidt trigger is received in the output of capacitor 720, and this Schmidt trigger is made up of PMOS pipe 730,735,740 and NMOS pipe 745,750,755.Schmidt trigger outputs to by PMOS pipe 760 and NMOS pipe 765 inverters of forming, the output of this inverter is again through managing 775 inverters of forming by PMOS pipe 770 and NMOS, these two reversers constitute output regulation circuit, the signal after the output time-delay at last.

Should be realized that Figure 10 only is an example, those of ordinary skill in the art will recognize many versions, substitute and modification.It should not limit the scope of claim inadequately.

Figure 11 is a part signal waveform schematic diagram of the present utility model.As shown in the figure, the PWM of feedback voltage signal VS, sampled clock signal SCKA and SCKB, sampling inhibit signal VSDET and finite state machine opens state, wait state, learning state, detected state and degaussing done state relation.When detected state detected SCKB, the value of VSDET was actually the VS signal value of last pulse SCKA sampling, as arrow indication among the figure.At detected state, when first reference signal during greater than second reference signal, be the increment sum of VSDET signal greater than real-time VS signal value and adaptive learning, just Δ V as shown in the figure is greater than the increment of adaptive learning, the expression degaussing finishes, at this moment the value of VSDET is exactly the value that last sampling clock SCKA is adopted, and as shown in the figure, has shown corresponding relation.

Figure 11 only is an example, and it should not limit the scope of claim inadequately.Those of ordinary skill in the art will recognize many versions, substitute and modification.

According to embodiment of the present utility model, as can be seen, by a complete PWM cycle is divided into five states, and constitute finite state machine by these five states, by the control of finite state machine, the collaborative work of each several part circuit can adaptive learning transformer demagnetization curve slope, thereby accurately detect the degaussing end point, high accuracy is finished the detection and the sampling maintenance work of system feedback voltage.For some different application, can both obtain accurate system feedback voltage, improved output accuracy; Say from another point of view, because can adaptive learning transformer demagnetization curve slope, the increment that promptly constitutes second reference signal is dynamic, be along with different application and peripheral circuit change and change, compare with the increment that usefulness is fixing, though transformer parameter has changed, but still can accurately find the degaussing end point, still can accurately sample system feedback voltage, thereby the parameter request of transformer reduced, under the prerequisite of guaranteed performance, reduced peripheral transformer coherence request, reduced device cost, the testing cost for product also has certain reduction simultaneously; And because the characteristics of energy adaptive learning transformer demagnetization curve slope, so in certain scope, the transformer with big inductance value both can have been selected by system, also can select the transformer of less inductance value, systematic function is unaffected, if select the transformer of less inductance value, then the transformer size is less, satisfies the requirement of product space miniaturization.

Claims (9)

1. one kind is used for the circuit that switch power supply feedback voltage detects and sampling keeps, and it is characterized in that described circuit specifically comprises:

Clock control circuit, it produces three tunnel clock signals, wherein the first via clock signal and the second tunnel clock signal are used for the sampling to switch power supply feedback voltage, the first via clock signal and the second tunnel clock signal are controlled by the degaussing end signal simultaneously, and the Third Road clock signal is used for the control of finite state machine; And

Sampling hold circuit, its to feedback voltage at first use the voltage follower buffer compartment from, divide two-way sampling then, the two-way sampled value is selected higher value output through getting the higher value circuit; And

The wait state control circuit is used for entering wait state behind the switch power supply feedback voltage detection and the circuit reset that keeps of sampling, and utilizes the Third Road clock timing, control sampling and wait waveform stabilization during this, and generation learning state clock; And

Learning state control circuit, wait state finish the laggard study state of going into, and utilize the learning state clock timing, are used to control the sequential of learning state during this, realize learning functionality to the transformer demagnetization curve in conjunction with increment control circuit and system, control circuit; And

The increment control circuit, it is at learning state, and associative learning state control circuit, system, control circuits etc. are used from the increment circuit of twice neighbouring sample of control, and

System, control circuit, it is at wait state, learning state, detected state and degaussing done state, and collaborative other circuit are controlled the state exchange and the output of finite state machine together; And

Delay circuit is used for the rising edge and the trailing edge of supplied with digital signal are handled, and realizes the time-delay that needs.

2. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said clock control circuit comprises:

Clock generation circuit, the pulse signal in its vibration generation cycle;

First trigger, it is used for the pulse signal in the cycle of clock generation circuit output is carried out frequency division;

Second trigger, it is used to control the first via clock signal and the second tunnel clock signal;

Clock output circuit, it is used to control the first via, the second road and the output of Third Road clock.

3. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said sampling hold circuit comprises:

The input voltage follower, its be used for to the buffer compartment of transformer feedback signal from, output to the switch of two-way sample circuit, and input be provided for the increment control circuit;

First capacitor, it is used to keep the value of first via sampling;

Second capacitor, it is used to keep the value of the second tunnel sampling;

First switch, it is used to respond first via sampling clock, and the first capacitor charge or discharge are controlled in the sampling of the control first via;

Second switch, it is used to respond the second road sampling clock, controls the second tunnel sampling, controls the second capacitor charge or discharge;

Get the higher value circuit, it is used for from the first via sampled value and the second tunnel sampled value, selects higher value, produces first reference signal.

4. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 3, the wherein said higher value circuit of getting comprises:

First via voltage follower, its be used for to the buffer compartment of first via sampled signal from;

No. the second voltage follower, its be used for to the buffer compartment of the second tunnel sampled signal from;

First via inhibit signal switch, it is used for response and whether selects first via sustaining voltage value;

The second road inhibit signal switch, it is used for response and whether selects the second tunnel sustaining voltage value;

Two-way sustaining voltage comparator, it is used for the value of the comparison first via sustaining voltage and the second tunnel sustaining voltage.

5. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said wait state control circuit comprises:

The wait state counter, it is used for the Third Road clock count, to constitute the time that wait state requires;

Study and monitoring state clock generation circuit are used to control the clock that produces learning state and monitoring state.

6. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said learning state control circuit comprises:

The learning state counter, it is used for the learning state clock count, to constitute the time that learning state requires;

The detected state id signal produces circuit, is used to control the id signal that produces detected state.

7. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said increment control circuit comprises:

Reference current source, it is used to provide reference current;

Current mirror, it is used for that current source is carried out ratio and duplicates, and produces the branch current based on different weight proportions;

The increment control counter, it responds learning state clock, produces the switching signal of each branch current;

The branch current switch, it is used to respond the control of each road branch current;

The detected state switch, it is used under detected state, increases electric current, improves the interference free performance of detected state;

The incremental resistance device, it is used to produce voltage increment, i.e. each branch current and the pressure drop on incremental resistance, this voltage increment adds the output of input voltage follower, produces second reference signal.

8. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said system, control circuit comprises:

First comparator, it is used for comparison first reference signal and second reference signal;

The 3rd trigger, it is used to latch the output of first comparator;

Increment control counter clock generation circuit, its control is created under the learning state;

The degaussing signal generating circuit, it is controlled under the detected state.

9. the circuit that is used for switch power supply feedback voltage detection and sampling maintenance according to claim 1, wherein said delay circuit comprises:

The PMOS that is used to charge;

The NMOS that is used to discharge;

Delay capacitor, it produces trailing edge and rising edge slowly slowly together with PMOS that is used to charge and the NMOS that is used to discharge respectively;

Schmidt trigger, it is used for the voltage of delay capacitor is become rising edge and the steeper ordinary numbers signal of trailing edge;

Output regulation circuit, it is used to adjust the phase place and the driving force of delay circuit output.

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