CN209543065U - Timing circuit and electronic stopclock - Google Patents
Timing circuit and electronic stopclock Download PDFInfo
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- CN209543065U CN209543065U CN201920318272.4U CN201920318272U CN209543065U CN 209543065 U CN209543065 U CN 209543065U CN 201920318272 U CN201920318272 U CN 201920318272U CN 209543065 U CN209543065 U CN 209543065U
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Abstract
The utility model is suitable for electronic stopclock technical field, provides a kind of timing circuit and electronic stopclock.The circuit includes RS trigger module, monostable flipflop, Clock generation module and count decoding module, and RS trigger module is all connected with monostable flipflop and Clock generation module；Monostable flipflop is connect with the input terminal of count decoding module, and Clock generation module is connect with the clock end of count decoding module；Trigger RS trigger module starting monostable flipflop and Clock generation module, monostable flipflop provides reset signal for count decoding module, count decoding module count is reset, and Clock generation module provides clock signal for count decoding module, and count decoding module count simultaneously shows timing numerical value.The utility model circuit structure is simple, cost and low energy consumption, and timing is accurate and stablizes.
Description
Technical field
The utility model belongs to electronic stopclock technical field more particularly to a kind of timing circuit and electronic stopclock.
Background technique
With the development of electronic technology, electronic technology is also more and more extensive in the application of every field, and people are to electronics skill
The understanding of art is also gradually deepened, it is desirable that also higher and higher.Such as electronic stopclock, indispensable time set in athletic competition.The electronics second
For table as a kind of common timing tool, type is relatively more, but traditional electronic stopclock circuit structure is complicated, at high cost, timing
Error is big.
Utility model content
In view of this, the utility model embodiment provides a kind of timing circuit and electronic stopclock, to solve the prior art
Middle stopwatch circuit is complicated, at high cost, the big problem of timing error.
The utility model embodiment first aspect provides a kind of timing circuit, comprising: RS trigger module, monostable trigger
Device, Clock generation module and count decoding module；
First output end of the RS trigger module is connect with the input terminal of the monostable flipflop, the RS trigger mode
The second output terminal of block is connect with the input terminal of the Clock generation module；The output end of the monostable flipflop and the meter
The input terminal connection of number decoding module；The clock end of the output end of the Clock generation module and the count decoding module connects
It connects；
It triggers the RS trigger module and starts the monostable flipflop and the Clock generation module, the monostable touching
Hair device provides reset signal for the count decoding module, and the counting of the count decoding module is reset, and mould occurs for the clock
Block provides clock signal for the count decoding module, and the count decoding module count simultaneously shows timing numerical value.
Optionally, the RS trigger module include: first switching element, second switch element, the first NAND gate, second with
NOT gate, first resistor and second resistance；
The first end of the first switching element is grounded, the second end of the first switching element and first NAND gate
First input end connected with the first end of the first resistor；The first end of the second switch element is grounded, and described second
The second end of switch element is connect with the first end of the first input end of second NAND gate and the second resistance；
The second end of the second end of the first resistor and the second resistance is connect with external power supply；
Second input terminal of first NAND gate is connect with the output end of second NAND gate, second NAND gate
The second input terminal connect with the output end of first NAND gate；The output end of first NAND gate is also triggered with the RS
First output end of module connects, and the output end of second NAND gate also connects with the second output terminal of the RS trigger module
It connects.
Optionally, the first switching element and the second switch element are button.
Optionally, the monostable flipflop includes: 3rd resistor, the 4th resistance, first capacitor, third NAND gate,
Four NAND gates and the 5th NAND gate；
The first input end of the third NAND gate and the first end of the 3rd resistor and the monostable flipflop
Input terminal is all connected with, and the second input terminal of the third NAND gate is connect with the output end of the 4th NAND gate, the third
The output end of NAND gate is connect with the first end of the first capacitor；
The second end of the first capacitor and the input terminal of the 4th NAND gate and the first end of the 4th resistance are equal
Connection, the second end ground connection of the 4th resistance；The output end of 4th NAND gate by the 5th NAND gate with it is described
The output end of monostable flipflop connects.
Optionally, the monostable flipflop further include: the 5th resistance and the second capacitor；
The first input end that the input terminal of the monostable flipflop passes through second capacitor and the third NAND gate
Connection, the input terminal of the monostable flipflop also pass through the 5th resistance eutral grounding.
Optionally, the Clock generation module includes: the 6th resistance, variable resistance, the 6th NAND gate, clock generation core
Piece, third capacitor and the 4th capacitor；
The first input end of 6th NAND gate is connect with the input terminal of the Clock generation module, the described 6th with it is non-
Second input terminal of door is connect with the output end that chip occurs for the clock, the output end and the clock of the 6th NAND gate
The output end connection of module occurs；
The ground terminal ground connection of chip occurs for the clock, and the control terminal that chip occurs for the clock passes through the third capacitor
The threshold value end of chip occurs for ground connection, the clock by the 4th capacity earth, and the threshold value end of chip occurs for the clock also
It passes sequentially through the 6th resistance and the variable resistance is connect with external power supply, the discharge end that chip occurs for the clock passes through
The variable resistance is connect with external power supply, and the triggering end that chip occurs for the clock is connect with the threshold value end, the clock
The reset terminal that chip occurs is connect with external power supply with feeder ear.
Optionally, it is 555 timers that chip, which occurs, for the clock.
Optionally, the count decoding module includes: timing unit and coding display equipment；The input of the timing unit
End is connect with the input terminal of the count decoding module, the clock of the clock end of the timing unit and the count decoding module
End connection, the output end of the timing unit are connect with the coding display equipment；
The timing unit is received to count after the reset signal of the monostable flipflop and be reset, and receives the clock
Start timing after the clock signal of module occurs, and timing signal is sent to the coding display equipment, the coding display
Equipment is decoded according to the timing signal and shows timing numerical value.
Optionally, the timing unit includes: the first timing chip, the second timing chip and third timing chip；
First reset terminal of the first timing chip, the second timing chip and the third timing chip is and institute
State the input terminal connection of timing unit, the first timing chip, the second timing chip and the third timing chip
Second reset terminal is connect with external power supply, the first timing chip, the second timing chip and the third timing core
The set end of piece is grounded；
The clock end of the first timing chip is connect with the clock end of the timing unit, the first timing chip
First output end is connect with the clock end of the second timing chip, the first output end of the second timing chip and described the
The clock end of three timing chips connects；All output ends of the second timing chip and the third timing chip with it is described
The output end of timing unit connects.
The utility model embodiment second aspect provides a kind of electronic stopclock, including as embodiment first aspect provides
Described in any item timing circuits.
Existing beneficial effect is the utility model embodiment compared with prior art: the circuit mainly includes RS trigger mode
Block, monostable flipflop, Clock generation module and count decoding module, RS trigger module include at least two switch elements, electricity
Line structure is simple, at low cost；Wherein, triggering RS trigger module starting monostable flipflop and Clock generation module, monostable touching
Hair device provides reset signal for count decoding module, and count decoding module count is reset, and prepares to count, Clock generation module
Clock signal is provided for count decoding module, count decoding module count realizes exact timing, and low energy consumption for integrated circuit, letter
Number stabilization.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of the technical scheme in the embodiment of the utility model
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only that this is practical new
Some embodiments of type for those of ordinary skill in the art without any creative labor, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of timing circuit provided by the embodiment of the utility model；
Fig. 2 is the physical circuit schematic diagram of timing circuit provided by the embodiment of the utility model.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, to understand thoroughly the utility model embodiment.However, it will be clear to one skilled in the art that there is no these
The utility model also may be implemented in the other embodiments of detail.In other situations, omit to well-known system,
The detailed description of apparatus, circuit and method, in case unnecessary details interferes the description of the utility model.
In order to illustrate technical solution described in the utility model, the following is a description of specific embodiments.
Embodiment one
Referring to Fig. 1, a kind of timing circuit provided in this embodiment, comprising: RS trigger module 100, monostable flipflop
200, Clock generation module 300 and count decoding module 400；RS trigger module 100 includes at least two switch elements.RS triggering
First output end of module 100 is connect with the input terminal of monostable flipflop 200, the second output terminal of RS trigger module 100 with
The input terminal of Clock generation module 300 connects；The output end of monostable flipflop 200 and the input terminal of count decoding module 400
Connection；The output end of Clock generation module 300 is connect with the clock end of count decoding module 400.
In concrete application, one of switch element of RS trigger module 100 can be first triggered, then RS trigger module 100
Start monostable flipflop 200, monostable flipflop 200 is that count decoding module 400 provides reset signal, count decoding module
400 count clearing, are ready for timing, avoid the occurrence of error；Then at least two of RS trigger module 100 is triggered simultaneously to open
Element is closed, RS trigger module 100 closes monostable flipflop 200 and starts Clock generation module 300, Clock generation module 300
Clock signal is provided for count decoding module 400, count decoding module 400 starts counting and show timing time, and timing is accurate.
In above-mentioned timing circuit, circuit is simple, at low cost；It triggers RS trigger module 100 and starts 200 He of monostable flipflop
Clock generation module 300, monostable flipflop 200 are that count decoding module 400 provides reset signal, count decoding module 400
It counts and resets, prepare to count, Clock generation module 300 is that count decoding module 400 provides clock signal, count decoding mould
Block 400 counts, and realizes exact timing, and low energy consumption for integrated circuit, signal stabilization.
In one embodiment, referring to fig. 2, RS trigger module 100 may include: first switching element S1, second switch member
Part S2, the first NAND gate U1, the second NAND gate U2, first resistor R1 and second resistance R2.
The first end of first switching element S1 is grounded, and the first of the second end of first switching element S1 and the first NAND gate U1
Input terminal is connected with the first end of first resistor R1；The first end of second switch element S2 is grounded, and the of second switch element S2
Two ends are connect with the first end of the first input end of the second NAND gate U2 and second resistance R2.The second end of first resistor R1 and
The second end of two resistance R2 is connect with external power supply；The output of the second input terminal of first NAND gate U1 and the second NAND gate U2
End connection, the second input terminal of the second NAND gate U2 are connect with the output end of the first NAND gate U1；The output of first NAND gate U1
End is also connect with the first output end of RS trigger module 100, the output end of the second NAND gate U2 also with RS trigger module 100 the
The connection of two output ends.
Illustratively, referring to fig. 2, the RS trigger module 100 of the present embodiment belongs to the trigger that low level directly triggers, and has
The function of direct set, reset, realization start and stop count decoding module 400, wherein the output end of the first NAND gate U1 is made
Output end for the input of monostable flipflop 200, the second NAND gate U2 is believed as the input control of Clock generation module 300
Number.Specifically, first triggering first switching element S1 (ground connection), the first NAND gate U1 exports high level signal, the second NAND gate U2
Low level signal is exported, resets the signal condition of first switching element S1, the first NAND gate U1 and the second NAND gate U2 output not
Become；Second switch element S2 (ground connection) is triggered again, and the second NAND gate U2 exports high level signal, when RS trigger module 100 starts
Module 300 occurs for clock, gets ready for the starting of count decoding module 400, while the first NAND gate U1 exports low level signal, to
Monostable flipflop 200 sends negative pulse, and starting monostable flipflop 200 works, and count decoding module 400 resets and starts to count
Number.
Optionally, first switching element S1 and second switch element S2 all can be button, push-botton operation is convenient, reset letter
Single and safety.First switching element S1 and second switch element S2 may be key or other switch elements, does not do have here
Body limits.
In one embodiment, referring to fig. 2, monostable flipflop 200 may include: 3rd resistor R3, the 4th resistance R4,
One capacitor C1, third NAND gate U3, the 4th NAND gate U4 and the 5th NAND gate U5.The first input end of third NAND gate U3 and
The first end of three resistance R3 and the input terminal of monostable flipflop 200 are all connected with, the second input terminal of third NAND gate U3 and
The output end of four NAND gate U4 connects, and the output end of third NAND gate U3 is connect with the first end of first capacitor C1；First capacitor
The second end of C1 is all connected with the input terminal of the 4th NAND gate U4 and the first end of the 4th resistance R4, the second end of the 4th resistance R4
Ground connection；The output end of 4th NAND gate U4 is connect by the 5th NAND gate U5 with the output end of monostable flipflop 200.
Optionally, monostable flipflop 200 can also include: the 5th resistance R5 and the second capacitor C2；Monostable flipflop
200 input terminal is connect by the second capacitor C2 with the first input end of third NAND gate U3, the input of monostable flipflop 200
End is also grounded by the 5th resistance R5.
Specifically, monostable flipflop 200 is that count decoding module 400 provides reset signal.Monostable flipflop 200
Input triggering is provided by the negative pulse of the first NAND gate U1 output, and monostable flipflop 200 receives negative pulse and passes through the 5th
NAND gate U5 is added to the input terminal of count decoding module 400, and count decoding module 400 is reset.When static, at the 4th NAND gate U4
In off state, therefore the 4th resistance R4 is necessarily less than the shutdown resistance of the 4th NAND gate U4, timing element (the 4th resistance R4 and
One capacitor C1) value is different, and the pulse width that monostable flipflop 200 exports is also different.When triggering negative pulse width is less than defeated
When pulse width out, the 5th resistance R5 and the second capacitor C2 of monostable flipflop 200 can be saved, simplifies circuit, is reduced
Cost.
In one embodiment, referring to fig. 2, Clock generation module 300 may include: the 6th resistance R6, variable resistance RP,
Chip I 1, third capacitor C3 and the 4th capacitor C4 occur for six NAND gate U6, clock.Optionally, chip I 1, which occurs, for clock to be
555 timers.
The first input end of 6th NAND gate U6 is connect with the input terminal of Clock generation module 300, the 6th NAND gate U6's
Second input terminal is connect, the output of the 6th NAND gate U6 with the output end (the OUT pins of 555 timers) that chip I 1 occurs for clock
End is connect with the output end of Clock generation module 300；The ground terminal (GND pins of 555 timers) that chip I 1 occurs for clock connects
Ground, the control terminal (the CTRL pins of 555 timers) that chip I 1 occurs for clock are grounded by third capacitor C3, and chip occurs for clock
The threshold value end (the THR pins of 555 timers) of I1 is grounded by the 4th capacitor C4, and the threshold value end of chip I 1 occurs for clock also successively
Connect by the 6th resistance R6 and variable resistance RP with external power supply, clock occur chip I 1 discharge end (555 timers
DIS pin) it is connect by variable resistance RP with external power supply, (TRIG of 555 timers draws the triggering end of clock generation chip I 1
Foot) it is connect with threshold value end, the reset terminal and feeder ear (the RST pins and VCC pin of 555 timers) that chip I 1 occurs for clock are
It is connect with external power supply.
The multivibrator that the Clock generation module 300 of the present embodiment is mainly made of 555 timers is that a kind of performance is good
With clock source at low cost, the OUT pin of 555 timers can be made to export the pulse of predeterminated frequency by adjusting variable resistance RP
Signal, such as the square-wave signal of 50HZ, when the second NAND gate U2 exports high level signal, the 6th NAND gate U6 is opened, this
When predeterminated frequency pulse signal by the 6th NAND gate U6 be that count decoding module 400 provides accurate and stable clock letter
Number.
In one embodiment, count decoding module 400 may include: timing unit 410 and coding display equipment 420.Meter
The input terminal of Shi Danyuan 410 is connect with the input terminal of count decoding module 400, the clock end and count decoding of timing unit 410
The clock end of module 400 connects, and the output end of timing unit 410 is connect with coding display equipment 420；Timing unit 410 receives
Reset signal to monostable flipflop 200 is reset, and starts timing after receiving the clock signal of Clock generation module 300, is produced
Raw timing signal is sent to coding display equipment 420, and coding display equipment 420 is decoded according to timing signal and shows timing
Numerical value.The coding display equipment 420 of the present embodiment can be made of decoder and display equipment, or including showing equipment
Decoder.
Optionally, referring to fig. 2, timing unit 410 includes: the first timing chip, the second timing chip and third timing core
Piece.Optionally, the first timing chip, the second timing chip and third timing chip can be 74LS90 chip, that is, be respectively
74LS90 (1) chip, 74LS90 (2) chip and 74LS90 (3) chip.
Specifically, the first reset terminal (R of the first timing chip, the second timing chip and third timing chip0(1) pin)
It is connect with the input terminal of timing unit 410, the second reset of the first timing chip, the second timing chip and third timing chip
Hold (R0(2) pin) and power end (UCCPin) it is connect with external power supply, the first timing chip, the second timing chip and third
Set end (the S of timing chip9(1) pin and S9(2) pin) and ground terminal (GND pin) be grounded.First timing chip when
Zhong Duan (the CP of 74LS90 (1) chip2Pin) it is connect with the clock end of timing unit 410, the first output of the first timing chip
Hold (the Q of 74LS90 (1) chipDPin) with the clock end (CP of 74LS90 (2) chip of the second timing chip1Pin) connection, the
The first output end (Q of 74LS90 (2) chip of two timing chipsDPin) with the clock end (74LS90 (3) of third timing chip
The CP of chip1Pin) connection；Output end of the output end of second timing chip and third timing chip with timing unit 410
Connection, the i.e. Q of 74LS90 (2) chipAPin, QBPin, QCPin and QDThe Q of pin and 74LS90 (3) chipAPin, QB
Pin, QCPin and QDPin is connect with coding display equipment 420.
In addition, the CP of 74LS90 (1) chip1Pin is set as high level " 1 ", the CP2 pin of 74LS90 (2) chip with
The Q of 74LS90 (2) chipAPin connection, the CP2 pin of 74LS90 (3) chip and the Q of 74LS90 (3) chipAPin connection.
Specifically, the CP of 74LS90 (1) chip1Pin is set as high level " 1 ", the CP of 74LS90 (1) chip2Pin connects
Clock signal, the Q of 74LS90 (1) chipBPin, QCPin and QDPin output, constitutes quinary counter；74LS90 (2) core
The CP of piece2Pin and its QAPin connection, the CP of 74LS90 (2) chip1Pin meets clock signal, the CP of 74LS90 (3) chip2
Pin and its QAPin connection, the CP of 74LS90 (3) chip1Pin meets clock signal, i.e. 74LS90 (2) chip and 74LS90 (3)
The Q of chipAPin, QBPin, QCPin and QDPin output, constitutes 842l code decade counter.
Illustratively, 74LS90 (1) chip carries out 5 frequency dividings to the clock pulses that frequency is 50Hz, in 74LS90 (1) chip
QDPin obtains the rectangular pulse that the period is 0.1s, and the clock as 74LS90 (2) chip inputs, the Q of 74LS90 (2) chipD
The output of pin is inputted as the clock of 74LS90 (3) chip, and 74LS90 (2) chip and 74LS90 (3) chip constitute 842l code
Input of the output pin of decade counter, 74LS90 (2) chip and 74LS90 (3) chip with coding display equipment 420
End connection, can show the timing of 0.1~0.9s or 1~9.9s, timing is accurate, and error is small.
In above-described embodiment, circuit mainly includes RS trigger module 100, monostable flipflop 200, Clock generation module
300 and count decoding module 400, RS trigger module 100 includes at least two switch elements, and circuit structure is simple, at low cost；Its
In, triggering RS trigger module 100 starts monostable flipflop 200 and Clock generation module 300, and monostable flipflop 200 is meter
Number decoding module 400 provides reset signal, and count decoding module 400, which counts, to reset, and prepares to count, Clock generation module
300 provide clock signal for count decoding module 400, and count decoding module 400 counts, and realize exact timing, and integrated circuit
Low energy consumption, signal stabilization.
Embodiment two
The present embodiment two provides a kind of electronic stopclock, including the timing circuit any in above-mentioned implementation one,
Beneficial effect with any of the above-described kind of timing circuit.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of described device is divided into different functional unit or module, more than completing
The all or part of function of description.Each functional unit in embodiment, module can integrate in one processing unit, can also
To be that each unit physically exists alone, can also be integrated in one unit with two or more units, it is above-mentioned integrated
Unit both can take the form of hardware realization, can also realize in the form of software functional units.In addition, each function list
Member, the specific name of module are also only for convenience of distinguishing each other, the protection scope being not intended to limit this application.Above system
The specific work process of middle unit, module, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, is not described in detail or remembers in some embodiment
The part of load may refer to the associated description of other embodiments.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
Embodiment described above is only to illustrate the technical solution of the utility model, rather than its limitations；Although referring to before
Embodiment is stated the utility model is described in detail, those skilled in the art should understand that: it still can be with
It modifies the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit for various embodiments of the utility model technical solution that it does not separate the essence of the corresponding technical solution
And range, it should all include being within the protection scope of the utility model.
Claims (10)
1. a kind of timing circuit characterized by comprising RS trigger module, monostable flipflop, Clock generation module and counting
Decoding module；
First output end of the RS trigger module is connect with the input terminal of the monostable flipflop, the RS trigger module
Second output terminal is connect with the input terminal of the Clock generation module；The output end of the monostable flipflop is translated with the counting
The input terminal connection of code module；The output end of the Clock generation module is connect with the clock end of the count decoding module；
It triggers the RS trigger module and starts the monostable flipflop and the Clock generation module, the monostable flipflop
Reset signal is provided for the count decoding module, the counting of the count decoding module is reset, and the Clock generation module is
The count decoding module provides clock signal, and the count decoding module count simultaneously shows timing numerical value.
2. timing circuit as described in claim 1, which is characterized in that the RS trigger module includes: first switching element,
Two switch elements, the first NAND gate, the second NAND gate, first resistor and second resistance；
The first end of the first switching element is grounded, and the of the second end of the first switching element and first NAND gate
One input terminal is connected with the first end of the first resistor；The first end of the second switch element is grounded, the second switch
The second end of element is connect with the first end of the first input end of second NAND gate and the second resistance；
The second end of the second end of the first resistor and the second resistance is connect with external power supply；
Second input terminal of first NAND gate is connect with the output end of second NAND gate, and the of second NAND gate
Two input terminals are connect with the output end of first NAND gate；The output end of first NAND gate also with the RS trigger module
The connection of the first output end, the output end of second NAND gate also connect with the second output terminal of the RS trigger module.
3. timing circuit as claimed in claim 2, which is characterized in that the first switching element and the second switch element
It is button.
4. timing circuit as described in claim 1, which is characterized in that the monostable flipflop includes: 3rd resistor, the 4th
Resistance, first capacitor, third NAND gate, the 4th NAND gate and the 5th NAND gate；
The input of the first input end of the third NAND gate and the first end of the 3rd resistor and the monostable flipflop
End is all connected with, and the second input terminal of the third NAND gate is connect with the output end of the 4th NAND gate, the third with it is non-
The output end of door is connect with the first end of the first capacitor；
The second end of the first capacitor is all connected with the input terminal of the 4th NAND gate and the first end of the 4th resistance,
The second end of 4th resistance is grounded；The output end of 4th NAND gate passes through the 5th NAND gate and the monostable
The output end of trigger connects.
5. timing circuit as claimed in claim 4, which is characterized in that the monostable flipflop further include: the 5th resistance and
Second capacitor；
The input terminal of the monostable flipflop is connect by second capacitor with the first input end of the third NAND gate,
The input terminal of the monostable flipflop also passes through the 5th resistance eutral grounding.
6. such as timing circuit described in any one of claim 1 to 5, which is characterized in that the Clock generation module includes: the 6th
Chip, third capacitor and the 4th capacitor occur for resistance, variable resistance, the 6th NAND gate, clock；
The first input end of 6th NAND gate is connect with the input terminal of the Clock generation module, the 6th NAND gate
Second input terminal is connect with the output end that chip occurs for the clock, and the output end and the clock of the 6th NAND gate occur
The output end of module connects；
The ground terminal ground connection of chip occurs for the clock, and the control terminal that chip occurs for the clock is connect by the third capacitor
The threshold value end of chip occurs for ground, the clock by the 4th capacity earth, the clock occur the threshold value end of chip also according to
Secondary to be connect by the 6th resistance and the variable resistance with external power supply, the discharge end that chip occurs for the clock passes through institute
It states variable resistance to connect with external power supply, the triggering end that chip occurs for the clock is connect with the threshold value end, the clock hair
The reset terminal of raw chip is connect with external power supply with feeder ear.
7. timing circuit as claimed in claim 6, which is characterized in that it is 555 timers that chip, which occurs, for the clock.
8. such as timing circuit described in any one of claim 1 to 5, which is characterized in that the count decoding module includes: timing
Unit and coding display equipment；The input terminal of the timing unit is connect with the input terminal of the count decoding module, the meter
The clock end of Shi Danyuan is connect with the clock end of the count decoding module, and the output end of the timing unit and the decoding are aobvious
Show that equipment connects；
The timing unit is received to count after the reset signal of the monostable flipflop and be reset, and is received the clock and is occurred
Start timing after the clock signal of module, and timing signal is sent to the coding display equipment, the coding display equipment
It is decoded according to the timing signal and shows timing numerical value.
9. timing circuit as claimed in claim 8, which is characterized in that the timing unit includes: the first timing chip, second
Timing chip and third timing chip；
First reset terminal of the first timing chip, the second timing chip and the third timing chip with the meter
The input terminal of Shi Danyuan connects, and the second of the first timing chip, the second timing chip and the third timing chip
Reset terminal is connect with external power supply, the first timing chip, the second timing chip and the third timing chip
Set end is grounded；
The clock end of the first timing chip is connect with the clock end of the timing unit, and the first of the first timing chip
Output end is connect with the clock end of the second timing chip, the first output end of the second timing chip and the third meter
When chip clock end connection；All output ends of the second timing chip and the third timing chip with the timing
The output end of unit connects.
10. a kind of electronic stopclock, which is characterized in that including timing circuit as described in any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920318272.4U CN209543065U (en) | 2019-03-13 | 2019-03-13 | Timing circuit and electronic stopclock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920318272.4U CN209543065U (en) | 2019-03-13 | 2019-03-13 | Timing circuit and electronic stopclock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209543065U true CN209543065U (en) | 2019-10-25 |
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| CN201920318272.4U Expired - Fee Related CN209543065U (en) | 2019-03-13 | 2019-03-13 | Timing circuit and electronic stopclock |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112506028A (en) * | 2020-11-19 | 2021-03-16 | 西安热工研究院有限公司 | Black start test node time recording device and method |
| CN114721246A (en) * | 2022-04-29 | 2022-07-08 | 山西新华防化装备研究院有限公司 | Software-free low-temperature-resistant timing timer |
-
2019
- 2019-03-13 CN CN201920318272.4U patent/CN209543065U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112506028A (en) * | 2020-11-19 | 2021-03-16 | 西安热工研究院有限公司 | Black start test node time recording device and method |
| CN112506028B (en) * | 2020-11-19 | 2022-11-22 | 西安热工研究院有限公司 | Black start test node time recording device and method |
| CN114721246A (en) * | 2022-04-29 | 2022-07-08 | 山西新华防化装备研究院有限公司 | Software-free low-temperature-resistant timing timer |
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Granted publication date: 20191025 |