CN208128225U

CN208128225U - A kind of shared oscillator frequency output circuitry and system

Info

Publication number: CN208128225U
Application number: CN201821059716.9U
Authority: CN
Inventors: 曹进伟; 陈孟邦; 蔡荣怀; 邹云根; 张丹丹; 雷先再
Original assignee: Zongren Technology (pingtan) Co Ltd
Current assignee: Zongren Technology (Pingtan) Co.,Ltd.
Priority date: 2018-07-05
Filing date: 2018-07-05
Publication date: 2018-11-20
Anticipated expiration: 2028-07-05

Abstract

The utility model relates to a kind of shared oscillator frequency output circuitry and systems, the period 1 reset signal mainly exported by reset signal processing module is resetted to entire shared oscillator frequency output circuitry and chip, wherein the first chip output third frequency signal is inputted as the External frequency signals of multiple synchronizing chips of rear end, chip is continuously switched between external frequency signal source and internal frequency signal source, multiple chips are realized using shared oscillator rate-adaptive pacemaker, when solving through peripheral control unit sending different coding signal, the clock signal of decoding circuit is strictly matched with encoded signal can be only achieved chip and reaches synchronous, it needs at this time while input control signal and clock signal, chip internal circuits will be made to become the problem of complexity causes chip cost to increase.

Description

A kind of shared oscillator frequency output circuitry and system

Technical field

The utility model relates to oscillator frequency output design field more particularly to a kind of shared oscillator rate-adaptive pacemaker electricity Road and system.

Background technique

Currently, being used mainly in lamp string application circuit in the control application of lamp string and containing address signal matches Then chip issues different encoded signals by peripheral control unit, after decoding via chip internal circuits, be matched to corresponding Sudden strain of a muscle method controls signal to control the blinking sequence of lamp string,

However, when issuing different encoded signals by peripheral control unit, the clock signal and encoded signal of decoding circuit Stringent matching can be only achieved chip and reach synchronous, need at this time while input control signal and clock signal, it will so that chip Internal circuit becomes complicated, considerably increases the manufacturing cost of chip.

Utility model content

The purpose of this utility model is to provide a kind of shared oscillator frequency output circuitry and systems, it is intended to which solution passes through When peripheral control unit issues different coding signal, the clock signal of decoding circuit is strictly matched with encoded signal can be only achieved chip Reach synchronous, need at this time while input control signal and clock signal, it will so that chip internal circuits become complexity and cause The problem of chip cost increases.

A kind of shared oscillator frequency output circuitry provided by the embodiment of the utility model, the shared oscillator frequency are defeated Circuit is connect with External frequency signals source and internal frequency signal source respectively out, the shared oscillator frequency output circuitry packet It includes：

Connect with the External frequency signals source, the External frequency signals for being exported to the External frequency signals source into Row detection, and export the External frequency signals detection module of the first trigger signal and the first reset signal；

It is connect with the internal frequency signal source and the External frequency signals detection module, for the internal frequency The internal frequency signal of rate signal source output is detected, and exports the first oscillator signal, the second oscillator signal and the The internal frequency signal detection module of two trigger signals；

It is connect with the External frequency signals detection module and the internal frequency signal detection module, for according to institute State the first oscillator signal, second oscillator signal and first reset signal output period 1 reset signal Reset signal processing module；

With the External frequency signals source, the External frequency signals detection module, the internal frequency signal source, described Internal frequency signal detection module and reset signal processing module connection, for according to first trigger signal, institute State the second trigger signal, the internal frequency signal and the External frequency signals output first frequency signal, second frequency The signal behavior processing module of signal, third frequency signal and the second reset signal.

Optionally, the External frequency signals detection module includes that External frequency signals input terminal, the second reset signal are defeated Enter end, the first trigger signal output end and the first reset signal output end；

The External frequency signals input terminal is connect with the External frequency signals source, and the External frequency signals detect mould Block further includes：First switch tube, the first phase inverter, the second phase inverter, the first counting unit and the 21st trigger；

The current input terminal of the first switch tube is connect with the first power supply, the electric current output of the first switch tube The input terminal of end and first phase inverter connects the foreign frequency letter as the External frequency signals detection module altogether Number input terminal, the output end of first phase inverter, the input terminal of second phase inverter and first counting unit Second input terminal is connect altogether as the first reset signal output end, and the output end of second phase inverter and described first counts The first input end of unit connects, and the second of the first output end of first counting unit and the 21st trigger is defeated Enter end connection, the second output terminal of first counting unit is connect with the first input end of the 21st trigger, institute The reset terminal of the reset terminal and the 21st trigger of stating the first counting unit connects defeated as second reset signal altogether Enter end, the second output terminal of the 21st trigger is as the first trigger signal output end.

Optionally, first counting unit includes：First trigger, the second trigger, third trigger and the 4th Trigger；

Second input terminal of second input terminal of first trigger as first counting unit, first touching Send out first input end of the first input end as first counting unit of device, the first output end of first trigger with Second input terminal of second trigger connects, and the of the second output terminal of first trigger and second trigger The connection of one input terminal, the first output end of second trigger is connect with the second input terminal of the third trigger, described The second output terminal of second trigger is connect with the first input end of the third trigger, and the first of the third trigger is defeated Outlet is connect with the second input terminal of the 4th trigger, the second output terminal of the third trigger and the 4th triggering The first input end of device connects, first output of the first output end of the 4th trigger as first counting unit End, second output terminal of the second output terminal of the 4th trigger as first counting unit, first trigger Reset terminal, second trigger reset terminal, the reset terminal of the third trigger and answering for the 4th trigger Position end connects the reset terminal as first counting unit altogether.

Optionally, the internal frequency signal detection module includes that internal frequency signal input part, the first reset signal are defeated Enter end, the first oscillator signal output end, the second oscillator signal output end and the second trigger signal output end；

The internal frequency signal input part is connect with the internal frequency signal source, the first reset signal input terminal It is connect with the first reset signal output end of the External frequency signals detection module；

The internal frequency signal detection module further includes：Third reverser, the 4th phase inverter, the second counting unit and 22nd trigger；

The input terminal of the third phase inverter is connect with the internal frequency signal input part, the third phase inverter it is defeated Second input terminal of outlet, the input terminal of the 4th phase inverter and second counting unit is connect altogether as the internal frequency First oscillator signal output end of rate signal detection module, the output end of the 4th phase inverter and second counting unit First input end connect the second oscillator signal output end as the internal frequency signal detection module altogether, second meter First output end of counting unit is connect with the second input terminal of the 22nd trigger, and the second of second counting unit Output end is connect with the first input end of the 22nd trigger, the reset terminal of second counting unit and described second The reset terminal of 12 triggers is connect altogether as the first reset signal input terminal, the second output of the 22nd trigger End is hanging, and the first output end of the 22nd trigger is as the second trigger signal output end.

Optionally, second counting unit includes：5th trigger, the 6th trigger and the 7th trigger；

Second input terminal of the first input end of 5th trigger as second counting unit, the 5th touching Send out second input terminal of second input terminal as second counting unit of device, the first input end of the 6th trigger with The second output terminal of 5th trigger connects, and the of the second input terminal of the 6th trigger and the 5th trigger The connection of one output end, the first input end of the 7th trigger is connect with the second output terminal of the 6th trigger, described Second input terminal of the 7th trigger is connect with the first output end of the 6th trigger, and the first of the 7th trigger is defeated First output end of the outlet as second counting unit, the second output terminal of the 7th trigger is as second meter The second output terminal of counting unit.

Optionally, the reset signal processing module is defeated including the first oscillator signal input terminal, the second oscillator signal It is defeated to enter end, first frequency signal input part, first selection signal input terminal, the first reset signal input terminal, power-on reset signal Enter end and period 1 reset signal output end；

The reset signal processing module further includes：8th trigger, the 23rd trigger, the 5th phase inverter, the 6th Phase inverter, the 24th trigger, the first nor gate, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter and first choice Device；

The first input end of 8th trigger is as the first oscillator signal input terminal, the 8th trigger The second input terminal as the second oscillator signal input terminal, the first output end of the 8th trigger, described second Second input terminal of the second input terminal of 13 triggers and the 24th trigger connects altogether, the 8th trigger The first input end of second output terminal, the first input end of the 23rd trigger and the 24th trigger is total It connects, the first output end of the 23rd trigger is connect with the input terminal of the 5th phase inverter, the hex inverter Input terminal connect with the output end of the 5th phase inverter, the output end of the hex inverter and it is described 24th triggering The third input terminal of device connects, the first output end of the 24th trigger and the first input end of first nor gate First signal input part of connection, the first selector is inputted as the first frequency signal of the reset signal processing module The second signal input terminal at end, the first selector is inputted as the first reset signal of the reset signal processing module The signal behavior input terminal at end, the first selector is inputted as the first selection signal of the reset signal processing module End, the output end of the first selector are connect with the reset terminal of the 23rd trigger, the 24th trigger Reset terminal, the second input terminal of first nor gate and the reset terminal of the 8th trigger connect altogether as the reset The power-on reset signal input terminal of signal processing module, the input of the output end of first nor gate and the 7th phase inverter End connection, the output end of the 7th phase inverter connect with the input terminal of the 8th phase inverter, the 8th phase inverter it is defeated Outlet is connect with the input terminal of the 9th phase inverter, and the output end of the 9th phase inverter is resetted as the period 1 to be believed Number output end.

Optionally, the signal behavior processing module include power-on reset signal input terminal, the first trigger signal input terminal, Second trigger signal input terminal, External frequency signals input terminal, internal frequency signal input part, the second reset signal output end, First frequency signal output end, second frequency signal output end and third frequency signal output end；

The signal behavior processing module further includes：Tenth phase inverter, the second nor gate, third nor gate, the 11st are instead Phase device, the 12nd phase inverter, the first NAND gate, the 13rd phase inverter, the 14th phase inverter, four nor gate, second selector, 15th phase inverter, the tenth hex inverter, the 17th reverser, third selector, the second NAND gate, eighteen incompatibilities phase device, 19 phase inverters, the 20th phase inverter, the 21st phase inverter, the 22nd phase inverter, the 23rd phase inverter, the 9th triggering Device, the tenth trigger, the 11st trigger, the 24th phase inverter and the 25th phase inverter；

The input terminal of tenth phase inverter is as the first trigger signal input terminal, the output of the tenth phase inverter End is connect with the first input end of second nor gate, and the of the output end of second nor gate and the third nor gate The connection of one input terminal, the second input terminal of the third nor gate as the second trigger signal input terminal, the third or The third input terminal of NOT gate is connect with the power-on reset signal input terminal, the second input terminal of second nor gate, described The signal behavior input terminal of the input terminal of 11st phase inverter, the output end of the third nor gate and the second selector It connects altogether, the of the output end of the 11st phase inverter, the input terminal of the 12nd phase inverter and first NAND gate Two input terminals connect altogether, and the output end of the NAND gate is connect with the input terminal of the 13rd phase inverter, the 13rd reverse phase The output end of device is connect with the second input terminal of the four nor gate, the first input end and the letter of the four nor gate The power-on reset signal input terminal connection of number selection processing module, the output end of the four nor gate and the 14th reverse phase The input terminal of device connects, second reset signal of the output end of the 14th phase inverter as the signal behavior processing module The output end of output end, the 12nd phase inverter is connect with the signal behavior input terminal of the third selector, and described second Internal frequency signal input part of first signal input part of selector as the signal behavior processing module, second choosing The second signal input terminal for selecting device is connect with the output end of the tenth hex inverter, the input terminal of the tenth hex inverter with The output end of 15th phase inverter connects, and the input terminal of the 15th phase inverter is as the signal behavior processing module External frequency signals input terminal, the output end of the second selector connect with the input terminal of the eighteen incompatibilities phase device, institute State the output end of eighteen incompatibilities phase device, the first input end of second NAND gate, the 19th phase inverter input terminal with And the second input terminal of the 9th trigger connects altogether, the of the output end of the 19th phase inverter and the 9th trigger The connection of one input terminal, the first output end of the 9th trigger is connect with the second input terminal of the tenth trigger, described The second output terminal of 9th trigger is connect with the first input end of the tenth trigger, and the first of the tenth trigger is defeated Outlet is connect with the second input terminal of the 11st trigger, the second output terminal and the described 11st of the tenth trigger The first input end of trigger connects, and the output end of the 11st trigger and the input terminal of the 24th phase inverter connect It connects, the input terminal of the 25th phase inverter is connect with the output end of the 24th phase inverter, and the described 25th is anti- The output end of phase device is connect with the first input end of first NAND gate, the reset terminal of the 9th trigger, the described tenth The reset terminal of the reset terminal of trigger and the 11st trigger connects altogether, the input terminal of the 17th phase inverter and reset The output end of signal processing module connection, the first signal input part of the third selector and the 17th phase inverter connects It connects, the signal behavior input terminal of the third selector is connect with the output end of the 12nd phase inverter, the third selection The second signal input terminal of device is connect with the first power supply, the output end of the third selector and second NAND gate The connection of second input terminal, the output end of second NAND gate are connect with the input terminal of the 19th phase inverter, and the described tenth The input terminal of the output end of nine phase inverters and the 20th phase inverter connects first as the signal behavior processing module altogether Frequency signal output end, the output end of the 20th phase inverter and the input terminal of the 21st phase inverter are connect altogether as institute State the second frequency signal output end of signal behavior processing module, the output end and the described 20th of the 21st phase inverter The input terminal of two phase inverters connects, and the output end of the 22nd reverser and the input terminal of the 23rd phase inverter connect It connects, third frequency signal output end of the output end of the 23rd phase inverter as the signal behavior processing module.

The utility model also proposed a kind of shared oscillator rate-adaptive pacemaker system, and the system comprises the first chips and more It include shared oscillator frequency as described in any one of the above embodiments inside a synchronizing chip, the first chip and multiple synchronizing chips Rate output circuit；

The External frequency signals input terminal of the external input signal detection module of first chip and the foreign frequency Signal source connection, the internal frequency signal input part of the internal frequency signal detection module of first chip and first core The internal oscillator signal source of piece connects；

The External frequency signals input terminal of the external input signal detection module of multiple synchronizing chips and described first The third frequency signal output end of the signal behavior processing module of chip connects, the internal frequency signal of multiple synchronizing chips The internal frequency signal input part of detection module is corresponded with the internal oscillator signal source of multiple synchronizing chips respectively Connection.

Optionally, the external frequency that the period 1 reset signal of the first chip output passes through multiple synchronizing chips Rate signal input part is output to multiple synchronizing chips, and multiple synchronizing chips pass through defeated to external frequency signal input end The pulse pair period 1 reset signal and third frequency signal of the signal entered are identified.

Optionally, the period 1 reset signal is used to carry out first chip and multiple synchronizing chips It resets.

It includes External frequency signals detection module, internal frequency signal detection module, reset signal that the utility model, which uses, The shared oscillator frequency output circuitry of processing module and signal behavior processing module, the shared oscillator frequency output circuitry Applied to the shared oscillator rate-adaptive pacemaker system including the first chip and multiple synchronizing chips, pass through reset signal processing module The period 1 reset signal of output is resetted to entire shared oscillator frequency output circuitry and chip, wherein first Chip export third frequency signal as multiple synchronizing chips of rear end External frequency signals input, allow chip outside Continuously switch between portion's frequency signal source and internal frequency signal source, it is defeated using shared oscillator frequency to realize multiple chips Out, solve by peripheral control unit issue different coding signal when, the clock signal of decoding circuit with encoded signal stringent Reaching synchronous with can be only achieved chip, needing at this time while input control signal and clock signal, it will so that chip interior is electric Road becomes the problem of complexity causes chip cost to increase.

Detailed description of the invention

Fig. 1 is a kind of function structure chart of shared oscillator frequency output circuitry provided by the embodiment of the utility model；

Fig. 2 is the exemplary circuit structure chart of External frequency signals detection module provided by the embodiment of the utility model；

Fig. 3 is the exemplary circuit structure chart of internal frequency signal detection module provided by the embodiment of the utility model；

Fig. 4 is the exemplary circuit structure chart of reset signal processing module provided by the embodiment of the utility model；

Fig. 5 is the exemplary circuit structure chart of reset signal processing module provided by the embodiment of the utility model；

Fig. 6 is the structural schematic diagram of the Z trigger in the utility model embodiment；

Fig. 7 is the structural schematic diagram of the d type flip flop in the utility model embodiment；

Fig. 8 is the structural schematic diagram of the signal selector in the utility model embodiment；

Fig. 9 is the structural schematic diagram of one of the utility model embodiment shared oscillator rate-adaptive pacemaker system.

Specific embodiment

In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain The utility model is not used to limit the utility model.

In the description of the present invention, it should be understood that term " first ", " second " are used for description purposes only, and It cannot be understood as indicating or implying relative importance or implicitly indicate the quantity of indicated technical characteristic.It defines as a result, The feature of " first ", " second " can explicitly or implicitly include one or more of the features.

Fig. 1 is a kind of function structure chart of shared oscillator frequency output circuitry provided by the embodiment of the utility model, such as Shown in Fig. 1, shared oscillator frequency output circuitry provided by the embodiment of the utility model respectively with External frequency signals source 11 with And internal frequency signal source 21 connects, the shared oscillator frequency output circuitry in the present embodiment includes：With External frequency signals Source 11 connects, and the External frequency signals for exporting to external frequency signal source 11 detect, and exports the first trigger signal And first reset signal External frequency signals detection module 10；It is examined with internal frequency signal source 21 and External frequency signals It surveys module 10 to connect, the internal frequency signal for exporting internal frequency signal source 21 detects, and exports the first oscillation The internal frequency signal detection module 20 of device signal, the second oscillator signal and the second trigger signal；With External frequency signals Detection module 10 and internal frequency signal detection module 20 connect, for being believed according to the first oscillator signal, the second oscillator Number and the first reset signal output period 1 reset signal reset signal processing module 30；With External frequency signals source 11, External frequency signals detection module 10, internal frequency signal source 21, internal frequency signal detection module 20 and reset signal Processing module 30 connects, for according to the first trigger signal, the second trigger signal, internal frequency signal and External frequency signals Export the signal behavior processing module of first frequency signal, second frequency signal, third frequency signal and the second reset signal 40。

In the present embodiment, when External frequency signals source 11 continuously inputs 32 pulse signals in the first preset time, The signal source of shared oscillator frequency output circuitry switches to internal frequency signal source 21, which can be The internal oscillator of IC chip, while External frequency signals detection module is resetted in the second preset time, Prevent external signal interference from causing the accumulation of pulse signal and chip is made to automatically switch to External frequency signals source 11.In addition, multiple Position signal processing module is also used to reset entire shared oscillator frequency output circuitry and chip, External frequency signals Detection module and internal frequency signal detection module are according to detecting External frequency signals and internal frequency signal As a result export the first trigger signal and the second trigger signal respectively, signal behavior processing module according to first trigger signal, Second trigger signal exports third frequency signal, allows chip in external frequency signal source and internal frequency signal Continuously switch between source, realizes shared oscillator rate-adaptive pacemaker.

Fig. 2 is the exemplary circuit structure chart of External frequency signals detection module provided by the embodiment of the utility model, such as Fig. 2 Shown, External frequency signals detection module 10 includes External frequency signals input terminal IN, the second reset signal input terminal tt10, the One trigger signal output end O10 and the first reset signal output end TT10, wherein External frequency signals input terminal IN and outside Frequency signal source 11 connects, and External frequency signals detection module 10 further includes：First switch tube M1, the first phase inverter V1, second Phase inverter V2, the first counting unit 101 and the 21st trigger Z21.Specifically, the current input terminal of first switch tube M1 It is connect with the first power supply VDD, the input terminal of the current output terminal of first switch tube M1 and the first phase inverter V1 connect work altogether For the External frequency signals input terminal IN of External frequency signals detection module 10, the output end of the first phase inverter V1, the second reverse phase The input terminal of device V2 and the second input terminal of the first counting unit 101 are connect altogether as the first reset signal output end TT10, the The output end of two phase inverter V2 is connect with the first input end of the first counting unit 101, the first output of the first counting unit 101 End is connect with the second input terminal CKB of the 21st trigger Z21, the second output terminal and the 20th of the first counting unit 101 The first input end CK connection of one trigger Z21, the first reset terminal of counting unit 101 and answering for the 21st trigger Z21 Position end R meets the second output terminal QB as the second reset signal input terminal tt10, the 21st trigger Z21 as the first touching altogether The first output end Q of signalling output end O10, the 21st trigger Z21 are hanging.

In the present embodiment, the External frequency signals input terminal IN of External frequency signals detection module 10 is connected to first switch Pipe M1, first switch tube M1 are as a pull-up resistor, specifically, first switch tube M1 can be PMOS tube, wherein The source electrode of PMOS tube is the current input terminal of first switch tube M1, and the grid of PMOS tube is the control terminal of first switch tube M1, The drain electrode of PMOS tube is the current output terminal of first switch tube M1.When external frequency signal source 11 does not input, foreign frequency The External frequency signals input terminal IN of signal detection module 10 be high level, External frequency signals after two phase inverters with The connection of first counting unit 101, the first counting unit 101 are used to calculate the umber of pulse of External frequency signals, only in external frequency When rate signal continuously inputs the pulse of the first predetermined number in the first preset time, the second of the 21st trigger Z21 is defeated Outlet QB will become low level signal from high level signal, specifically, the 21st trigger Z21 is d type flip flop.

When the second output terminal QB of the 21st trigger Z21 will become low level from high level, the second reset signal Become low level signal, if the frequency signal source of shared oscillator frequency output circuitry is internal frequency signal, second resets The signal period of signal has to be larger than 64 times of the period of External frequency signals, so that External frequency signals are in the first preset time The pulse of the first predetermined number of interior continuous input, if External frequency signals are pre- without continuously input first in the first preset time If the pulse of number, then the second reset signal resets the first counting unit 101 and the 21st trigger Z21, prevents Only the accumulation of External frequency signals pulse and cause chip to stop working.

Fig. 2 is referred to, as an embodiment of the present invention, in the present embodiment, the first counting unit 101 includes：The One trigger Z1, the second trigger Z2, third trigger Z3 and the 4th trigger Z4；The second input terminal of first trigger Z1 Second input terminal of the CKB as the first counting unit 101, the first input end Q of the first trigger Z1 is as the first counting unit Second input terminal CKB of 101 first input end, the first output end Q and the second trigger Z2 of the first trigger Z1 is connect, the The second output terminal QB of one trigger Z1 is connect with the first input end CK of the second trigger Z2, and the first of the second trigger Z2 is defeated Outlet Q is connect with the second input terminal CKB of third trigger Z3, the second output terminal QB and third trigger of the second trigger Z2 Second input terminal CKB of the first input end CK connection of Z3, the first output end Q and the 4th trigger Z4 of third trigger Z3 connects It connects, the second output terminal QB of third trigger Z3 is connect with the first input end CK of the 4th trigger Z4, the 4th trigger Z4's First output end of the first output end Q as the first counting unit 101, the second output terminal QB of the 4th trigger Z4 is as first The second output terminal of counting unit 101, the reset terminal R of the first trigger of Z1, the reset terminal R of the second trigger Z2, third triggering The reset terminal R of the reset terminal R and the 4th trigger Z4 of device Z3 connect the reset terminal as the first counting unit 101 altogether.

In the present embodiment, the first counting unit 101 is cascaded by four triggers, wherein the first trigger Z1, Second trigger Z2, third trigger Z3 and the 4th trigger Z4 are T trigger, four T triggers and a d type flip flop Series connection calculates the pulse of External frequency signals, so that External frequency signals are continuous only in the first preset time When inputting 32 pulses, the second output terminal QB of the 21st trigger Z21 will be become low level from high level, at this point, external First trigger signal of the output of frequency signal detection module 10 is low level signal.

As an embodiment of the present invention, Fig. 3 is internal frequency signal detection mould provided by the embodiment of the utility model The exemplary circuit structure chart of block, as shown in figure 3, internal frequency signal detection module 20 include internal frequency signal input part IN2, First reset signal input terminal TT20, the first oscillator signal output end O201, the second oscillator signal output end O202 and Second trigger signal output end O20；Internal frequency signal input part IN2 is connect with internal frequency signal source 21, and first resets letter Number input terminal TT20 is connect with the first reset signal output end TT10 of External frequency signals detection module 10；In the present embodiment In, internal frequency signal detection module 20 further includes：Third reverser V3, the 4th phase inverter V4, the second counting unit 201 and 22nd trigger Z22；Specifically, the input terminal of third phase inverter V3 is connect with internal frequency signal input part IN2, third Second input terminal of the output end of phase inverter V3, the input terminal of the 4th phase inverter V4 and the second counting unit 201 connects conduct altogether First oscillator signal output end O201 of internal frequency signal detection module 20, the output end of the 4th phase inverter V4 and the second meter The first input end of counting unit 201 connects the second oscillator signal output end as internal frequency signal detection module 20 altogether O202, the first output end of the second counting unit 201 are connect with the second input terminal CKB of the 22nd trigger Z22, the second meter The second output terminal of counting unit 201 is connect with the first input end CK of the 22nd trigger Z22, the second counting unit 201 The reset terminal R of reset terminal and the 22nd trigger Z22 are connect altogether as the first reset signal input terminal TT0, the 22nd triggering The first output end Q of the second output terminal of device Z22 hanging QB, the 22nd trigger Z22 are as the second trigger signal output end O20。

In the present embodiment, the inside frequency that internal frequency signal detection module 20 is used to export internal frequency signal source 21 Rate signal is detected, which is the frequency signal that the internal oscillator of chip generates, and internal frequency signal exists It is exported after the second counting unit 201 after two phase inverters, the second counting unit is used for the arteries and veins to internal frequency signal It rushes number to be counted, only when internal frequency signal inputs the pulse of the second predetermined number, the 22nd trigger Z22 is defeated The second trigger signal out becomes high level signal from low level signal, wherein and the 22nd trigger Z22 is d type flip flop, when When External frequency signals have input, the first reset signal answers the second counting unit 201 and the 22nd trigger Z22 Position, restarts the counting of the second counting unit 201, stops inputting in External frequency signals, and the second counting unit 201 is counted When number meets the pulse of the second predetermined number, the frequency signal source of chip switches to internal frequency signal source 21, i.e., using inside Oscillator frequency signal input, realizes internal oscillator frequency signal and the effect that External frequency signals source is automatically switched.

Referring to Fig. 3, as an embodiment of the present invention, the second counting unit 201 in the utility model embodiment is wrapped It includes：5th trigger Z5, the 6th trigger Z6 and the 7th trigger Z7.Specifically, the first input end of the 5th trigger Z5 Second input terminal of the CK as the second counting unit 201, the second input terminal CKB of the 5th trigger Z5 is as the second counting unit 201 the second input terminal, the first input end CK of the 6th trigger Z6 are connect with the second output terminal QB of the 5th trigger Z5, the The second input terminal CKB of six trigger Z6 is connect with the first output end Q of the 5th trigger Z5, and the first of the 7th trigger Z7 is defeated Enter to hold CK and the second output terminal QB of the 6th trigger Z6 to connect, the triggering of the second input terminal CKB of the 7th trigger Z7 and the 6th The first output end Q connection of device Z6, first output of the first output end Q of the 7th trigger Z7 as the second counting unit 201 End, second output terminal of the second output terminal QB of the 7th trigger Z7 as the second counting unit 201.

In the present embodiment, the 5th trigger Z5, the 6th trigger Z6 and the 7th trigger Z7 are T trigger, the It is connected in series in two counting units 201 by three T triggers, at this point, when internal frequency signal inputs 8 pulses, the 20th Second trigger signal of two trigger Z22 output becomes high level signal from low level signal, stops in External frequency signals defeated Enter, and when the second counting unit 201 is counted as 8, the frequency signal source of chip switches to internal frequency signal source 21, that is, uses The input of internal oscillator frequency signal, realizes internal oscillator frequency signal and the effect that External frequency signals source is automatically switched.

As an embodiment of the present invention, Fig. 4 is reset signal processing module provided by the embodiment of the utility model Exemplary circuit structure chart, reset signal processing module 30 include the first oscillator signal input terminal IN301, the second oscillator signal Input terminal IN302, first frequency signal input part A2Y, first selection signal input terminal POE3, the first reset signal input terminal TT30, power-on reset signal input terminal POR and period 1 reset signal output terminals A 10.Wherein, reset signal processing module 30 further include：8th trigger Z8, the 23rd trigger Z23, the 5th phase inverter V5, hex inverter V6, the 24th touching Send out device Z24, the first nor gate NOR1, the 7th phase inverter V7, the 8th phase inverter V8, the 9th phase inverter V9 and first selector ZMUX1。

Specifically, the first input end CK of the 8th trigger Z8 is as the first oscillator signal input terminal IN301, the 8th touching Send out device Z8 the second input terminal CKB as the second oscillator signal input terminal IN302, the 8th trigger Z8 the first output end Q, The second input terminal CKB of the second input terminal CKB and the 24th trigger Z24 of 23rd trigger Z23 connect altogether, and the 8th The second output terminal QB of trigger Z8, the first input end CK and the 24th trigger Z24 of the 23rd trigger Z23 First input end CK connects altogether, and the first output end Q of the 23rd trigger Z23 is connect with the input terminal of the 5th phase inverter V5, the The input terminal of hex inverter V6 is connect with the output end of the 5th phase inverter V5, the output end of hex inverter V6 and the 24th touching The third input terminal D connection of hair device Z24, the first of the first output end Q and the first nor gate NOR1 of the 24th trigger Z24 Input terminal connection, first frequency of the first signal input part I0 of first selector ZMUX1 as reset signal processing module 30 The second signal input terminal I1 of signal input part A2Y, first selector ZMUX1 are answered as the first of reset signal processing module 30 Position signal input part TT30, first choice of the signal behavior input terminal S of first selector as reset signal processing module 30 The output end O of signal input part POE3, first selector ZMUX1 are connect with the reset terminal R of the 23rd trigger Z23, and second The reset terminal of the reset terminal R of 14 trigger Z24, the second input terminal of the first nor gate NOR1 and the 8th trigger Z8 are total Connect, and the power-on reset signal input terminal POR as reset signal processing module 30 is connect with power-on reset signal source, first or The output end of NOT gate NOR1 is connect with the input terminal of the 7th phase inverter V7, the output end and the 8th phase inverter V8 of the 7th phase inverter V7 Input terminal connection, the output end of the 8th phase inverter V8 connect with the input terminal of the 9th phase inverter V9, and the 9th phase inverter V9's is defeated Outlet is as period 1 reset signal output terminals A 10.

In the present embodiment, the first oscillator signal and the second oscillator signal pass sequentially through the 8th trigger Z8 and Nine trigger Z9 input, doubles the pulse period of output, when shared oscillator frequency output circuitry is internal oscillator When signal inputs, first selection signal is low level, and first selector ZMUX1 output is first frequency signal, is vibrated when sharing When device frequency output circuitry is that External frequency signals input, first selection signal is high level, and first selector ZMUX1 output is First reset signal.In the present embodiment, the 8th trigger Z8 is T trigger, the 23rd trigger Z23 and the 24th Trigger Z24 is d type flip flop, and the output end O of first selector ZMUX1 is connect with the reset terminal R of the 23rd trigger Z23, 23rd trigger Z23 is used for detection cycle signal, and wherein the high level signal of periodic signal is internal oscillator signal Four times of pulse, if the signal of first selector ZMUX1 output is lasting low level signal, the 23rd trigger The first output end Q of Z23 has signal output, if the signal of first selector ZMUX1 output is not lasting low level signal, Then the first output end Q of the 23rd trigger Z23 is exported by clutter, at this point, the first output end of the 23rd trigger Z23 Q is connect by two continuous phase inverters with the third input terminal D of the two or four trigger Z24, and the two or four trigger Z24 was used for Filter clutter stablizes output waveform, and the period 1 reset signal of final output resets entire chip.

As an embodiment of the present invention, Fig. 5 is reset signal processing module provided by the embodiment of the utility model Exemplary circuit structure chart, signal behavior processing module 40 include power-on reset signal input terminal POR, the first trigger signal input terminal IN310, the second trigger signal input terminal IN320, External frequency signals input terminal IN, internal frequency signal input part IN2, second Reset signal output end tt40, first frequency signal output end A2Y, second frequency signal output end A2 and third frequency signal Output end OUT.

In the present embodiment, signal behavior processing module 40 further includes：Tenth phase inverter V10, the second nor gate NOR2, Three nor gate NOR3, the 11st phase inverter V11, the 12nd phase inverter V12, the first NAND gate NAND1, the 13rd phase inverter V13, 14th phase inverter V14, four nor gate NOR4, second selector ZMUX2, the 15th phase inverter V15, the tenth hex inverter V16, the 17th reverser V17, third selector ZMUX3, the second NAND gate NAND2, eighteen incompatibilities phase device V18, the 19th are instead Phase device V19, the 20th phase inverter V20, the 21st phase inverter V21, the 22nd phase inverter V22, the 23rd phase inverter V23, the 9th trigger Z9, the tenth trigger Z10, the 11st trigger Z11, the 24th phase inverter V24 and the 25th Phase inverter V25.Specifically, the input terminal of the tenth phase inverter V10 is as the first trigger signal input terminal IN310, the tenth phase inverter The output end of V10 is connect with the first input end of the second nor gate NOR2, the output end of the second nor gate NOR2 and third or non- The first input end connection of door NOR3, the second input terminal of third nor gate NOR3 as the second trigger signal input terminal IN320, The third input terminal of third nor gate NOR320 is connect with power-on reset signal input terminal POR, and the second of the second nor gate NOR2 The signal choosing of input terminal, the input terminal of the 11st phase inverter, the output end of third nor gate NOR3 and second selector ZMUX2 It selects input terminal S to connect altogether, the output end of the 11st phase inverter, the input terminal of the 12nd phase inverter and the first NAND gate NAND1 Second input terminal connects altogether, and the output end of the first NAND gate NAND1 is connect with the input terminal of the 13rd phase inverter V13, and the 13rd is anti- The output end of phase device V13 is connect with the second input terminal of four nor gate NOR4, the first input end of four nor gate NOR4 with The power-on reset signal input terminal POR connection of signal behavior processing module 40, the output end of four nor gate NOR4 and the 14th The input terminal of phase inverter V14 connects, and the output end of the 14th phase inverter V14 is resetted as the second of signal behavior processing module 40 The output end of signal output end tt40, the 12nd phase inverter V12 are connect with the signal behavior input terminal S of third selector ZMUX3, Internal frequency signal input part of the first signal input part I0 of second selector ZMUX2 as signal behavior processing module 40 The second signal input terminal I1 of IN2, second selector ZMUX2 are connect with the output end of the tenth hex inverter V16, the 16th reverse phase The input terminal of device V16 is connect with the output end of the 15th phase inverter V15, and the input terminal of the 15th phase inverter V15 is selected as signal The output end of External frequency signals the input terminal IN, second selector ZMUX2 of processing module 40 are selected with eighteen incompatibilities phase device V18's Input terminal connection, first input end, the 19th phase inverter of the output end of eighteen incompatibilities phase device V18, the second NAND gate NAND2 The second input terminal CKB of the input terminal of V19 and the 9th trigger Z9 connect altogether, the output end and the 9th of the 19th phase inverter V19 The first input end CK connection of trigger Z9, the second input of the first output end Q and the tenth trigger Z10 of the 9th trigger Z9 CKB connection is held, the second output terminal QB of the 9th trigger Z9 is connect with the first input end CK of the tenth trigger Z10, the tenth touching The first output end Q of hair device Z10 is connect with the second input terminal CK of the 11st trigger Z11, and the second of the tenth trigger Z10 is defeated Outlet QB is connect with the first input end CK of the 11st trigger Z11, and the output end of the 11st trigger Z11 and the 24th is instead The input terminal of phase device V24 connects, and the input terminal of the 25th phase inverter V25 is connect with the output end of the 24th phase inverter V24, The output end of 25th phase inverter V25 is connect with the first input end of the first NAND gate NAND1, the reset of the 9th trigger Z9 The reset terminal R of the reset terminal R and the 11st trigger Z11 of end R, the tenth trigger Z10 connect altogether, third selector ZMUX3's First signal input part is connect with the output end of the 17th phase inverter V17, the signal behavior input terminal S of third selector ZMUX3 It is connect with the output end of the 12nd phase inverter V12, the second signal input terminal I1 and the first power supply of third selector ZMUX3 VDD connection, the output end O of third selector ZMUX3 are connect with the second input terminal of the second NAND gate NAND2, the second NAND gate The output end of NAND2 is connect with the input terminal of the 19th phase inverter V19, and the output end of the 19th phase inverter V19 and the 20th is instead The input terminal of phase device V20 connects the first frequency signal output end A2Y as signal behavior processing module 40, the 20th phase inverter altogether The input terminal of the output end of V20 and the 21st phase inverter V21 connect the second frequency letter as signal behavior processing module 40 altogether The output end of number the 2, the 21st phase inverter V21 of output terminals A is connect with the input terminal of the 22nd phase inverter V22, and the 22nd The output end of reverser V22 is connect with the input terminal of the 23rd phase inverter V23, and the output end of the 23rd phase inverter V23 is made For the third frequency signal output end OUT of signal behavior processing module 40.

As an embodiment of the present invention, the 9th trigger Z9, the tenth trigger Z10 and the 11st trigger Z11 For T trigger.

In the present embodiment, when the frequency signal input of shared oscillator frequency output circuitry is internal frequency signal source When, the 11st phase inverter V11 exports high level signal, when the frequency signal input of shared oscillator frequency output circuitry is outside When frequency signal source, the 11st phase inverter V11 exports low level signal, wherein the first choice of the 12nd phase inverter V12 output Signal is used to select the output of the every work a cycle reset signal of the first chip, wherein the input terminal of the 17th phase inverter inputs Signal be the every work a cycle of the first chip to the reset signal of entire circuit, when first selection signal is low level signal When, third selector ZMUX3 output is reset signal of the every work a cycle of the first chip to entire circuit, first choice letter Number be high level signal when, third selector ZMUX3 output be power supply VDD output signal, and with second selection The internal frequency signal or External frequency signals of device ZMUX output carry out NAND gate combination, and every work a cycle is made to reset letter It number is transferred to the External frequency signals input terminal of the second synchronizing chip, the cycle reset signal that only the first chip generates can transmit It is resetted to multiple second synchronizing chips, when External frequency signals input, first selection signal is high level signal, third What selector ZMUX was exported is the signal of power supply VDD output, at this point, the reset cycle of each chip is identical, all cores It is synchronous that piece realizes that shared oscillator frequency achievees the effect that.

The signal of first NAND gate NAND1 first input end input is that the second frequency signal of the 20th phase inverter output mentions The signal of chip interior signal work is supplied, the signal period must be greater than 64 times of the period of External frequency signals, when interior When portion's frequency signal inputs, the signal of the 11st phase inverter V11 output is high level signal, when External frequency signals input, The signal of 11st phase inverter V11 output is low level signal.When the input of internal frequency signal, the period of the second reset signal Greater than 64 times of the period of External frequency signals, when External frequency signals input, the low level of the second reset signal output.

In the present embodiment, the signal of eighteen incompatibilities phase device V18 output final output control week after three T triggers The reset terminal of the pulse width of phase reset signal, the 9th trigger Z9, the tenth trigger Z10 and the 11st trigger Z11 are total Cycle reset single short pulse signal is received, the 9th trigger Z9, the tenth trigger Z10 and the 11st trigger Z11 are made The counting unit of composition counts again.As an embodiment of the present invention, Fig. 6 is the Z triggering in the utility model embodiment The structural schematic diagram of device, as shown in fig. 6, the end CK of Z trigger is first input end, the end CKB is the second input terminal, input Signal is on the contrary, the end R of Z trigger is reset terminal, when the reset signal of the end R input is low level signal, the normal work of Z trigger Make, when the reset signal of the end R input is high level, Z trigger will not work, and the recovery of Z trigger is made to power on rigid beginning state；Z The the first output end Q and second output terminal QB of trigger are that the level signal of output is opposite, wherein second output terminal QB output Signal frequency is 1/2 times (period twice) of the signal frequency of the first output end Q output.

As an embodiment of the present invention, Fig. 7 is the structural schematic diagram of the d type flip flop in the utility model embodiment, As shown in fig. 7, the end r of d type flip flop is reset terminal, when the input of the end r is low level signal, d type flip flop is worked normally, the input of the end r When for for high level, d type flip flop will not work, and d type flip flop recovery is made to power on rigid beginning state；The end CK of d type flip flop is first Input terminal, the end CKB be the second input terminal, input signal on the contrary, d type flip flop the first output end Q and second output terminal QB Be output level signal it is opposite, wherein when the end r input signal be low level signal when, the first output end Q output level Signal will become low level signal from high level signal, and when the signal of the end r input is high level signal, the first output end Q is defeated Level signal out is high level signal, after second output terminal QB restarts timing a cycle, the first output end Q output Level signal becomes low level signal again.

As an embodiment of the present invention, Fig. 8 is the structural representation of the signal selector in the utility model embodiment Figure, as shown in figure 8, in the present embodiment, when the end S of signal selector is high level signal, output end O output is input The signal for holding I1 input, when the end S is low level signal, what output end O was exported is the signal of input terminal I0 input.

As an embodiment of the present invention, Fig. 9 is that one of the utility model embodiment shared oscillator frequency is defeated Propose shared oscillator rate-adaptive pacemaker system in structural schematic diagram the present embodiment of system out, the system include the first chip with It include the shared oscillator rate-adaptive pacemaker such as any of the above-described inside multiple synchronizing chips, the first chip and multiple synchronizing chips Circuit；The External frequency signals input terminal of the external input signal detection module of first chip is connect with External frequency signals source, The internal frequency signal input part of the internal frequency signal detection module of first chip and the internal oscillator signal of the first chip Source connection；The External frequency signals input terminal of the external input signal detection module of multiple chips and the signal behavior of the first chip The third frequency signal output end of processing module connects, the internal frequency signal of the internal frequency signal detection module of multiple chips Input terminal connects one to one with the internal oscillator signal source of multiple chips respectively.

As an embodiment of the present invention, the period 1 reset signal of the first chip output passes through multiple synchronizing chips External frequency signals input terminal be output to multiple synchronizing chips, multiple synchronizing chips are by inputting External frequency signals The pulse pair period 1 reset signal and third frequency signal for holding the signal of input are identified.

Specifically, the first chip does not have the input of External frequency signals source, the first chip uses internal frequency signal source, that is, adopts The oscillator frequency signal of the first chip interior is used to input as frequency signal, all synchronizing chips in rear end are all made of the first core Oscillator frequency signal inside piece achievees the effect that all chips share internal oscillator.

As an embodiment of the present invention, period 1 reset signal is used for first chip and multiple described Synchronizing chip is resetted.In the present embodiment, when the External frequency signals input terminal of the first chip does not have signal input, first Chip uses internal frequency signal, i.e. the frequency signal of the internal oscillator of the first chip is inputted as frequency signal source, and first The External frequency signals input terminal of the synchronizing chip of the third frequency signal output end and rear end of chip connects, at this point, rear end The External frequency signals input terminal of multiple synchronizing chips of the third frequency signal output end and rear end again of synchronizing chip successively connects It connects, all synchronizing chips is made all to use the frequency signal of the internal oscillator of the first chip and realize synchronous effect.

As an embodiment of the present invention, when External frequency signals source stops output, the first chip uses internal frequency Signal source is exported as third frequency signal.

As an embodiment of the present invention, External frequency signals source continuously exports 32 pulses in the first preset time When signal, the first chip, which is used, to be exported using External frequency signals source as third frequency signal.Specifically, when third is preset It is interior that External frequency signals detection module is resetted, prevent the interference of External frequency signals from causing the accumulation of pulse signal, It inputs the frequency signal of the first chip and automatically switches to internal frequency signal source.

In the present embodiment, corresponding reset signal can be generated in a cycle that the first chip interior completes work, And the reset signal that the first chip generates is output in multiple synchronizing chips by third frequency signal output end, makes to own Chip resetted after a cycle that works once, realize the synchronization of frequency signal.

The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model Protection scope within.

Claims

1. a kind of shared oscillator frequency output circuitry, the shared oscillator frequency output circuitry respectively with External frequency signals Source and the connection of internal frequency signal source, which is characterized in that the shared oscillator frequency output circuitry includes：

It is connect with the External frequency signals source, the External frequency signals for exporting to the External frequency signals source are examined It surveys, and exports the External frequency signals detection module of the first trigger signal and the first reset signal；

It is connect with the internal frequency signal source and the External frequency signals detection module, for believing the internal frequency The internal frequency signal of number source output is detected, and exports the first oscillator signal, the second oscillator signal and the second touching The internal frequency signal detection module of signalling；

It is connect with the External frequency signals detection module and the internal frequency signal detection module, for according to described the The reset of one oscillator signal, second oscillator signal and first reset signal output period 1 reset signal Signal processing module；

With the External frequency signals source, the External frequency signals detection module, the internal frequency signal source, the inside Frequency signal detection module and reset signal processing module connection, for according to first trigger signal, described the Two trigger signals, the internal frequency signal and the External frequency signals output first frequency signal, second frequency signal, The signal behavior processing module of third frequency signal and the second reset signal.

2. shared oscillator frequency output circuitry as described in claim 1, which is characterized in that the External frequency signals detection Module includes External frequency signals input terminal, the second reset signal input terminal, the first trigger signal output end and the first reset Signal output end；

The External frequency signals input terminal is connect with the External frequency signals source, and the External frequency signals detection module is also Including：First switch tube, the first phase inverter, the second phase inverter, the first counting unit and the 21st trigger；

The current input terminal of the first switch tube is connect with the first power supply, the current output terminal of the first switch tube with And the input terminal of first phase inverter connect altogether it is defeated as the External frequency signals of the External frequency signals detection module Enter end, the second of the output end of first phase inverter, the input terminal of second phase inverter and first counting unit Input terminal is connect altogether as the first reset signal output end, the output end of second phase inverter and first counting unit First input end connection, the second input terminal of the first output end of first counting unit and the 21st trigger Connection, the second output terminal of first counting unit connect with the first input end of the 21st trigger, and described the The reset terminal of the reset terminal of one counting unit and the 21st trigger is connect altogether as the second reset signal input terminal, The second output terminal of 21st trigger is as the first trigger signal output end.

3. shared oscillator frequency output circuitry as claimed in claim 2, which is characterized in that the first counting unit packet It includes：First trigger, the second trigger, third trigger and the 4th trigger；

Second input terminal of second input terminal of first trigger as first counting unit, first trigger First input end of the first input end as first counting unit, the first output end of first trigger with it is described Second input terminal of the second trigger connects, and the first of the second output terminal of first trigger and second trigger is defeated Entering end connection, the first output end of second trigger is connect with the second input terminal of the third trigger, and described second The second output terminal of trigger is connect with the first input end of the third trigger, the first output end of the third trigger It is connect with the second input terminal of the 4th trigger, the second output terminal of the third trigger and the 4th trigger First input end connection, first output end of the first output end of the 4th trigger as first counting unit, institute State second output terminal of the second output terminal of the 4th trigger as first counting unit, the reset of first trigger The reset terminal at end, the reset terminal of second trigger, the reset terminal of the third trigger and the 4th trigger is total Connect the reset terminal as first counting unit.

4. shared oscillator frequency output circuitry as described in claim 1, which is characterized in that the internal frequency signal detection Module includes internal frequency signal input part, the first reset signal input terminal, the first oscillator signal output end, the second oscillator Signal output end and the second trigger signal output end；

The internal frequency signal input part is connect with the internal frequency signal source, the first reset signal input terminal and institute State the first reset signal output end connection of External frequency signals detection module；

The internal frequency signal detection module further includes：Third reverser, the 4th phase inverter, the second counting unit and second 12 triggers；

The input terminal of the third phase inverter is connect with the internal frequency signal input part, the output of the third phase inverter Second input terminal at end, the input terminal of the 4th phase inverter and second counting unit is connect altogether as the internal frequency First oscillator signal output end of signal detection module, output end and second counting unit of the 4th phase inverter First input end connects the second oscillator signal output end as the internal frequency signal detection module altogether, and described second counts First output end of unit is connect with the second input terminal of the 22nd trigger, and the second of second counting unit is defeated Outlet is connect with the first input end of the 22nd trigger, the reset terminal of second counting unit and the described 20th The reset terminal of two triggers is connect altogether as the first reset signal input terminal, the second output terminal of the 22nd trigger Vacantly, the first output end of the 22nd trigger is as the second trigger signal output end.

5. shared oscillator frequency output circuitry as claimed in claim 4, which is characterized in that the second counting unit packet It includes：5th trigger, the 6th trigger and the 7th trigger；

Second input terminal of the first input end of 5th trigger as second counting unit, the 5th trigger Second input terminal of second input terminal as second counting unit, the first input end of the 6th trigger with it is described The second output terminal of 5th trigger connects, and the first of the second input terminal of the 6th trigger and the 5th trigger is defeated Outlet connection, the first input end of the 7th trigger are connect with the second output terminal of the 6th trigger, and the described 7th Second input terminal of trigger is connect with the first output end of the 6th trigger, the first output end of the 7th trigger As the first output end of second counting unit, the second output terminal of the 7th trigger counts single as described second The second output terminal of member.

6. shared oscillator frequency output circuitry as described in claim 1, which is characterized in that the reset signal processing module Including the first oscillator signal input terminal, the second oscillator signal input terminal, first frequency signal input part, first selection signal Input terminal, the first reset signal input terminal, power-on reset signal input terminal and period 1 reset signal output end；

The reset signal processing module further includes：8th trigger, the 23rd trigger, the 5th phase inverter, the 6th reverse phase Device, the 24th trigger, the first nor gate, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter and first selector；

The first input end of 8th trigger is as the first oscillator signal input terminal, and the of the 8th trigger Two input terminals are as the second oscillator signal input terminal, the first output end of the 8th trigger, the described 23rd Second input terminal of the second input terminal of trigger and the 24th trigger connects altogether, and the second of the 8th trigger The first input end of output end, the first input end of the 23rd trigger and the 24th trigger connects altogether, First output end of the 23rd trigger is connect with the input terminal of the 5th phase inverter, the hex inverter it is defeated Enter end to connect with the output end of the 5th phase inverter, the output end of the hex inverter and the 24th trigger The connection of third input terminal, the first output end of the 24th trigger and the first input end of first nor gate connect It connects, the first signal input part of the first selector is inputted as the first frequency signal of the reset signal processing module The second signal input terminal at end, the first selector is inputted as the first reset signal of the reset signal processing module The signal behavior input terminal at end, the first selector is inputted as the first selection signal of the reset signal processing module End, the output end of the first selector are connect with the reset terminal of the 23rd trigger, the 24th trigger Reset terminal, the second input terminal of first nor gate and the reset terminal of the 8th trigger connect altogether, described first or The output end of NOT gate is connect with the input terminal of the 7th phase inverter, the output end of the 7th phase inverter and the 8th reverse phase The input terminal of device connects, and the output end of the 8th phase inverter is connect with the input terminal of the 9th phase inverter, and the described 9th is anti- The output end of phase device is as the period 1 reset signal output end.

7. shared oscillator frequency output circuitry as described in claim 1, which is characterized in that the signal behavior processing module Including power-on reset signal input terminal, the first trigger signal input terminal, the second trigger signal input terminal, External frequency signals input End, internal frequency signal input part, the second reset signal output end, first frequency signal output end, the output of second frequency signal End and third frequency signal output end；

The signal behavior processing module further includes：Tenth phase inverter, the second nor gate, third nor gate, the 11st phase inverter, 12nd phase inverter, the first NAND gate, the 13rd phase inverter, the 14th phase inverter, four nor gate, second selector, the tenth Five phase inverters, the tenth hex inverter, the 17th reverser, third selector, the second NAND gate, eighteen incompatibilities phase device, the 19th Phase inverter, the 20th phase inverter, the 21st phase inverter, the 22nd phase inverter, the 23rd phase inverter, the 9th trigger, Tenth trigger, the 11st trigger, the 24th phase inverter and the 25th phase inverter；

The input terminal of tenth phase inverter as the first trigger signal input terminal, the output end of the tenth phase inverter with The first input end of second nor gate connects, and the first of the output end of second nor gate and the third nor gate is defeated Enter end connection, the second input terminal of the third nor gate is as the second trigger signal input terminal, the third nor gate Third input terminal connect with the power-on reset signal input terminal, the second input terminal of second nor gate, the described tenth The signal behavior input terminal of the input terminal of one phase inverter, the output end of the third nor gate and the second selector is total It connects, the second of the output end of the 11st phase inverter, the input terminal of the 12nd phase inverter and first NAND gate Input terminal connects altogether, and the output end of first NAND gate is connect with the input terminal of the 13rd phase inverter, and the described 13rd is anti- The output end of phase device is connect with the second input terminal of the four nor gate, the first input end of the four nor gate with it is described The power-on reset signal input terminal of signal behavior processing module connects, and the output end of the four nor gate is anti-with the described 14th The input terminal of phase device connects, and the output end of the 14th phase inverter resets letter as the second of the signal behavior processing module Number output end, the output end of the 12nd phase inverter are connect with the signal behavior input terminal of the third selector, and described Internal frequency signal input part of first signal input part of two selectors as the signal behavior processing module, described second The second signal input terminal of selector is connect with the output end of the tenth hex inverter, the input terminal of the tenth hex inverter It is connect with the output end of the 15th phase inverter, the input terminal of the 15th phase inverter handles mould as the signal behavior The External frequency signals input terminal of block, the output end of the second selector are connect with the input terminal of the eighteen incompatibilities phase device, The output end of the eighteen incompatibilities phase device, the first input end of second NAND gate, the 19th phase inverter input terminal And the second input terminal of the 9th trigger connects altogether, output end and the 9th trigger of the 19th phase inverter First input end connection, the first output end of the 9th trigger are connect with the second input terminal of the tenth trigger, institute The second output terminal for stating the 9th trigger is connect with the first input end of the tenth trigger, and the first of the tenth trigger Output end is connect with the second input terminal of the 11st trigger, the second output terminal and the described tenth of the tenth trigger The first input end of one trigger connects, the output end of the 11st trigger and the input terminal of the 24th phase inverter Connection, the input terminal of the 25th phase inverter are connect with the output end of the 24th phase inverter, and the described 25th The output end of phase inverter is connect with the first input end of first NAND gate, the reset terminal of the 9th trigger, described The reset terminal of the reset terminal of ten triggers and the 11st trigger connects altogether, the first signal input of the third selector End is connect with the output end of the 17th phase inverter, and the signal behavior input terminal of the third selector is anti-with the described 12nd The output end of phase device connects, and the second signal input terminal of the third selector is connect with the first power supply, the third choosing The output end for selecting device is connect with the second input terminal of second NAND gate, the output end of second NAND gate and the described tenth The input terminal of nine phase inverters connects, and the output end of the 19th phase inverter and the input terminal of the 20th phase inverter connect work altogether For the first frequency signal output end of the signal behavior processing module, the output end and described second of the 20th phase inverter The input terminal of 11 phase inverters connects the second frequency signal output end as the signal behavior processing module altogether, and the described 20th The output end of one phase inverter is connect with the input terminal of the 22nd phase inverter, the output end of the 22nd reverser with The input terminal of 23rd phase inverter connects, and the output end of the 23rd phase inverter is handled as the signal behavior The third frequency signal output end of module.

8. a kind of system for exporting synchronous frequency signal, which is characterized in that the system comprises the first chips and multiple same Chip is walked, includes such as the described in any item shared oscillations of claim 1-7 inside the first chip and multiple synchronizing chips Device frequency output circuitry；

The External frequency signals input terminal and the External frequency signals of the external input signal detection module of first chip Source connection, the internal frequency signal input part of the internal frequency signal detection module of first chip and first chip The connection of internal oscillator signal source；

The External frequency signals input terminal of the external input signal detection module of multiple synchronizing chips and first chip Signal behavior processing module third frequency signal output end connection, the internal frequency signal detection of multiple synchronizing chips Internal oscillator signal source of the internal frequency signal input part of module respectively with multiple synchronizing chips connects one to one.

9. system as claimed in claim 8, which is characterized in that the period 1 reset signal of the first chip output passes through The External frequency signals input terminal of multiple synchronizing chips is output to multiple synchronizing chips, and multiple synchronizing chips are logical It crosses and the pulse pair period 1 reset signal and third frequency signal of the signal of external frequency signal input end input is carried out Identification.

10. system as claimed in claim 9, which is characterized in that the period 1 reset signal is used for first core Piece and multiple synchronizing chips are resetted.