CN205485435U - Microcontroller and timer conter thereof - Google Patents
Microcontroller and timer conter thereof Download PDFInfo
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- CN205485435U CN205485435U CN201620019595.XU CN201620019595U CN205485435U CN 205485435 U CN205485435 U CN 205485435U CN 201620019595 U CN201620019595 U CN 201620019595U CN 205485435 U CN205485435 U CN 205485435U
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Abstract
The utility model belongs to the technical field of electronic circuit, a microcontroller and timer conter thereof is provided. The utility model discloses in, timer conter includes that a timing count module, the 2nd timing count module, infrared control module, a capturing module, the 2nd capturing module and envelope signal produce the module, the carrier wave parameter and the data parameter of the exportable required carrier wave infrared code signal of decoding of this timer conter have realized decoding to carrier wave infrared code signal. Simultaneously, this timer conter still has general timing count function. Consequently, realized among the general timer conter of the decoding function of carrier wave infrared code signal embedding, so just save the peripheral circuit of realizing infrared communication decoding function, reduced the complexity of microcontroller peripheral circuit, also makeed simultaneously the control system's that constitutes by microcontroller cost reduction, reliability strengthen.
Description
Technical field
This utility model belongs to electronic circuit technology field, particularly relates to a kind of microcontroller and timer counter thereof
Device.
Background technology
Microcontroller (Micro Controller Unit, MCU) is various electronic product, industrial control system
In indispensable key control unit, in the every field produced from living to, every automatically control need
MCU chip will be used in the place asked, and in order to meet the functional requirement of different application occasion, is applied to not
With the MCU chip of occasion with different peripheral circuits.
The MCU chip being applied to infrared communication need to have the peripheral circuit realizing infrared communication decoding function,
But, when certain occasion also has other functional requirements in addition to infrared communication decoding function to be realized, then should
MCU chip also needs to increase other peripheral circuit, so substantially increases the complexity of MCU chip peripheral circuit
Property, therefore reduce the reliability of MCU chip peripheral circuit, do not meet simple to circuit structure, reliable
The requirement that property is high.Therefore, outside existing microcontroller is when being applied to infrared communication because needing outfit complicated
Enclosing circuit causes cost to increase and low the asking of reliability to realize infrared communication decoding and other functions simultaneously
Topic.
Utility model content
The purpose of this utility model is to provide the timer conter of a kind of microcontroller, it is intended to solve existing
Microcontroller is equipped with complicated peripheral circuit to realize infrared communication simultaneously when being applied to infrared communication because of needs
Decoding and other functions and cause cost to increase and the low problem of reliability.
This utility model is achieved in that the timer conter of a kind of microcontroller, described timer conter
Including the first timer counter module and the second timer counter module, described timer conter also includes infrared control
Module, the first trapping module, the second trapping module and envelope signal generation module.
The input of described first trapping module receives carrier wave infrared encoded signal, described first trapping module
First outfan and the second outfan are defeated with the first input end of described first timer counter module and second respectively
Enter end to be connected, the input of described envelope signal generation module, outfan and control end respectively with described the
The one timing control signal outfan of counting module, the input of described second trapping module and described infrared control
The outfan of molding block is connected, the first outfan of described second trapping module and the second outfan respectively with
First input end and second input of described second timer counter module are connected, described infrared control module
Outfan and described first timer counter module control end, the control end of described second timer counter module
And the Enable Pin of described envelope signal generation module is connected.
Rising edge and the trailing edge of described carrier wave infrared encoded signal are captured by described first trapping module,
And exporting the first capture control signal and the second capture control signal, described first timer counter module is according to institute
State the infrared of the first capture control signal, described second capture control signal and the output of described infrared control module
Control signal output envelope control signal and the carrier parameter of described carrier wave infrared encoded signal, described envelope is believed
Number generation module exports described carrier wave infrared coding according to described envelope control signal and described infrared control signal
The envelope signal of signal, rising edge and the trailing edge of described envelope signal are caught by described second trapping module
Obtain, and export the 3rd capture control signal and the 4th capture control signal, described second timer counter module root
Institute is exported according to described 3rd capture control signal, described 4th capture control signal and described infrared control signal
State the data parameters of carrier wave infrared encoded signal.
Another object of the present utility model is to provide a kind of microcontroller including above-mentioned timer conter.
In this utility model, timer conter include the first timer counter module, the second timer counter module,
Infrared control module, the first trapping module, the second trapping module and envelope signal generation module, this timing ga(u)ge
The carrier parameter of the carrier wave infrared encoded signal of the exportable required decoding of number device and data parameters, it is achieved that right
The decoding of carrier wave infrared encoded signal.Meanwhile, this timer conter also has general timer counter function.
It is thereby achieved that the decoding function of carrier wave infrared encoded signal is embedded in general timer conter, the most just
Eliminate the peripheral circuit realizing infrared communication decoding function, reduce the complexity of microcontroller peripheral circuit,
The cost simultaneously also making the control system being made up of microcontroller reduces, reliability strengthens.
Accompanying drawing explanation
Fig. 1 is the structural representation of the timer conter that this utility model embodiment provides；
Fig. 2 is the structural representation of the timer conter that another embodiment of this utility model provides；
Fig. 3 is that the carrier parameter that this utility model embodiment provides obtains schematic diagram；
Fig. 4 is that the another kind of carrier parameter that this utility model embodiment provides obtains schematic diagram.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing
And embodiment, this utility model is further elaborated.Should be appreciated that described herein specifically
Embodiment, only in order to explain this utility model, is not used to limit this utility model.
Fig. 1 shows the structure of the timer conter that this utility model embodiment provides, for convenience of description,
Illustrate only the part relevant to this utility model embodiment, details are as follows:
The timer conter of a kind of microcontroller includes first timer counter module the 100, second timing ga(u)ge digital-to-analogue
Block 200, infrared control module the 600, first trapping module the 300, second trapping module 400 and envelope signal
Generation module 500.
The input of the first trapping module 300 receives carrier wave infrared encoded signal, the first trapping module 300
First outfan and the second outfan are defeated with the first input end of the first timer counter module 100 and second respectively
Entering end to be connected, the input of envelope signal generation module 500, outfan and control end are fixed with first respectively
Time the control signal outfan of counting module 100, the input of the second trapping module 400 and infrared control mould
The outfan of block 600 is connected, the first outfan of the second trapping module 400 and the second outfan respectively with
First input end and second input of the second timer counter module 200 are connected, infrared control module 600
Outfan and the first timer counter module 100 control end, the control end of the second timer counter module 200
And the Enable Pin of envelope signal generation module 500 is connected.
Rising edge and the trailing edge of carrier wave infrared encoded signal are captured by the first trapping module 300, and defeated
Going out the first capture control signal and the second capture control signal, the first timer counter module 100 is caught according to first
Obtain the infrared control signal output of control signal, the second capture control signal and infrared control module 600 output
Envelope control signal and the carrier parameter of carrier wave infrared encoded signal, envelope signal generation module 500 is according to bag
Network control signal and the envelope signal of infrared control signal outgoing carrier infrared encoded signal, the second trapping module
Rising edge and the trailing edge of 400 pairs of envelope signals capture, and export the 3rd capture control signal and the 4th
Capture control signal, the second timer counter module 200 controls according to the 3rd capture control signal, the 4th capture
Signal and the data parameters of infrared control signal outgoing carrier infrared encoded signal.
Concrete, the input of envelope signal generation module 500 includes set input S and clear input
C。
Preferably, infrared control module 600 controls depositor, envelope signal generation module 500 for infrared decoding
For depositor.
Concrete, it is eight bit register that infrared decoding controls depositor, and the 0th of eight bit register is first
The infrared decoding of timer counter module 100 and the second timer counter module 200 enables position, eight bit register
2nd be the first timer counter module 100 and the second timer counter module 200 capture enable position, 8
The output that 3rd is envelope signal generation module 500 of depositor enables position.
As this utility model one embodiment, as in figure 2 it is shown, the first trapping module 300 includes the first rising
Along capturing unit 301 and the first trailing edge capturing unit 302, the input of the first rising edge capturing unit 301
The input of end and the first trailing edge capturing unit 302 connects the input forming the first trapping module 300 altogether,
The outfan of the first rising edge capturing unit 301 and the outfan of the first trailing edge capturing unit 302 are respectively
First outfan of the first trapping module 300 and the second outfan.
Concrete, the first rising edge capturing unit 301 includes the depositor that dual serial connects, and is used for capturing
The rising edge time of carrier wave infrared encoded signal, and export the first capture control signal.First trailing edge capture
Unit 302 includes the depositor that dual serial connects, during for capturing the trailing edge of carrier wave infrared encoded signal
Carve, and export the second capture control signal.
As this utility model one embodiment, as in figure 2 it is shown, the second trapping module 400 includes the second rising
Along capturing unit 401 and the second trailing edge capturing unit 402, the input of the second rising edge capturing unit 401
The input of end and the second trailing edge capturing unit 402 connects the input forming the second trapping module 400 altogether,
The outfan of the second rising edge capturing unit 401 and the outfan of the second trailing edge capturing unit 402 are respectively
First outfan of the second trapping module 400 and the second outfan.
Concrete, the second rising edge capturing unit 401 includes the depositor that dual serial connects, and is used for capturing
The rising edge time of envelope signal, and export the 3rd capture control signal.Second trailing edge capturing unit 402
The depositor connected including dual serial, for capturing trailing edge moment of envelope signal, and exports the 4th and catches
Obtain control signal.
As this utility model one embodiment, as in figure 2 it is shown, the first timer counter module 100 includes first
Clock unit CLK1, the first gating unit S1, the first counting unit T1C, the first comparing unit C1,
One trapping memory cells CAP1, the second trapping memory cells CAP2, the first signal behavior unit 102,
One logic or unit 101, period 1 memory element T1DR and the first control unit T1CON.
First trapping memory cells CAP1 controls end and the first input end of the first signal behavior unit 102
Connect the first input end forming the first timer counter module 100, the control of the second trapping memory cells CAP2 altogether
Second input of end processed and the first signal behavior unit 102 connects altogether and forms the first timer counter module 100
Second input, the outfan of the first trapping memory cells CAP1 and the second trapping memory cells CAP2's
The carrier parameter of outfan equal outgoing carrier infrared encoded signal, the outfan of the first control unit T1CON
It is connected with the control end of the first signal behavior unit 102, the input of the first trapping memory cells CAP1,
The input of the second trapping memory cells CAP2 and the first input end of the first comparing unit C1 are all with first
The outfan of counting unit T1C is connected, and second input of the first comparing unit C1 was deposited with the period 1
The outfan of storage unit T1DR is connected, and the first clock unit CLK1 connects the through the first gating unit S1
The input end of clock of one counting unit T1C, the control end of the first gating unit S1 is the first timing ga(u)ge digital-to-analogue
The control end of block 100, the first logic or the first input end of unit 101, the second input and outfan divide
Not with the outfan of the first comparing unit C1, the outfan of the first signal behavior unit 102 and the first counting
The clearing of unit T1C controls end and is connected, and the outfan of the first comparing unit C1 and the first signal behavior
The outfan of unit 102 is the control signal outfan of the first timer counter module 100.
Concrete, the outfan of the first signal behavior unit 102 also with the putting of envelope signal generation module 500
Position input S-phase connect, the outfan of the first comparing unit C1 also with envelope signal generation module 500
Clear input C is connected.
Concrete, the first clock unit CLK1 is made up of microcontroller crystal oscillator and frequency dividing circuit；First
Gating unit S1 for enabling switch, the first gating unit S1 by infrared decoding control the 0th of depositor and
2nd co-controlling, when infrared decoding controls the 0th of depositor and the 2nd equal set is 1, the
The input of one gating unit S1 connects with outfan；First counting unit T1C is enumerator；First ratio
Relatively unit C1 is comparator；First trapping memory cells CAP1 and the second trapping memory cells CAP2 is
Capture depositor；First signal behavior unit 102 is signal selector, and signal selector is according to control signal
Select a road input signal output；First logic or unit 101 are or door；Period 1 memory element T1DR
For period register；First control unit T1CON is the control depositor in general timer conter.
As this utility model one embodiment, as in figure 2 it is shown, the second timer counter module 200 includes second
Clock unit CLK2, the second gating unit S2, the second counting unit T2C, the second comparing unit C2,
Three trapping memory cells CAP3, the 4th trapping memory cells CAP4, secondary signal select unit 202, the
Two logics or unit 201, memory element T2DR second round and the second control unit T2CON.
The first input end controlling end and secondary signal selection unit 202 of the 3rd trapping memory cells CAP3
Connect the first input end forming the second timer counter module 200, the control of the 4th trapping memory cells CAP4 altogether
End processed and secondary signal select the second input of unit 202 to connect altogether and form the second timer counter module 200
Second input, the outfan of the 3rd trapping memory cells CAP3 and the 4th trapping memory cells CAP4's
The data parameters of outfan equal outgoing carrier infrared encoded signal, the outfan of the second control unit T2CON
The control end selecting unit 202 with secondary signal is connected, the input of the 3rd trapping memory cells CAP3,
The input of the 4th trapping memory cells CAP4 and the first input end of the second comparing unit C2 are all with second
The outfan of counting unit T2C is connected, and second input of the second comparing unit C2 was deposited with second round
The outfan of storage unit T2DR is connected, and second clock unit CLK2 connects the through the second gating unit S2
The input end of clock of two counting units T2C, the control end of the second gating unit S2 is the second timing ga(u)ge digital-to-analogue
The control end of block 200, the second logic or the first input end of unit 201, the second input and outfan divide
Outfan and second counting of unit 202 is not selected with the outfan of the second comparing unit C2, secondary signal
The clearing of unit T2C controls end and is connected, and the outfan of the second comparing unit C2 and secondary signal select
The outfan of unit 202 is the control signal outfan of the second timer counter module 200.
Concrete, second clock unit CLK2 is made up of microcontroller crystal oscillator and frequency dividing circuit；Second
Gating unit S2 for enabling switch, the second gating unit S2 by infrared decoding control the 0th of depositor and
2nd co-controlling, when infrared decoding controls the 0th of depositor and the 2nd equal set is 1, the
The input of two gating unit S2 connects with outfan；Second counting unit T2C is enumerator；Second ratio
Relatively unit C2 is comparator；3rd trapping memory cells CAP3 and the 4th trapping memory cells CAP4 is
Capture depositor；Secondary signal selects unit 202 to be signal selector, and signal selector is according to control signal
Select a road input signal output；Second logic or unit 201 are or door；Second round memory element T2DR
For period register；Second control unit T2CON is the control depositor in general timer conter.
Below in conjunction with operation principle, the timer conter shown in Fig. 2 is described in detail:
The process being decoded carrier wave infrared encoded signal includes: obtain the carrier wave of carrier wave infrared encoded signal
Parameter, the envelope signal obtaining carrier wave infrared encoded signal and the data parameters of acquisition carrier wave infrared encoded signal.
The principle of the carrier parameter obtaining carrier wave infrared encoded signal is as follows:
The carrier parameter of carrier wave infrared encoded signal is by the first trapping module 300 and the first timer counter module
100 obtain, and the carrier parameter of carrier wave infrared encoded signal is high electricity in including carrier cycle and a carrier cycle
Flat or low level duration.Concrete acquisition process is as follows: infrared control module 600 controls the first gating unit
The input of S1 connects with outfan, and the first control unit T1CON controls the first signal behavior unit 102
Work in rising edge strobe pattern.First counting unit T1C starts counting up, when the first rising edge capturing unit
During the rising edge that 301 capture carrier wave infrared encoded signal, the first rising edge capturing unit 301 exports high electricity
Ordinary mail number, this high level signal is defeated through the first signal behavior unit 102 to the first logic or unit 101
Enter end, so that the count value of the first counting unit T1C resets；When the first trailing edge capturing unit 302 is caught
When receiving the trailing edge of carrier wave infrared encoded signal, the first trailing edge capturing unit 302 exports high level signal
So that the second trapping memory cells CAP2 stores and exports the count value of the first counting unit T1C, this counting
Value is the high level duration in a carrier cycle, owing to the first control unit T1CON controls the first letter
Number select unit 102 work in rising edge strobe pattern, high level signal now can not pass through the first signal
Select unit 102, thus the count value of the first counting unit T1C can not be made to reset；When the first rising edge is caught
When obtaining the rising edge that unit 301 captures carrier wave infrared encoded signal again, the first rising edge capturing unit 301
Output high level signal, this high level signal makes the first trapping memory cells CAP1 store and export the first meter
The count value of counting unit T1C, this count value is carrier cycle, and this high level signal is through the first letter simultaneously
Number select unit 102 to the first logic or the input of unit 101, make the counting of the first counting unit T1C
Value resets.First trapping memory cells CAP1 and the second trapping memory cells CAP2 exports the count value moment
With corresponding relation reference Fig. 3 of carrier wave infrared encoded signal, wherein, IR represents carrier wave infrared encoded signal.
In above-mentioned work process, the first control unit T1CON also can control the first signal behavior unit 102
Work in trailing edge gated mode, when the first signal behavior unit 102 works in trailing edge gated mode,
The high level signal of the first trailing edge capturing unit 302 output can be by the first signal behavior unit 102 to the
One logic or unit 101, so that the count value of the first counting unit T1C resets, and the first rising edge is caught
The high level signal obtaining unit 301 output can not pass through the first signal behavior unit 102, and therefore, first catches
The count value obtaining the output of memory element CAP1 is low level duration in a carrier cycle, and the second capture is deposited
The count value of storage unit CAP2 output is carrier cycle.First trapping memory cells CAP1 and second capture
Corresponding relation reference Fig. 4 of memory element CAP2 output count value moment and carrier wave infrared encoded signal, its
In, IR represents carrier wave infrared encoded signal.
In order to the carrier parameter making the carrier wave infrared encoded signal of acquisition is the most accurate, rising can be performed a plurality of times
Along capture or trailing edge capture, and carry out mean value computation to repeatedly capturing the count value obtained.
The principle of the envelope signal obtaining carrier wave infrared encoded signal is as follows:
Infrared control module 600 makes the control end of envelope signal generation module 500 be high level, namely makes
The output function of energy envelope signal generation module 500, the storage value of period 1 memory element T1DR is 1.5*
Carrier cycle.When the first signal behavior unit 102 exports high level signal, envelope signal generation module 500
Output high level；Count value and the storage of period 1 memory element T1DR when the first counting unit T1C
When being worth equal, the first comparing unit C1 exports high level signal, and now envelope signal generation module 500 is defeated
Go out low level.The signal of envelope signal generation module 500 output continuously in time is carrier wave infrared coding
The envelope signal of signal.
The principle of the data parameters obtaining carrier wave infrared encoded signal is as follows:
The data parameters of carrier wave infrared encoded signal includes the duration in envelope signal each cycle and in each cycle
High level or low level duration, obtain principle and the acquisition carrier wave of the data parameters of carrier wave infrared encoded signal
The principle of the carrier parameter of infrared encoded signal is identical.When the second control unit T2CON controls secondary signal
When selecting unit 202 to work in rising edge strobe pattern, the counting of the 3rd trapping memory cells CAP3 output
Value is the duration in envelope signal each cycle, and the count value of the 4th trapping memory cells CAP4 output is each
The duration of high level in cycle, wherein, reaches when the second counting unit T2C counts from zero its count value
Second round memory element T2DR storage value after when continuing to count from zero, then the cycle of envelope signal
The time count value of a length of 3rd trapping memory cells CAP3 output and memory element T2DR second round
Storage value sum；Unit 202 is selected to work in decline when the second control unit T2CON controls secondary signal
During along gated mode, in the count value of the 3rd trapping memory cells CAP3 output is envelope signal each cycle
Low level duration, the count value of the 4th trapping memory cells CAP4 output is envelope signal each cycle
Duration, wherein, reaches storage second round list when the second counting unit T2C counts from zero its count value
After the storage value of unit T2DR when continuing to count from zero, then the cycle of envelope signal time a length of 4th catch
Obtain the count value of memory element CAP4 output and the storage value sum of memory element T2DR second round.
Based on above-mentioned timer conter application advantage in the microcontroller, this utility model additionally provides one
Microcontroller including timer conter.
In this utility model, timer conter includes first timer counter module the 100, second timer counter
Module 200, infrared control module the 600, first trapping module the 300, second trapping module 400 and envelope letter
Number generation module 500, the carrier wave of the carrier wave infrared encoded signal of the exportable required decoding of this timer conter
Parameter and data parameters, it is achieved that the decoding to carrier wave infrared encoded signal.Meanwhile, this timer conter is also
There is general timer counter function.It is thereby achieved that the decoding function of carrier wave infrared encoded signal is embedded
In general timer conter, the most just eliminate the peripheral circuit realizing infrared communication decoding function, reduce
The complexity of microcontroller peripheral circuit, also makes the cost fall of the control system being made up of microcontroller simultaneously
Low, reliability strengthens.
The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model,
All any amendment, equivalent and improvement etc. made within spirit of the present utility model and principle, all should
Within being included in protection domain of the present utility model.
Claims (8)
1. a timer conter for microcontroller, described timer conter include the first timer counter module and
Second timer counter module, it is characterised in that described timer conter also include infrared control module, first
Trapping module, the second trapping module and envelope signal generation module；
The input of described first trapping module receives carrier wave infrared encoded signal, described first trapping module
First outfan and the second outfan are defeated with the first input end of described first timer counter module and second respectively
Enter end to be connected, the input of described envelope signal generation module, outfan and control end respectively with described the
The one timing control signal outfan of counting module, the input of described second trapping module and described infrared control
The outfan of molding block is connected, the first outfan of described second trapping module and the second outfan respectively with
First input end and second input of described second timer counter module are connected, described infrared control module
Outfan and described first timer counter module control end, the control end of described second timer counter module
And the Enable Pin of described envelope signal generation module is connected；
Rising edge and the trailing edge of described carrier wave infrared encoded signal are captured by described first trapping module,
And exporting the first capture control signal and the second capture control signal, described first timer counter module is according to institute
State the infrared of the first capture control signal, described second capture control signal and the output of described infrared control module
Control signal output envelope control signal and the carrier parameter of described carrier wave infrared encoded signal, described envelope is believed
Number generation module exports described carrier wave infrared coding according to described envelope control signal and described infrared control signal
The envelope signal of signal, rising edge and the trailing edge of described envelope signal are caught by described second trapping module
Obtain, and export the 3rd capture control signal and the 4th capture control signal, described second timer counter module root
Institute is exported according to described 3rd capture control signal, described 4th capture control signal and described infrared control signal
State the data parameters of carrier wave infrared encoded signal.
2. timer conter as claimed in claim 1, it is characterised in that described first trapping module includes
First rising edge capturing unit and the first trailing edge capturing unit, the input of described first rising edge capturing unit
The input of end and described first trailing edge capturing unit connects the input forming described first trapping module altogether,
The outfan of described first rising edge capturing unit and the outfan of described first trailing edge capturing unit are respectively
First outfan of described first trapping module and the second outfan.
3. timer conter as claimed in claim 1, it is characterised in that described second trapping module includes
Second rising edge capturing unit and the second trailing edge capturing unit, the input of described second rising edge capturing unit
The input of end and described second trailing edge capturing unit connects the input forming described second trapping module altogether,
The outfan of described second rising edge capturing unit and the outfan of described second trailing edge capturing unit are respectively
First outfan of described second trapping module and the second outfan.
4. timer conter as claimed in claim 1, it is characterised in that described first timer counter module
Including the first clock unit, the first gating unit, the first counting unit, the first comparing unit, the first capture
Memory element, the second trapping memory cells, the first signal behavior unit, the first logic or unit, first week
Phase memory element and the first control unit；
The first input end controlling end and described first signal behavior unit of described first trapping memory cells is altogether
Connect the first input end forming described first timer counter module, the control end of described second trapping memory cells
Connect altogether with the second input of described first signal behavior unit and form the second of described first timer counter module
Input, the outfan of described first trapping memory cells and the outfan of described second trapping memory cells are equal
Export the carrier parameter of described carrier wave infrared encoded signal, the outfan of described first control unit and described the
The control end of one signal behavior unit is connected, the input of described first trapping memory cells, described second
The input of trapping memory cells and the first input end of described first comparing unit are all single with described first counting
The outfan of unit is connected, the second input of described first comparing unit and described period 1 memory element
Outfan be connected, it is single that described first clock unit connects described first counting through described first gating unit
The input end of clock of unit, the control that control end is described first timer counter module of described first gating unit
End, described first logic or the first input end of unit, the second input and outfan are respectively with described first
The outfan of comparing unit, the outfan of described first signal behavior unit and described first counting unit clear
Zero controls end is connected, and the outfan of described first comparing unit and described first signal behavior unit is defeated
Go out end and be the control signal outfan of described first timer counter module.
5. timer conter as claimed in claim 1, it is characterised in that described second timer counter module
Including second clock unit, the second gating unit, the second counting unit, the second comparing unit, the 3rd capture
Memory element, the 4th trapping memory cells, secondary signal select unit, the second logic or unit, second week
Phase memory element and the second control unit；
The end that controls of described 3rd trapping memory cells selects the first input end of unit altogether with described secondary signal
Connect the first input end forming described second timer counter module, the control end of described 4th trapping memory cells
Select the second input of unit to connect altogether with described secondary signal and form the second of described second timer counter module
Input, the outfan of described 3rd trapping memory cells and the outfan of described 4th trapping memory cells are equal
Export the data parameters of described carrier wave infrared encoded signal, the outfan of described second control unit and described the
Binary signal selects the control end of unit to be connected, the input of described 3rd trapping memory cells, the described 4th
The input of trapping memory cells and the first input end of described second comparing unit are all single with described second counting
The outfan of unit is connected, the second input of described second comparing unit and memory element described second round
Outfan be connected, it is single that described second clock unit connects described second counting through described second gating unit
The input end of clock of unit, the control that control end is described second timer counter module of described second gating unit
End, described second logic or the first input end of unit, the second input and outfan are respectively with described second
The outfan of comparing unit, described secondary signal select the outfan of unit and the clear of described second counting unit
Zero controls end is connected, and the outfan of described second comparing unit and described secondary signal select the defeated of unit
Go out end and be the control signal outfan of described second timer counter module.
6. timer conter as claimed in claim 1, it is characterised in that described infrared control module is red
Outer decoding controls depositor.
7. timer conter as claimed in claim 6, it is characterised in that described infrared decoding controls to deposit
Device is eight bit register, and the 0th of described eight bit register is described first timer counter module and described
The infrared decoding of two timer counter modules enables position, and the 2nd of described eight bit register is described first timing
The capture of counting module and described second timer counter module enables position, and the 3rd of described eight bit register is
The output of described envelope signal generation module enables position.
8. a microcontroller, it is characterised in that described microcontroller includes as claim 1 to 7 is arbitrary
Timer conter described in Xiang.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620019595.XU CN205485435U (en) | 2016-01-07 | 2016-01-07 | Microcontroller and timer conter thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620019595.XU CN205485435U (en) | 2016-01-07 | 2016-01-07 | Microcontroller and timer conter thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205485435U true CN205485435U (en) | 2016-08-17 |
Family
ID=56666329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620019595.XU Active CN205485435U (en) | 2016-01-07 | 2016-01-07 | Microcontroller and timer conter thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205485435U (en) |
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2016
- 2016-01-07 CN CN201620019595.XU patent/CN205485435U/en active Active
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