CN103684423A - Variable synchronous clock frequency division circuit - Google Patents
Variable synchronous clock frequency division circuit Download PDFInfo
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- CN103684423A CN103684423A CN201210362745.3A CN201210362745A CN103684423A CN 103684423 A CN103684423 A CN 103684423A CN 201210362745 A CN201210362745 A CN 201210362745A CN 103684423 A CN103684423 A CN 103684423A
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Abstract
The invention discloses a variable synchronous clock frequency division circuit which comprises a clock counter, a frequency division multiple configuration register, a comparator and a gating logic circuit, wherein the clock counter is used for counting the number of input source clocks, the frequency division multiple configuration register is used for registering a clock frequency division multiple, an output gating logic enable signal is invalid when the value of the clock counter and the value of the frequency division multiple configuration register are not equal through comparison, the output gating logic enable signal is valid when the two values are equal, the gating logic circuit is switched off when the output gating logic enable signal is invalid, the source clocks are frequency-divided and output when the output gating logic enable signal is valid, and the value of the clock timer returns to zero in the next clock cycle. According to the variable synchronous clock frequency division circuit, arbitrary integer division can be carried out, and the frequency division multiple can be configured in a certain range.
Description
Technical field
The present invention relates to clock division circuits field, particularly relate to a kind of variable synchronous clock frequency dividing circuit.
Background technology
Digital integrated circuit is applied in the middle of actual life more and more widely, little of household electrical appliance, smart card system, and arrive greatly computer graphical and process, electronic communication and large-scale processor etc., it all occupies an important position therein.Along with the development in epoch, people are more and more higher to the performance requirement of digital circuit, as area, and power consumption, functional diversity etc.
Clock is the important component part of digital circuit, so long as sequence circuit, just be unable to do without clock, and therefore, Clock Design is the basis of the multifunctional digital circuit that becomes increasingly complex now, and it directly affects the performance of digital circuit, particularly speed and power consumption.Clock frequency is higher, and circuit speed is faster; Timing topology is cleaner, and Clock Tree time delay is shorter, and in the situation that other conditions are constant, the power consumption of circuit accordingly will be less.
In clock circuit, frequency dividing circuit is more common a kind of circuit, and almost all to need original high frequency clock frequency division be low-frequency clock to most of digital circuit, for the circuit of other different pieces, uses.Therefore, the structure of frequency dividing circuit, also has positive effect to improving chip performance, and a good frequency dividing circuit is concerning circuit performance requires more and more higher chip design, most important.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of variable synchronous clock frequency dividing circuit, can carry out arbitrary integer frequency division, and can configure frequency division multiple within the specific limits.
For solving the problems of the technologies described above, variable synchronous clock frequency dividing circuit of the present invention, comprising:
One clock counter, its input end of clock input source clock, its reset terminal input asynchronous reset signal, for counting the source clock number of input;
One frequency division multiple configuration register, for depositing clock division multiple;
One comparator, one input end is connected with the output of the register of described clock counter, and another input is connected with the output of described frequency division multiple configuration register, the enable signal of its output output gate logic; After the value of described clock counter and the value of frequency division multiple configuration register compare, when both do not wait, the enable signal of described gate logic is invalid; After the value of described clock counter and the value of frequency division multiple configuration register compare, when both are equal, the enable signal of described gate logic is effective;
One gate logical circuit, its data input pin is connected with the output of described comparator, and its Enable Pin is connected with the input end of clock of described clock counter, input source clock; When the enable signal of described gate logic is invalid, this gate logical circuit is closed; When the enable signal of described gate logic is effective, this gate logical circuit will be exported after the clock division of source, and the value of clock counter made zero in the next clock cycle.
The present invention can carry out arbitrary integer frequency division, and can configure frequency division multiple within the specific limits; Meanwhile, utilize the feature of synchronous clock frequency dividing circuit, and add a gate logic, both can remove the burr of introducing because of asynchronous reset on clock, also can reduce the time delay on Clock Tree.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is existing synchronization frequency division circuit theory diagrams;
Fig. 2 is the synchronous clock frequency dividing circuit theory diagrams after improving;
Fig. 3 is gate logical circuit embodiment mono-schematic diagram;
Fig. 4 is gate logical circuit embodiment bis-schematic diagrams.
Embodiment
Referring to Fig. 1, existing synchronization frequency division circuit consists of a clock counter Counter, supposes that source clock is clk, and asynchronous reset signal is rst, need to carry out 2 to source clock clk
nfrequency division, wherein n is positive integer; The bit wide of the register of clock counter Counter is n so, its m bit register output Counter[m] be 2
(m+1)frequency-dividing clock, corresponding the 0th, the 1st, m position and highest order n-1 bit register, be respectively 2 frequency divisions, 4 frequency divisions, 2
(m+1)frequency division and 2
nfractional frequency signal.This synchronization frequency division circuit device is simple in structure, is easy to realize, but also has following shortcoming:
1, can only carry out 2 index multiple frequency division, i.e. 2 frequency divisions, 4 frequency divisions, 8 frequency divisions etc., can not carry out other multiple frequency division, as 3 frequency divisions, 6 frequency divisions, 9 frequency divisions etc.
2, clock division circuits belongs to the part above Clock Tree, and in back-end realization, Clock Tree can, through the register of clock division circuits, strengthen clock delay.
3, when clock division circuits needs an asynchronous reset signal to reset to it in design, can on each frequency-dividing clock, introduce a burr causing because of asynchronous reset, clock quality is declined, What is more, may cause disabler.
Fig. 2 carries out improved synchronous clock frequency dividing circuit on the circuit structure of synchronization frequency division shown in Fig. 1 basis, on the basis of original clock counter, has increased a frequency division multiple configuration register, a comparator and a gate logical circuit.
The output of the register of described clock counter Counter is connected with an input of described comparator, the output of described frequency division multiple configuration register is connected with another input of described comparator, the output of described comparator is connected with the data input pin of described gate logical circuit, and the input end of clock of described clock counter Counter is connected with the Enable Pin of described gate logical circuit.The enable signal enable of the output output gate logic of described comparator.
What in described frequency division multiple configuration register, deposit is frequency division multiple, according to demand readable writing.The function of described clock counter Counter is the same with traditional synchronization frequency division circuit, and the number of clock pulse is counted.Described comparator compares the value of the value of clock counter Counter and frequency division multiple configuration register, and when both do not wait, the enable signal enable of the gate logic of its output is invalid, and described gate logical circuit is closed; Otherwise when both are equal, the enable signal enable of gate logic is effective, and will after the clock clk frequency division of source, by output terminal of clock gclk, be exported, and the value of clock counter Counter made zero in the next clock cycle.
As can be seen here, the synchronous clock frequency dividing circuit after improvement can carry out arbitrary integer clock division doubly by frequency division multiple configuration register, and frequency division multiple is able to programme; Clock path, only through a gate logical circuit, is compared with the register through clock counter Counter in conventional synchronization frequency dividing circuit, and the time delay increasing is less.In addition, asynchronous reset signal rst is when carrying out asynchronous reset to clock counter, the burr of introducing on the register of clock counter Counter, can transfer on the enable signal enable of gate logic, by gate logical circuit, filtered subsequently, guarantee the quality of clock after frequency division, improved the stability of circuit.
Described synchronous clock frequency dividing circuit can be achieved through the following technical solutions: according to frequency division scope, determine clock counter scale and clock division multiple configuration register scale, by the value of comparison clock counter and clock division multiple configuration register, obtain the enable signal of gate logic, utilize the enable signal of gate logic to carry out frequency division to source clock.Its concrete steps are as follows:
Step 2, according to frequency division scope, determine the scale of clock division multiple configuration register.In general, the scale of clock counter is the same with the scale of clock division multiple configuration register, that is to say, when the register bit wide of clock counter is n, the bit wide of clock division multiple configuration register is also n so, unless be designed with special requirement.
Step 3, utilize comparator, produce the enable signal of gate logic.If the value of clock counter is not equal to the value of clock division multiple configuration register, the enable signal of gate logic is invalid, otherwise, be effectively, and clock counter was made zero in the next clock cycle.
Step 4, according to clock characteristic requirement, select suitable gate logical circuit, and complete the design of synchronous clock frequency dividing circuit.Gate logical circuit is to consist of a latch and a gate, and different if clock characteristic requires, the structure of gate logical circuit is also different.
If require clock when closing in high level, so need the gate logical circuit of a high pass latch and or a composition, as shown in Figure 3.The enable signal enable of the data input pin D input gate logic of described high pass latch GS, its Enable Pin G input source clock clk; The output Q of described high pass latch GS with one or door OR an input be connected, should or door OR another input be connected with the Enable Pin G of described high pass latch GS, input source clock clk.Output described or door OR is the output terminal of clock gclk after frequency division.
If require clock when closing in low level, so need a gate logical circuit for a low pass latch and and door composition, as shown in Figure 4.The enable signal enable of the data input pin D input gate logic of described low pass latch DS, its Enable Pin GN input source clock clk(Low level effective); The output Q of described low pass latch DS is connected with an input of door AND with one, should be connected with the Enable Pin GN of described low pass latch DS with another input of door AND, and input source clock clk.Output described and door AND is the output terminal of clock gclk after frequency division.
In general technology library, for above-mentioned two kinds of typical gate logical circuits, there is integrated gated devices, when realizing, can select according to real needs.According to Fig. 3 and Fig. 4, can find out, the logical device passing on clock path be one with door or or door, what pass with conventional synchronization frequency dividing circuit is that a register is compared, the time delay adding is much smaller.
Step 5, according to the synchronous clock frequency dividing circuit shown in the selected gate logical circuit of step 4 and Fig. 2, complete the design of whole synchronous clock frequency dividing circuit.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a variable synchronous clock frequency dividing circuit, comprising:
One clock counter, its input end of clock input source clock, its reset terminal input asynchronous reset signal, for counting the source clock number of input; It is characterized in that, also comprise:
One frequency division multiple configuration register, for depositing clock division multiple;
One comparator, one input end is connected with the output of the register of described clock counter, and another input is connected with the output of described frequency division multiple configuration register, the enable signal of its output output gate logic; After the value of described clock counter and the value of frequency division multiple configuration register compare, when both do not wait, the enable signal of described gate logic is invalid; After the value of described clock counter and the value of frequency division multiple configuration register compare, when both are equal, the enable signal of described gate logic is effective;
One gate logical circuit, its data input pin is connected with the output of described comparator, and its Enable Pin is connected with the input end of clock of described clock counter, input source clock; When the enable signal of described gate logic is invalid, this gate logical circuit is closed; When the enable signal of described gate logic is effective, this gate logical circuit will be exported after the clock division of source, and the value of clock counter made zero in the next clock cycle.
2. synchronous clock frequency dividing circuit as claimed in claim 1, is characterized in that: the bit wide of the bit wide of the register of described clock counter and frequency division multiple configuration register equates.
3. synchronous clock frequency dividing circuit as claimed in claim 1, is characterized in that: described gate logical circuit comprises a high pass latch, one or door; The enable signal of the data input pin input gate logic of described high pass latch, its Enable Pin input source clock, its output is connected with an input described or door, should or door another input be connected with the Enable Pin of described high pass latch, input source clock, output described or door is output terminal of clock; Make source clock when closing in high level.
4. synchronous clock frequency dividing circuit as claimed in claim 1, is characterized in that: described gate logical circuit comprises a low pass latch, one with door; The enable signal of the data input pin input gate logic of described low pass latch, its Enable Pin input source clock, its output is connected with an input of door with described, should be connected with the Enable Pin of described low pass latch with another input of door, input source clock, output described and door is output terminal of clock; Make source clock when closing in low level.
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| CN201210362745.3A CN103684423A (en) | 2012-09-25 | 2012-09-25 | Variable synchronous clock frequency division circuit |
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| CN201210362745.3A CN103684423A (en) | 2012-09-25 | 2012-09-25 | Variable synchronous clock frequency division circuit |
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| CN104242885A (en) * | 2014-09-11 | 2014-12-24 | 福州瑞芯微电子有限公司 | Reset circuit and circuit resetting method |
| CN107565936A (en) * | 2017-08-28 | 2018-01-09 | 上海集成电路研发中心有限公司 | A kind of logic realization device of input clock stabilizing circuit |
| CN107786200A (en) * | 2016-08-31 | 2018-03-09 | 中国科学院大连化学物理研究所 | A kind of frequency divider |
| CN109635355A (en) * | 2018-11-19 | 2019-04-16 | 北京时代民芯科技有限公司 | A kind of adjustable filter circuit of frequency towards GPIO |
| CN114726367A (en) * | 2022-06-02 | 2022-07-08 | 上海泰矽微电子有限公司 | Gate-controlled low-jitter clock frequency division circuit and control method |
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Cited By (8)
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| CN104242885A (en) * | 2014-09-11 | 2014-12-24 | 福州瑞芯微电子有限公司 | Reset circuit and circuit resetting method |
| CN107786200A (en) * | 2016-08-31 | 2018-03-09 | 中国科学院大连化学物理研究所 | A kind of frequency divider |
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| CN107565936A (en) * | 2017-08-28 | 2018-01-09 | 上海集成电路研发中心有限公司 | A kind of logic realization device of input clock stabilizing circuit |
| CN109635355A (en) * | 2018-11-19 | 2019-04-16 | 北京时代民芯科技有限公司 | A kind of adjustable filter circuit of frequency towards GPIO |
| CN109635355B (en) * | 2018-11-19 | 2023-04-18 | 北京时代民芯科技有限公司 | GPIO-oriented frequency-adjustable filter circuit |
| CN114726367A (en) * | 2022-06-02 | 2022-07-08 | 上海泰矽微电子有限公司 | Gate-controlled low-jitter clock frequency division circuit and control method |
| CN114726367B (en) * | 2022-06-02 | 2022-08-23 | 上海泰矽微电子有限公司 | Gate-controlled low-jitter clock frequency division circuit and control method |
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Application publication date: 20140326 |