CN208110589U - mipi communication interface circuit - Google Patents
mipi communication interface circuit Download PDFInfo
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- CN208110589U CN208110589U CN201820322062.8U CN201820322062U CN208110589U CN 208110589 U CN208110589 U CN 208110589U CN 201820322062 U CN201820322062 U CN 201820322062U CN 208110589 U CN208110589 U CN 208110589U
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Abstract
The utility model relates to a kind of mipi communication interface circuits comprising the first analog-digital converter, the second analog-digital converter, the first shift register, the second shift register, data register, Clock dividers and mipi protocol sensing circuitry；First analog-digital converter passes sequentially through the first data input pin that the data register is connected to after first shift register；Second analog-digital converter passes sequentially through the second data input pin that the data register is connected to after second shift register；The output end of the Clock dividers is respectively connected to the input end of clock of the data register and the input end of clock of the mipi protocol sensing circuitry；The output end of the data register is connected to the data input pin of the mipi protocol sensing circuitry.The mipi communication interface circuit, processing speed higher advantage less with power consumption.
Description
Technical field
The utility model relates to mipi interface communication technologies, more particularly to a kind of mipi communication interface circuit.
Background technique
Mobile industry processor interface (Mobile Industry Processor Interface, abbreviation MIPI) be for
The open standard that mobile application processor is formulated.
Mipi dsi (digital speech interpolation) serial communication interface as a kind of high speed show communication interface mobile phone,
Tablet computer etc. show equipment on using more and more extensive.And with the raising of display technology, to the communication speed of mipi interface
The requirement of degree is also higher and higher.
The speed for the mipi communication interface that display equipment on the market uses at present at most can reach the data speed of 1.2GHz
Rate.Its circuit theory as shown in Figure 1, first carrying out adc conversion in analog end first, sentence by the matching Character decoder for then carrying out agreement
It is disconnected, it finally carries out digital end and protocol encapsulation packet is decoded.
Due to carry out matching Character decoder judgement to signal at breadboardin end, this decision circuitry will be in serial data
It is executed under rate, causes the power consumption of circuit big, speed is difficult to improve.
Utility model content
It is less with power consumption the purpose of the utility model is to provide a kind of mipi communication interface circuit based on this,
The higher advantage of processing speed.
A kind of mipi communication interface circuit, including the first analog-digital converter, the second analog-digital converter, the first shift LD
Device, the second shift register, data register, Clock dividers and mipi protocol sensing circuitry；
First analog-digital converter is connected to the data register after passing sequentially through first shift register
First data input pin；
Second analog-digital converter is connected to the data register after passing sequentially through second shift register
Second data input pin；
The output end of the Clock dividers is respectively connected to the input end of clock of the data register and described
The input end of clock of mipi protocol sensing circuitry；
The output end of the data register is connected to the data input pin of the mipi protocol sensing circuitry.
The analog difference signal of input is converted into digital signal by first analog-digital converter and the second analog-digital converter,
And respectively by the numeral output to first shift register and the second shift register, first shift register and
Second shift register respectively successively moves right two ways of digital signals one bit in each time pulse, and exports to institute
Data register is stated, the input end of clock of the data register connects the output end of the Clock dividers, in the clock
The lower rate for reducing output data of the frequency-dividing clock control of frequency divider output, makes to export to the number of the mipi protocol sensing circuitry
It is reduced according to rate, reduces the calorific value of the mipi protocol sensing circuitry, reduce power consumption, and improve processing speed.
In one embodiment, the input terminal of the Clock dividers and first, second shift register when
Clock input terminal is respectively connected to control clock.
The shift register exports after carrying out data sampling according to the control clock of input to the data register, institute
Clock dividers input control clock is stated, and the control clock is converted into the lower frequency-dividing clock of frequency and is exported to the number
According to register, keep the data of the data register synchronous with clock, reaches optimization process effect.
In one embodiment, the control clock can be system clock.
In one embodiment, first shift register includes sequentially connected first trigger, the choosing of the first multichannel
Select device, the second trigger, the second multiple selector, third trigger, third multiple selector, the 4th trigger, the 4th multichannel
Selector and the 5th trigger；Second trigger, the third trigger, the 4th trigger and the described 5th
The output end of trigger is connected to the first data input pin of the data register.
First shift register is made of multiple triggers and multiple selector, can be triggered by described second
The output end synchronization of device, the third trigger, the 4th trigger and the 5th trigger exports data to institute
Data register is stated, transfer efficiency is improved.
In one embodiment, second trigger, the third trigger, the 4th trigger and described
The input end of clock of five triggers is connected to control clock.
By connecting unified control clock, second trigger, the third trigger, the 4th trigger with
And the 5th trigger reaches synchronization, and the effect of shift register is played with multiple selector cooperation.
In one embodiment, second shift register includes sequentially connected 6th trigger, the choosing of the 5th multichannel
Select device, the 7th trigger, the 6th multiple selector, the 8th trigger, the 7th multiple selector, the 9th trigger, the 8th multichannel
Selector and the tenth trigger；7th trigger, the 8th trigger, the 9th trigger and the described tenth
The output end of trigger is connected to the first data input pin of the data register.
Second shift register is made of multiple triggers and multiple selector, can pass through the 7th triggering
The output end synchronization of device, the 8th trigger, the 9th trigger and the tenth trigger exports data to institute
Data register is stated, transfer efficiency is improved.
In one embodiment, the 7th trigger, the 8th trigger, the 9th trigger and described
The input end of clock of ten triggers is connected to control clock.
By connecting unified control clock, the 7th trigger, the 8th trigger, the 9th trigger with
And the tenth trigger reaches synchronization, and the effect of shift register is played with multiple selector cooperation.
In order to better understand and implement, according to the present invention will be described in detail below with reference to the accompanying drawings.
Detailed description of the invention
Fig. 1 is the circuit theory schematic diagram of traditional mipi communication interface circuit；
Fig. 2 is the circuit theory schematic diagram of the mipi communication interface circuit of the utility model.
Specific embodiment
Referring to Fig. 2, Fig. 2 is the circuit theory schematic diagram of the mipi communication interface circuit of the utility model.This is practical new
The mipi communication interface circuit of type includes the first analog-digital converter 11, the second analog-digital converter 12, the first shift register 13, the
Two shift registers 14, data register 15, Clock dividers 16 and mipi protocol sensing circuitry 17；
First analog-digital converter 11 is connected to the data register after passing sequentially through first shift register 13
First data input pin of device 15；
Second analog-digital converter 12 is connected to the data register after passing sequentially through second shift register 14
Second data input pin of device 15；
The output end of the Clock dividers 16 is respectively connected to input end of clock and the institute of the data register 15
State the input end of clock of mipi protocol sensing circuitry 17；
The output end of the data register 15 is connected to the data input pin of the mipi protocol sensing circuitry 17.
The mipi communication interface circuit is by posting data register setting in the first shift register and the second displacement
The output end of storage is controlled by the frequency-dividing clock that the Clock dividers export, and the differential data of input is converted to speed
The lower output data of rate, then exported after carrying out matching Character decoder judgement by the mipi protocol sensing circuitry.Therefore, institute
The data processing speed for stating mipi protocol sensing circuitry can reduce under the frequency-dividing clock control that the Clock dividers export, and subtract
The calorific value of few mipi protocol sensing circuitry, reduces power consumption, and improve processing speed.
Data in first, second shift register can successively move to right by turn under shift pulse effect, usually
It is to be combined to constitute by the trigger with store function.Trigger can store a binary code, store the position N two
The register of carry system code need to be constituted with N number of trigger.
The Clock dividers 16 are the frequency of input signal with becoming into multiple lower than the output signal of input frequency.It can
It is realized using traditional approach such as counters.Its principle is：Using the signal of input as pulse is counted, due to the output of counter
Port is output pulse according to certain rules, so to the signal pulse of different port output, so that it may regard as to input
The frequency dividing of signal.Crossover frequency is determined by the counter selected.It is ten frequency dividings if it is metric counter, if it is
Binary counter is two divided-frequency, and the quaternary, octal system, hexadecimal etc. also can be used, with specific reference to the mipi
The processing speed of protocol sensing circuitry 17 is set.
The mipi protocol sensing circuitry 17 can be judged by the matching Character decoder of the various mipi agreements of the prior art
Circuit composition, the various mipi decoding chips that the prior art can also be used realize, the not output data if decoding failure.
In one embodiment, the input terminal of the Clock dividers 16 and first, second shift register
Clock enters end, is respectively connected to control clock.
First, second shift register exports after carrying out data sampling according to the control clock of input to the data
Register 15, the 16 input control clock of Clock dividers, and when the control clock is converted to frequency lower frequency dividing
Clock is exported makes the data of the data register 15 synchronous with clock to the data register 15, reaches optimization process effect.
In one embodiment, the control clock can be system clock.
In one embodiment, first shift register 13 is by multiple triggers 131 and multiple multiple selector 132
Composition.It includes sequentially connected first trigger, the first multiple selector, the second trigger, the second multiple selector, third
Trigger, third multiple selector, the 4th trigger, the 4th multiple selector and the 5th trigger (not indicating)；It is described
Second trigger, the third trigger, the 4th trigger and the 5th trigger output end be connected to it is described
First data input pin of data register.
First shift register 13 is made of multiple triggers 131 and multiple selector 132, can be by described
Second trigger, the third trigger, the output end of the 4th trigger and the 5th trigger are synchronous by data
Output improves transfer efficiency to the data register 15.
The trigger can store a binary code.The shift register stores N binary codes, needs to use
The N number of above trigger is constituted.
Multiple selector, that is, the data selector.In multichannel data transmit process, will can wherein it appoint as needed
The circuit that meaning is elected all the way, also referred to as variable connector.
In one embodiment, second trigger, the third trigger, the 4th trigger and described
The input end of clock of five triggers is connected to control clock.
By connecting unified control clock, second trigger, the third trigger, the 4th trigger with
And the 5th trigger reaches synchronization, and the effect of shift register is played with multiple selector cooperation.
In one embodiment, second shift register 14 is by multiple triggers 141 and multiple multiple selector 142
Composition.It includes sequentially connected 6th trigger, the 5th multiple selector, the 7th trigger, the 6th multiple selector, the 8th
Trigger, the 7th multiple selector, the 9th trigger, the 8th multiple selector and the tenth trigger (not indicating)；It is described
7th trigger, the 8th trigger, the 9th trigger and the tenth trigger output end be connected to it is described
First data input pin of data register.
Second shift register 14 is made of multiple triggers 141 and multiple selector 142, can be by described
7th trigger, the 8th trigger, the output end of the 9th trigger and the tenth trigger are synchronous by data
Output improves transfer efficiency to the data register.
In one embodiment, the 7th trigger, the 8th trigger, the 9th trigger and described
The input end of clock of ten triggers is connected to control clock.
By connecting unified control clock, the 7th trigger, the 8th trigger, the 9th trigger with
And the tenth trigger reaches synchronization, and the effect of shift register is played with multiple selector cooperation.
Above-described embodiments merely represent several embodiments of the utility model, the description thereof is more specific and detailed,
But it cannot be understood as the limitations to utility model patent range.It should be pointed out that for the common skill of this field
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
The protection scope of the utility model.
Claims (6)
1. a kind of mipi communication interface circuit, which is characterized in that including the first analog-digital converter, the second analog-digital converter, first
Shift register, the second shift register, data register, Clock dividers and mipi protocol sensing circuitry；
First analog-digital converter is connected to the first of the data register after passing sequentially through first shift register
Data input pin；
Second analog-digital converter is connected to the second of the data register after passing sequentially through second shift register
Data input pin；
The output end of the Clock dividers is respectively connected to input end of clock and the mipi association of the data register
Discuss the input end of clock of detection circuit；
The output end of the data register is connected to the data input pin of the mipi protocol sensing circuitry.
2. mipi communication interface circuit according to claim 1, which is characterized in that the input terminal of the Clock dividers with
And the input end of clock of first, second shift register, it is respectively connected to control clock.
3. mipi communication interface circuit according to claim 1 or 2, which is characterized in that first shift register
Including sequentially connected first trigger, the first multiple selector, the second trigger, the second multiple selector, third trigger,
Third multiple selector, the 4th trigger, the 4th multiple selector and the 5th trigger；Second trigger, described
The output end of three triggers, the 4th trigger and the 5th trigger is connected to the first number of the data register
According to input terminal.
4. mipi communication interface circuit according to claim 3, which is characterized in that second trigger, the third
The input end of clock of trigger, the 4th trigger and the 5th trigger is connected to control clock.
5. mipi communication interface circuit according to claim 1 or 2, which is characterized in that second shift register
Including sequentially connected 6th trigger, the 5th multiple selector, the 7th trigger, the 6th multiple selector, the 8th trigger,
7th multiple selector, the 9th trigger, the 8th multiple selector and the tenth trigger；7th trigger, described
The output end of eight triggers, the 9th trigger and the tenth trigger is connected to the first number of the data register
According to input terminal.
6. mipi communication interface circuit according to claim 5, which is characterized in that the 7th trigger, the described 8th
The input end of clock of trigger, the 9th trigger and the tenth trigger is connected to control clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820322062.8U CN208110589U (en) | 2018-03-08 | 2018-03-08 | mipi communication interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820322062.8U CN208110589U (en) | 2018-03-08 | 2018-03-08 | mipi communication interface circuit |
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| CN208110589U true CN208110589U (en) | 2018-11-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110300221A (en) * | 2019-05-20 | 2019-10-01 | 努比亚技术有限公司 | MIPI control circuit and system, circuit control and circuit system control method |
| CN113285695A (en) * | 2021-07-26 | 2021-08-20 | 浙江芯昇电子技术有限公司 | High-frequency clock phase modulation circuit and implementation method thereof |
-
2018
- 2018-03-08 CN CN201820322062.8U patent/CN208110589U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110300221A (en) * | 2019-05-20 | 2019-10-01 | 努比亚技术有限公司 | MIPI control circuit and system, circuit control and circuit system control method |
| CN113285695A (en) * | 2021-07-26 | 2021-08-20 | 浙江芯昇电子技术有限公司 | High-frequency clock phase modulation circuit and implementation method thereof |
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| TR01 | Transfer of patent right |
Effective date of registration: 20210125 Address after: 518000 District D and E, 7th Floor, Building 3, Tingwei Industrial Park, 6 Liufang Road, Xin'an Street, Baoan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN AIXIESHENG TECHNOLOGY Co.,Ltd. Address before: 523808 building 10, Zhongji Zhigu, No.1, hunanshan Road, Songshan, Dongguan City, Guangdong Province Patentee before: DONGGUAN AIXIESHENG INTELLIGENT TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518000 District D and E, 7th Floor, Building 3, Tingwei Industrial Park, 6 Liufang Road, Xin'an Street, Baoan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Aixiesheng Technology Co.,Ltd. Address before: 518000 District D and E, 7th Floor, Building 3, Tingwei Industrial Park, 6 Liufang Road, Xin'an Street, Baoan District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN AIXIESHENG TECHNOLOGY Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |