CN103633969A - Asynchronous signal transmission circuit - Google Patents

Abstract

The invention disclose an asynchronous signal transmission circuit comprising a first D-trigger, a second D-trigger, a third D-trigger, an inverter and an AND gate. A clock signal to be transmitted of a source clock domain is transmitted to a target clock domain by utilizing the first D-trigger and the second D-trigger. The clock signal to be transmitted of the source clock domain is inputted to reset ends of the three D-triggers. Then the acquired clock signal of the target clock domain is adjusted to be width of one target clock period by utilizing the third D-trigger so that an objective of signal transmission among asynchronous clock domains is achieved. Transmission of the signal between two asynchronous clock domains can be processed by the asynchronous signal transmission circuit. Besides, the asynchronous signal transmission circuit is simple in circuit realization, and meta-stability, leakage sampling and repetitive sampling problems which are liable to appear in signal transmission among the asynchronous clock domains are greatly handled simultaneously.

Description

Asynchronous signal transfer circuit

Technical field

The present invention relates to the asynchronous signal transfer circuit that between two asynchronous clock domains of a kind of processing, signal transmits.

Background technology

Signal transmission between two asynchronous clock domains, is the problem to be processed that needs in many Design of Digital Circuit, and the signal of Direct Sampling out of phase, can cause metastable state problem.And the signal of sampling different frequency, in the situation that target clock zone clock frequency is slower than source clock zone clock frequency, can causes and Lou adopt; In target clock zone clock frequency, faster than source clock zone clock frequency in the situation that, can cause heavily and adopt, the signal that signal of a source clock cycle width can many target clock cycle width of collected one-tenth, is unfavorable for processing.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of asynchronous signal transfer circuit, and circuit is realized simple, can effectively reduce between asynchronous clock domain the metastable state occurring when signal transmits, and the probability that leaks sampling and resample.

For solving the problems of the technologies described above, asynchronous signal transfer circuit of the present invention, comprising:

One first d type flip flop, its data input pin D is input logic level"1" signal fixedly;

One second d type flip flop, its data input pin D is connected with the output Q of described the first d type flip flop;

One 3d flip-flop, its data input pin D is connected with an input of door with the output Q and of described the second d type flip flop;

One reverser, its input is connected with the output Q of described 3d flip-flop, and its output is connected with another input of door with described;

The clock signal of the input end of clock input target clock zone of described the first d type flip flop, the second d type flip flop and 3d flip-flop; The reset terminal R of described the first d type flip flop, the second d type flip flop and 3d flip-flop inputs the clock signal of source clock zone to be passed;

Output described and door is exactly the output of described asynchronous signal transfer circuit, and output is delivered to a wide signal of target clock cycle of target clock zone.

The present invention utilizes two d type flip flops that source clock signal is collected in target clock zone; Wherein, source clock signal to be passed is input to the reset terminal of d type flip flop.Recycle a d type flip flop target clock zone signal previously having collected is adjusted to a target clock cycle width, thereby reach the object that signal transmits between asynchronous clock domain.

The present invention can process the transmission of signal between two asynchronous clock domains; Adopt that fairly simple circuit is goodish has processed the metastable state problem being prone to when signal between asynchronous clock domain transmits, and the problem of leaking sampling and resampling, effectively reduce the frequency of appearance.

When the present invention is specially adapted to asynchronous clock signal and need to transmits, the clock of target clock zone is not situation about always existing; Or the clock frequency of target clock zone is slower than the situation of the clock frequency of source clock zone.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Accompanying drawing is described asynchronous signal transfer circuit schematic diagram.

Embodiment

By reference to the accompanying drawings, described asynchronous signal transfer circuit comprises in the following embodiments: 3 d type flip flops, i.e. the first d type flip flop DCF1, the second d type flip flop DCF2 and 3d flip-flop DCF3; A reverser FM1, one and a door AND1.

Described the first d type flip flop DCF1, its data input pin D is input logic level"1" signal fixedly.

Described the second d type flip flop DCF2, its data input pin D is connected with the output Q of described the first d type flip flop DCF1.

Described 3d flip-flop DCF3, its data input pin D is with the output Q of described the second d type flip flop DCF2 and be connected with an input of door AND1.

Described reverser FM1, its input is connected with the output Q of described 3d flip-flop DCF2, and its output is connected with another input of door AND1 with described.

The input end of clock input of described the first d type flip flop DCF1, the second d type flip flop DCF2 and 3d flip-flop DCF3 connects the clock signal clk of target clock zone.The reset terminal R of described the first d type flip flop DCF1, the second d type flip flop DCF2 and 3d flip-flop DCF3 inputs the clock signal din of source clock zone to be passed.

Output described and door AND1 is exactly the output of described asynchronous signal transfer circuit, i.e. output is delivered to the wide signal dout of a target clock cycle of target clock zone.

The clock signal din of source clock zone to be passed is the high level signal of a source clock cycle of source clock zone.After the clock signal din of source clock zone to be passed uprises, described the first d type flip flop DCF1, the second d type flip flop DCF2 and 3d flip-flop DCF3 are reset to 0.After the clock signal din step-down of source clock zone to be passed, the reset of described the first d type flip flop DCF1, the second d type flip flop DCF2 and 3d flip-flop DCF3 is invalid, thereby these three d type flip flops according to target clock of clock zone trigger, and logical one is passed to the second d type flip flop DCF2 from the first d type flip flop DCF1 and pass to 3d flip-flop DCF3 again.

Easily there is metastable d type flip flop in the first d type flip flop DCF1, and because the probability of metastable state generation was decayed by exponential law according to the time.So passed through the first d type flip flop DCF1, while arriving the Q end of the second d type flip flop DCF2, owing to having passed through the time of 1 target clock cycle, so the probability occurring is very little.Finally, owing to being delivered to wide signal dout of target clock cycle of target clock zone only when the output Q of the second d type flip flop DCF2 is for high, and the output Q of 3d flip-flop DCF3 while being low just for high; This only has and from the first d type flip flop DCF1, has passed to the output Q of the second d type flip flop DCF2 when logical one level signal, and just can occur while also not passing to the output Q of 3d flip-flop DCF3, so be delivered to the high level that the wide signal dout of a target clock cycle of target clock zone only maintains a target clock width.Thereby realized asynchronous signal transmission, the clock signal wide source clock zone of one or more source clock cycle, has been delivered to target clock zone, and the signal of output only has a target clock cycle wide.

Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (1)

1. an asynchronous signal transfer circuit, is characterized in that, comprising:

One first d type flip flop, its data input pin D is input logic level"1" signal fixedly;

One second d type flip flop, its data input pin D is connected with the output Q of described the first d type flip flop;

One 3d flip-flop, its data input pin D is connected with an input of door with the output Q and of described the second d type flip flop;

One reverser, its input is connected with the output Q of described 3d flip-flop, and its output is connected with another input of door with described;

The clock signal of the input end of clock input target clock zone of described the first d type flip flop, the second d type flip flop and 3d flip-flop; The reset terminal R of described the first d type flip flop, the second d type flip flop and 3d flip-flop inputs the clock signal of source clock zone to be passed;

Output described and door is exactly the output of described asynchronous signal transfer circuit, and output is delivered to a wide signal of target clock cycle of target clock zone.

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