CN101299159B - Clock switch circuit - Google Patents
Clock switch circuit Download PDFInfo
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- CN101299159B CN101299159B CN2008100681642A CN200810068164A CN101299159B CN 101299159 B CN101299159 B CN 101299159B CN 2008100681642 A CN2008100681642 A CN 2008100681642A CN 200810068164 A CN200810068164 A CN 200810068164A CN 101299159 B CN101299159 B CN 101299159B
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Abstract
The invention discloses a clock commutation circuit, which resolves technical problem of producing bur and metastable state. The clock commutation circuit of the invention is composed of two reset producing circuits, two OR gates, three NOT gates, two D-flip-flops and a clock output circuit, the reset producing circuits and the NOT gates constitutes a RS latch. Compared with the prior technology, when the first clock is switched to the second clock, the gating signal of the first clock is switched off when the first clock is at a low level, meanwhile the reset outputting signal of the second RS latch is released, the gating signal of the second clock is switched-on when the second clock is at a low level, thereby avoiding the bur during the clock switch. The reset producing circuit ensures that the asynchronous reset terminal of the D-flip-flop executes the synchronization operation to the reset signal through the RS latch circuit when the clock is at a low level, thereby avoiding the production of metastable state.
Description
Technical field
The present invention relates to clock circuit, particularly a kind of circuit that two clock signals are changed.
Background technology
At present a lot of circuit application all need to carry out the switching of clock frequency, and receiving data when for example carrying out data communication needs different clock frequencies with return data, and this just need switch between the clock of different frequency.The clock switch circuit of prior art has the following disadvantages: 1, can produce burr when clock switches, the generation of burr can cause follow-up trigger to produce action to this burr, thereby the generation of the action that will lead to errors finally causes capability error; 2, metastable generation, some clock switch circuit adopts the mode of feedback that certain clock trigger output is linked to each other with the input end of another clock trigger, because the asynchronous relationship between the clock will probably cause metastable generation, thereby make circuit be in unpredictable state.The problems referred to above all will cause application circuit to be made mistakes.
Summary of the invention
The purpose of this invention is to provide a kind of clock switch circuit, the technical matters that solve is to avoid producing burr, metastable state.
The present invention is by the following technical solutions: a kind of clock switch circuit, by two reset generation circuit, two or, three not gates, two d type flip flops and clock output circuit form; First reset generation circuit, second reset generation circuit connect first d type flip flop, second d type flip flop respectively, and the Q end of two d type flip flops outputs signal to clock output circuit respectively; Second d type flip flop
End signal connects an input end, this second d type flip flop of first reset generation circuit
End signal connects the input end of second not gate, the input end of the output termination the 3rd of this second not gate or door, first d type flip flop
An input end of termination second reset generation circuit, this first d type flip flop simultaneously
End signal connects the input end of the 3rd not gate, the input end of the output termination the 4th of the 3rd not gate or door; Another input termination the 3rd of first reset generation circuit or the output terminal of door, another input termination the 4th of second reset generation circuit or the output terminal of door; The D input termination clock selection signal of described first d type flip flop, the inversion signal that the D input termination clock selection signal of second d type flip flop obtains through first not gate; The clock end of first d type flip flop and the 3rd or another input termination first clock signal of door, the clock end of second d type flip flop and the 4th or another input termination second clock signal of door.
The RS latch that first reset generation circuit of the present invention is made of first, second Sheffer stroke gate, and first or door form; The RS latch that described second reset generation circuit is made of the 3rd, the 4th Sheffer stroke gate, and second or door form.
Two d type flip flops of the present invention are the clock negative edge and trigger and be with the asynchronous reset end.
Clock output circuit of the present invention is made up of the 5th Sheffer stroke gate, the 6th Sheffer stroke gate and the 7th Sheffer stroke gate, the 5th Sheffer stroke gate connects first d type flip flop Q end, the 6th Sheffer stroke gate connects second d type flip flop Q end, and the 7th Sheffer stroke gate is carried out export target clock after the NAND operation to the 5th Sheffer stroke gate and the six or five Sheffer stroke gate output signal.
The clock end of first d type flip flop of the present invention, the 3rd or the door and input termination first clock signal of the 5th Sheffer stroke gate; The clock end of second d type flip flop, the 4th or the door and the input termination second clock signal of the 6th Sheffer stroke gate.
Two input ends of a RS latch of the present invention are respectively with the 3rd or the output terminal and second d type flip flop of door
End links to each other, and the output terminal of second Sheffer stroke gate of a RS latch and reset signal connect first or the input end of door, the asynchronous reset end of its output termination first d type flip flop.
Two input ends of the 2nd RS latch of the present invention are respectively with the 4th or the output terminal and first d type flip flop of door
End links to each other, and the output terminal of the 3rd not gate of the 2nd RS latch and reset signal connect second or the input end of door, and asynchronous reset end of its output termination second d type flip flop links to each other.
The present invention compared with prior art, adopt reset generation circuit, two or, three not gates, the clock switch circuit that two d type flip flops and clock output circuit are formed, when first clock switches to second clock, turn-off the gate-control signal of first clock during for low level at first clock, discharge the reset output signal of the 2nd RS latch simultaneously, the burr when thereby the gate-control signal that second clock is opened second clock during for low level has avoided clock to switch, reset generation circuit guaranteed d type flip flop the asynchronous reset end must be when clock is low level, reset signal to be carried out synchronous operation by the RS latch cicuit, therefore avoided metastable generation.
Description of drawings
Fig. 1 is the clock switch circuit schematic diagram of the embodiment of the invention.
Fig. 2 is the simulation waveform figure of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in further detail.Clock switch circuit of the present invention adopts the mode of asynchronous reset that clock selection signal and clock signal are carried out synchronously, according to selecting signal Sel between incoherent first clock signal C lk_a and second clock signal Clk_b, to change, export carrot-free clock output signal Clk_out, and avoided the metastable state problem to produce.
Clock switch circuit of the present invention by two reset generation circuit, two or, three not gates, two d type flip flops and clock output circuit form.As shown in Figure 1, the first reset generation circuit A, the second reset generation circuit B connect the first d type flip flop DFF1, the second d type flip flop DFF2 respectively, described two d type flip flops are the clock negative edge and trigger and be with the asynchronous reset end, and the Sel_reg that the Q end of two d type flip flops is exported respectively, Sel_n_reg signal are to clock output circuit.The second d type flip flop DFF2's
The input end of output end signal QNb to the first reset generation circuit A, simultaneously through the signal n5 to the three behind the second not gate I2 or the door OR3 input end, the first d type flip flop DFF1's
The input end of output end signal QNa to the second reset generation circuit B, simultaneously through the signal n6 to the four behind the 3rd not gate I3 or the door OR4 input end.Another input termination the 3rd of the first reset generation circuit A or the output terminal n3 signal of door OR3, another input termination the 4th of the second reset generation circuit B or the output terminal n4 signal of door OR4.
Select the D input end of signal Sel to the first d type flip flop DFF1, obtain the D input end of inversion signal Sel_n to the second d type flip flop DFF2 simultaneously through the first not gate I1; The clock end of first clock signal C lk_a to the first d type flip flop DFF1, the clock end of second clock signal Clk_b to the second d type flip flop DFF2.
The RS latch R1 that the first reset generation circuit A is made of the first Sheffer stroke gate A1, the second Sheffer stroke gate A2, and first or the door OR1 that are connected its output terminal form, the RS latch R2 that the second reset generation circuit B is made of the 3rd Sheffer stroke gate A3, the 4th Sheffer stroke gate A4, and second or the door OR2 that are connected its output terminal form.Clock output circuit is made up of the 5th Sheffer stroke gate A5, the 6th Sheffer stroke gate A6 and the 7th Sheffer stroke gate A7, the first clock signal C lk_a and second clock signal Clk_b are selected, Sheffer stroke gate A5 carries out clock Clk_a_out after gate obtains gate by signal Sel_reg to clock Clk_a, Sheffer stroke gate A6 carries out clock Clk_b_out after gate obtains gated clock by signal Sel_n_reg to clock Clk_b, and Sheffer stroke gate A7 carries out NAND operation to Clk_a_ut and Clk_b_out and obtains target clock Clk_out.
Two input ends of RS latch R1 respectively with or the door OR3 output terminal n3 signal and
The output signal QNb of end links to each other, wherein the output terminal Reset_a signal of Sheffer stroke gate A2 and reset signal Rst with or the input end of door OR1 link to each other, or the output terminal Rst_a of an OR1 links to each other with the asynchronous reset end of d type flip flop DFF1.Two input ends of RS latch R2 respectively with or the door OR4 output terminal n4 signal and
The output signal end QNa of end links to each other, wherein the output terminal Reset_b signal of Sheffer stroke gate A3 and reset signal Rst with or the input end of door OR2 link to each other, or the output terminal Rst_b of an OR2 links to each other with the asynchronous reset end of d type flip flop DFF2.
Reset generation circuit A and B are respectively applied for the asynchronous reset signal that produces DFF1, DFF2, guarantee when selection signal Sel overturns, will at first produce any one clock signal and not allow moment of exporting; Or door OR3 is used for preventing that Clk_a and QNb from the vibration that saltus step causes RS latch R1 to take place taking place simultaneously, or door OR4 is used for preventing that Clk_b and QNa from the vibration that saltus step causes RS latch R2 to take place taking place simultaneously; Not gate I1, I2 and I3 are respectively applied for the inversion signal that signal Sel, QNb and QNa are provided; Two d type flip flops are used to deposit clock selection signal Sel and Sel_n; Clock output circuit is selected two-way clock signal C lk_a and Clk_b, the export target clock.
Reset generation circuit A produces the asynchronous reset signal of DFF1 according to the value of the output terminal QNb of clock signal C lk_a and DFF2; Reset generation circuit B produces the asynchronous reset signal of DFF2 according to the value of the output terminal QNa of clock signal C lk_b and DFF1; The inversion signal output terminal QNb of d type flip flop DFF2 is linked to each other with the input of reset generation circuit A, the asynchronous reset end Rst_a of the effective seasonal d type flip flop DFF1 of selection signal Sel_n_reg that makes at Clk_b is effective, and then makes the selection signal Sel_reg pressure of Clk_a invalid; The inversion signal output terminal QNa of d type flip flop DFF1 is linked to each other with the input of reset generation circuit B, the asynchronous reset end Rst_b of the effective seasonal d type flip flop DFF2 of selection signal Sel_reg that makes at Clk_a is effective, and then makes the selection signal Sel_n_reg pressure of Clk_b invalid;
Or door OR3 is used for preventing that Clk_a and QNb from the vibration that saltus step causes RS latch R1 to take place taking place simultaneously, or door OR4 is used for preventing that Clk_b and QNa from the vibration that saltus step causes RS latch R2 to take place taking place simultaneously.
Clock output circuit is selected export target clock Clk_out according to the value of selecting signal Sel_reg and Sel_n_reg to clock signal C lk_a and Clk_b.
As shown in Figure 2, at T1 constantly, selecting signal Sel is 0, and entire circuit is in steady state (SS), and target clock is selected clock signal C lk_b.
At T2 constantly, select signal Sel to become 1 by 0, also by any one clock signal do not sampled owing to this signal this moment, so other signal of circuit does not change.
At T3 constantly, promptly after the negative edge of Clk_b, the selection signal Sel_n_reg of Clk_b becomes 0, and this moment is because Clk_a is a high level, so the asynchronous reset end of DFF1 still be high, and exporting Sel_reg still is 0.
At T4 constantly, promptly Clk_a by hypermutation for after low, through or the delay of door OR1 and OR3 add the asynchronous reset end step-down of DFF1 after the delay of RS latch R1, this moment, DFF1 can wait for the negative edge sampling Sel signal of Clk_a.
At T5 constantly, be after the negative edge of Clk_a, DFF1 samples the Sel signal, the selection signal Sel_reg of clock signal C lk_a is uprised, target clock is selected clock signal C lk_a, at T3～T5 during this period of time, the selection signal Sel_reg and the Sel_n_reg of two clock signals are 0, and target clock remains 0.
At T6 constantly, select signal Sel to become 0 by 1, also by any one clock signal do not sampled owing to this signal this moment, so other signal of circuit does not change.
At T7 constantly, promptly after the negative edge of Clk_a, the selection signal Sel_reg of Clk_a becomes 0, and therefore will cause the asynchronous reset end of DFF2 become 0 because Clk_b is a low level this moment.
At T8 constantly, promptly T7 constantly after again through or the delay of door OR4 and OR2 add moment after the delay of RS latch R2, the asynchronous reset end of DFF2 becomes 0.
At T9 constantly, it is the negative edge of the Clk_a of T8 after the moment, DFF2 samples the Sel_n signal, the selection signal Sel_n_reg of clock signal C lk_b is uprised, target clock is selected clock signal C lk_b, at T7～T9 during this period of time, the selection signal Sel_reg and the Sel_n_reg of two clock signals are 0, and target clock remains 0.
Clock switch circuit of the present invention has solved Burr Problem and metastable state problem in the general clock switch circuit by reset generation circuit, realized the seamless switching between the uncorrelated clock: 1, the elimination of burr: when clock Clk_a (or Clk_b) switches to clock Clk b (or Clk_a), when Clk_a (or Clk_b) is low level, DFF1 (DFF2) turn-offs the gate-control signal of Clk_a (or Clk_b), discharge the reset output signal Reset_b (or Reset_a) of RS latch R2 (R1) simultaneously, Clk_b (or Clk_a) open Clk_b (or Clk_a) during for low level thus the burr of gate-control signal when having avoided clock to switch; 2, metastable solution: reset generation circuit has guaranteed that the release of the asynchronous reset end of d type flip flop carries out synchronous operation by the RS latch cicuit to reset signal when clock is low level, has therefore avoided metastable generation.
Claims (7)
1. clock switch circuit is characterized in that: described clock switch circuit by two reset generation circuit, two or, three not gates, two d type flip flops and clock output circuit form; First reset generation circuit, second reset generation circuit connect first d type flip flop, second d type flip flop respectively, and the Q end of two d type flip flops outputs signal to clock output circuit respectively; Second d type flip flop
End signal connects an input end, this second d type flip flop of first reset generation circuit
End signal connects the input end of second not gate, the input end of the output termination the 3rd of this second not gate or door, first d type flip flop
An input end of termination second reset generation circuit, this first d type flip flop simultaneously
End signal connects the input end of the 3rd not gate, the input end of the output termination the 4th of the 3rd not gate or door; Another input termination the 3rd of first reset generation circuit or the output terminal of door, another input termination the 4th of second reset generation circuit or the output terminal of door; The D input termination clock selection signal of described first d type flip flop, the inversion signal that the D input termination clock selection signal of second d type flip flop obtains through first not gate; The clock end of first d type flip flop and the 3rd or another input termination first clock signal of door, the clock end of second d type flip flop and the 4th or another input termination second clock signal of door.
2. clock switch circuit according to claim 1 is characterized in that: the RS latch that described first reset generation circuit is made of first, second Sheffer stroke gate, and first or door form; The RS latch that described second reset generation circuit is made of the 3rd, the 4th Sheffer stroke gate, and second or door form.
3. clock switch circuit according to claim 2 is characterized in that: described two d type flip flops are the clock negative edge and trigger and be with the asynchronous reset end.
4. clock switch circuit according to claim 3, it is characterized in that: described clock output circuit is made up of the 5th Sheffer stroke gate, the 6th Sheffer stroke gate and the 7th Sheffer stroke gate, the 5th Sheffer stroke gate connects first d type flip flop Q end, the 6th Sheffer stroke gate connects second d type flip flop Q end, and the 7th Sheffer stroke gate is carried out export target clock after the NAND operation to the 5th Sheffer stroke gate and the six or five Sheffer stroke gate output signal.
5. clock switch circuit according to claim 4 is characterized in that: the clock end of described first d type flip flop, the 3rd or the door and input termination first clock signal of the 5th Sheffer stroke gate; The clock end of second d type flip flop, the 4th or the door and the input termination second clock signal of the 6th Sheffer stroke gate.
6. clock switch circuit according to claim 2 is characterized in that: two input ends of a described RS latch are respectively with the 3rd or the output terminal and second d type flip flop of door
End links to each other, and the output terminal of second Sheffer stroke gate of a RS latch and reset signal connect first or the input end of door, the asynchronous reset end of its output termination first d type flip flop.
7. clock switch circuit according to claim 2 is characterized in that: two input ends of described the 2nd RS latch are respectively with the 4th or the output terminal and first d type flip flop of door
End links to each other, and the output terminal of the 3rd not gate of the 2nd RS latch and reset signal connect second or the input end of door, and asynchronous reset end of its output termination second d type flip flop links to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100681642A CN101299159B (en) | 2008-07-01 | 2008-07-01 | Clock switch circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100681642A CN101299159B (en) | 2008-07-01 | 2008-07-01 | Clock switch circuit |
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| CN101299159A CN101299159A (en) | 2008-11-05 |
| CN101299159B true CN101299159B (en) | 2010-06-09 |
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| CN2008100681642A Expired - Fee Related CN101299159B (en) | 2008-07-01 | 2008-07-01 | Clock switch circuit |
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| CN102012717B (en) * | 2010-11-16 | 2012-10-03 | 青岛海信信芯科技有限公司 | Clock switching method and device |
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| CN102201802A (en) * | 2011-03-28 | 2011-09-28 | 东南大学 | Timing sequence optimization method of anti-burr clock selector and circuit thereof |
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| CN103631318B (en) * | 2012-08-20 | 2017-07-04 | 上海华虹集成电路有限责任公司 | burr-free clock switching circuit |
| US9207704B2 (en) * | 2012-10-26 | 2015-12-08 | Silicon Laboratories, Inc. | Glitchless clock switching that handles stopped clocks |
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| DE102014212288A1 (en) * | 2014-06-26 | 2015-12-31 | Dr. Johannes Heidenhain Gmbh | Device and method for generating a trigger signal in a position measuring device and position measuring device for this purpose |
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| CN109283966B (en) * | 2018-08-17 | 2020-11-10 | 维沃移动通信有限公司 | Clock circuit and terminal |
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| CN111262562B (en) * | 2020-03-02 | 2021-08-27 | 上海交通大学 | Metastable state detection circuit |
| CN111399588B (en) * | 2020-03-18 | 2021-09-21 | 深圳市紫光同创电子有限公司 | Clock signal generation circuit, driving method and electronic device |
| CN113676163B (en) * | 2021-07-14 | 2023-04-07 | 芯华章科技股份有限公司 | Circuit for eliminating burr |
| CN113985960B (en) * | 2021-11-05 | 2023-12-15 | 普冉半导体(上海)股份有限公司 | System clock burr-free switching circuit and reset implementation method thereof |
| CN117200765B (en) * | 2023-11-06 | 2024-01-23 | 灿芯半导体(成都)有限公司 | Clock selection circuit capable of eliminating burrs |
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