CN102427363B - Multiphase multimode frequency-dividing circuit with small frequency coefficient - Google Patents
Multiphase multimode frequency-dividing circuit with small frequency coefficient Download PDFInfo
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- CN102427363B CN102427363B CN201110440805.4A CN201110440805A CN102427363B CN 102427363 B CN102427363 B CN 102427363B CN 201110440805 A CN201110440805 A CN 201110440805A CN 102427363 B CN102427363 B CN 102427363B
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Abstract
The invention discloses a multiphase multimode frequency-dividing circuit with a small frequency coefficient, comprising two control ends and four D triggers, wherein the NAND logical signals of the output signals of the third D trigger D3 and the fourth D trigger D4 are served as the input signals at D terminal of the first D trigger D1; the NAND logical signals of the control signal of the first control end and the output signal of the third D trigger D3, and the AND logical signal of the output signal of the first D trigger D1 are served as the input signals at the D terminal of the second D trigger D2; the output signal of the second D trigger D2 is served as the input signal at the D terminal of the third D trigger D3; the NOT logical signal of the output signal of the third D trigger D3 and the NAND logical signal of the control signal of the second control end are served as the input signal at the D terminal of the fourth D trigger D4; and the output signal of the first D trigger D1 is served as the output signal of the multiphase multimode frequency-dividing circuit.
Description
Technical field
The present invention relates to a kind of frequency dividing circuit, the multiphase multimode frequency dividing circuit of a kind of little divide ratio of special design.
Background technology
Clock exhibition frequently technology is a kind of important way of reduction system EMI (electromagnetic interference), and the divide ratio of the frequency dividing circuit usually adopted at present is higher, from tens to several thousand not etc.Also low system EMI is required in TFT-LCD (TFT-LCD display screen) display system, except the mode adopting system, time schedule controller (TCON) chip having exhibition frequency function is utilized in TFT-LCD display system to be also a kind of important solutions.But in this application system, the divide ratio of clock multiplier system very low is a special system requirements, this proposes new requirement to the clock multiplier system of band exhibition frequency function.For clock multiplier system, require that frequency dividing circuit wherein meets following two requirements: one is that frequency dividing circuit must switch to dynamic in 3 kinds of frequency dividing ratios, and insensitive to the sequential of switching signal; Two is that the operating frequency of frequency dividing circuit is as far as possible high, so the structure of frequency dividing circuit should be tried one's best simply, feedback path is as far as possible short.
Summary of the invention
In order to solve the problems referred to above of prior art, the object of this invention is to provide a kind of multiphase multimode frequency dividing circuit of little divide ratio, to switch in 3 kinds of frequency dividing ratios with making frequency dividing circuit dynamic, and also insensitive to the sequential of switching signal.
To achieve these goals, the invention provides a kind of multiphase multimode frequency dividing circuit of little divide ratio, described multiphase multimode frequency dividing circuit comprises two control ends and four d type flip flops, wherein,
The input signal that the NAND logical signal of the output signal of the output signal of the 3rd d type flip flop D3 and the 4th d type flip flop D4 is held as the D of first d type flip flop D1;
The input signal that the "AND" logical signal of the control signal of first control end and the NAND logical signal of output signal of described 3rd d type flip flop D3 and the output signal of described first d type flip flop D1 is held as the D of second d type flip flop D2;
The input signal that the output signal of described second d type flip flop D2 is held as the D of described 3rd d type flip flop D3;
The input signal that " non-" logical signal of output signal of described 3rd d type flip flop D3 and the NAND logical signal of the control signal of second control end are held as the D of described 4th d type flip flop D4;
The output signal of described first d type flip flop D1 is as the output signal of described multiphase multimode frequency dividing circuit.
As preferably, the output of described 3rd d type flip flop D3 connects one in two inputs of first NAND gate, the output of the 4th d type flip flop D4 connect in two inputs of first NAND gate another, the output of this first NAND gate connects the input of the D end of described first d type flip flop D1; The output of described 3rd d type flip flop D3 is connected two inputs of second NAND gate with described first control end, the output of this second NAND gate connect one with in two inputs of door, the output of described first d type flip flop D1 connect in two inputs of this and door another, the input that the D that should be connected described second d type flip flop D2 with the output of door holds; The output of described second d type flip flop D2 connects the input of the D end of described 3rd d type flip flop D3; The output of described 3rd d type flip flop D3 connects the input of an inverter, the output of this inverter connects one in two inputs of the 3rd NAND gate, described second control end connect in two inputs of the 3rd NAND gate another, the output of the 3rd NAND gate connects the input of the D end of described 4th d type flip flop D4.
As preferably, what be connected with the input that the D of described second d type flip flop D2 holds is integrated in described second d type flip flop D2 with door.
As preferably, when the control signal of described first control end is 0, the control signal of described second control end is 0 or 1; When the control signal of described first control end is 1, the control signal of described second control end is 0.
Compared with prior art, the present invention has following beneficial effect: the multiphase multimode frequency dividing circuit of little divide ratio provided by the invention can dynamically except 5/ except 6/ and except 7 these 3 kinds of frequency dividing ratios in switch, and insensitive to the sequential of switch-over control signal; By the improvement to circuit specific implementation, make the structure of frequency dividing circuit simple, feedback path is short, improves the operating frequency of frequency dividing circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of multiphase multimode frequency dividing circuit of the present invention.
Fig. 2 works as k1=0, structural representation during k2=0 for the multiphase multimode frequency dividing circuit shown in Fig. 1.
Fig. 3 works as k1=0, structural representation during k2=1 for the multiphase multimode frequency dividing circuit shown in Fig. 1.
Fig. 4 is the structural representation of the multiphase multimode frequency dividing circuit shown in Fig. 1 as k2=0.
Fig. 5 in the multiphase multimode frequency dividing circuit shown in Fig. 1 with a kind of implementation of door and second d type flip flop D2.
Fig. 6 in the multiphase multimode frequency dividing circuit shown in Fig. 1 with the another kind of implementation of door and second d type flip flop D2.
Embodiment
Below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Embodiment one:
Fig. 1 is the structural representation of multiphase multimode frequency dividing circuit of the present invention.As shown in Figure 1, multiphase multimode frequency dividing circuit of the present invention comprises two control ends and four d type flip flops, wherein,
The input signal that the output signal Q3 of the 3rd d type flip flop D3 and a 4th d type flip flop D4, the NAND logical signal of Q4 are held as the D of first d type flip flop D1;
The input signal that the NAND logical signal of output signal Q3 of control signal k1 and a 3rd d type flip flop D3 of first control end and the logical AND of the output signal Q1 of first d type flip flop D1 are held as the D of second d type flip flop D2;
The input signal that the output signal Q2 of second d type flip flop D2 holds as the D of the 3rd d type flip flop D3;
The input signal that the NAND logical signal of the logic NOT of the output signal Q3 of the 3rd d type flip flop D3 and the control signal k2 of second control end is held as the D of the 4th d type flip flop D4;
The output signal Q1 of first d type flip flop D1 is as the output signal Out of described multiphase multimode frequency dividing circuit.
In the present embodiment, the 3rd d type flip flop D3 is connected two inputs of first NAND gate with the output of the 4th d type flip flop D4, and the output of this first NAND gate connects the input of the D end of first d type flip flop D1; The output of the 3rd d type flip flop D3 is connected two inputs of second NAND gate with first control end, the output of this second NAND gate be connected with the output of first d type flip flop D1 one with two inputs of door, the input that the D that should be connected second d type flip flop D2 with the output of door holds; The output of second d type flip flop D2 connects the input of the D end of the 3rd d type flip flop D3; The output of the 3rd d type flip flop D3 connects the input of an inverter, the output of this inverter is connected two inputs of the 3rd NAND gate with second control end, the output of the 3rd NAND gate connects the input of the D end of the 4th d type flip flop D4.
Fig. 2 works as k1=0, structural representation during k2=0 for the multiphase multimode frequency dividing circuit shown in Fig. 1.As shown in Figure 2, work as k1=0, during k2=0, multiphase multimode frequency dividing circuit of the present invention can realize the function except 6, and wherein the output signal Q4 of the 4th d type flip flop D4 is constantly equal to 1, and the output signal Q1 of other three d type flip flops, the conversion process of Q2, Q3 are:
Fig. 3 works as k1=0, structural representation during k2=1 for the multiphase multimode frequency dividing circuit shown in Fig. 1.As shown in Figure 3, work as k1=0, during k2=1, multiphase multimode frequency dividing circuit of the present invention can realize the function except 7, and the output signal Q1 of four d type flip flops, the conversion process of Q2, Q3, Q4 are:
Fig. 4 is the structural representation of the multiphase multimode frequency dividing circuit shown in Fig. 1 as k2=0.As shown in Figure 4, as k2=0, by regulate k1, can realize respectively except 5 and except 6 function; As k1=0, its circuit structure is identical with the circuit structure in Fig. 2, can realize the function except 6; As k1=1, can realize the function except 5, wherein the output signal Q4 of the 4th d type flip flop D4 is constantly equal to 1, and the output signal Q1 of other three d type flip flops, the conversion process of Q2, Q3 are:
Can be found out by above-mentioned analysis, when the control signal k1 of described first control end is 0, the control letter k2 of described second control end is 0 or 1; When the control signal k1 of described first control end is 1, the control letter k2 of described second control end is 0.By arranging the control signal of two control ends, obtain different frequency dividing ratios, if the setting of frequency dividing ratio immobilizes, the multiphase multimode frequency dividing circuit that the present embodiment provides can correctly work.
Once, when frequency dividing ratio dynamic change, whether the front and back that the multiphase multimode frequency dividing circuit that the present embodiment provides is switching can normally work lower surface analysis.Table 1 lists the change situation of the output signal of each d type flip flop in the multiphase multimode frequency dividing circuit that the present embodiment provides, and the change situation below by the output signal of each d type flip flop listed by table 1 is analyzed.
Table 1
Initial using the rising edge of the output signal Q1 of first d type flip flop D1 as a dividing cycle, (state number=2) is first beat of dividing cycle so No. 2 states, for except 5/ except 6/ except 7 these 3 patterns are not always the case.
First compare except 5 with except 6 two patterns.The first count of these two patterns, the situation of the output signal of second count and third shot (i.e. state number=2,3,4) each d type flip flop is completely the same.Therefore, as long as before third shot (i.e. state number=4) terminates, determine except 5/ except 6 control signal, namely determine the value of k1 and k2, just can realize correct in 5 and the frequency division that removes under 6 two patterns.In other words, except 5/ except the effective time of the control signal of 6 terminates to current dividing cycle from the 4th bat, and to remain unchanged within effective time.
Then compare except 6 with except 7 two patterns.The first count of these two patterns, except Q4, output signal Q1, Q2 with Q3 of other three d type flip flops are all identical for second count and third shot (i.e. state number=2,3,4).Wherein, in first count and second count (i.e. state number=2,3), because the output signal Q3 of the 3rd d type flip flop D3 equals 0, so no matter the value of the output signal Q4 of the 4th d type flip flop D4 is 0 or 1, do not affect the input signal of first d type flip flop D1, the input signal of first d type flip flop D1 is constantly equal to 1.Therefore, as long as before second count (i.e. state number=3) terminates, determine except 6/ except 7 control signal, namely determine the value of k1 and k2, just can realize correct in 6 and the frequency division that removes under 7 two patterns.In other words, except 6/ except the effective time of the control signal of 7 terminates to current dividing cycle from third shot, and to remain unchanged within effective time.Except 5 is identical with it with the situation except 7 two patterns.
In sum, the multiphase multimode frequency dividing circuit that the present embodiment provides is when meeting the following conditions, and the correct response dynamics frequency dividing ratio of energy, can normally work in the front and back switched:
1) output of described multiphase multimode frequency dividing circuit is the rising edge of the output signal Q1 of first d type flip flop D1;
2), in 2 beats exported from described multiphase multimode frequency dividing circuit, the control signal k1 of two control ends and k2 will be ready to.
Fig. 5 in the multiphase multimode frequency dividing circuit shown in Fig. 1 with a kind of implementation of door and second d type flip flop D2.As shown in Figure 5, describedly be respectively A and B with the input signal of two inputs of door, in this implementation, usual manner is all adopted to realize with door and second d type flip flop D2, signal A and signal B first carries out logical AND by described with door, and then sends into second d type flip flop D2 and sample.
Embodiment two:
The similar of the structure of the multiphase multimode frequency dividing circuit that the present embodiment provides and the multiphase multimode frequency dividing circuit of embodiment one, its difference is only improving with the specific implementation of door and second d type flip flop D2 in the multiphase multimode frequency dividing circuit shown in Fig. 1.
The multiphase multimode frequency dividing circuit that embodiment two provides also comprises two control ends and four d type flip flops, wherein,
Be integrated in second d type flip flop D2 with door, namely this input that D of second d type flip flop is held is "AND" logic, and single " D " of this "AND" logical AND holds input to compare, and all only has 1 grade, does not have extra propagation delay;
The input signal that the NAND logical signal of the output signal of the 3rd d type flip flop D3 and a 4th d type flip flop D4 is held as the D of first d type flip flop D1;
The input signal that the control signal k1 of first control end and the NAND logical signal of output signal of described 3rd d type flip flop D3 and the output signal of described first d type flip flop D1 are held as the D of described second d type flip flop D2;
The input signal that the output signal of described second d type flip flop D2 is held as the D of described 3rd d type flip flop D3;
The logic NOT of output signal of described 3rd d type flip flop D3 and the NAND logical signal of the control signal of second control end are as the input signal of the D end of the 4th d type flip flop D4 described in the;
The output signal of described first d type flip flop D1 is as the output signal of described multiphase multimode frequency dividing circuit.
Fig. 6 in the multiphase multimode frequency dividing circuit shown in Fig. 1 with the another kind of implementation of door and second d type flip flop D2.As shown in Figure 6, describedly be respectively A and B with the input signal of two inputs of door, in this implementation, the concrete circuit structure with door and second d type flip flop D2 is optimized, the input of second d type flip flop D2 has been transformed into a "AND" logic.And " D " that this "AND" logical AND is single holds input to compare, and all only has 1 grade, does not have extra propagation delay, compared with the implementation in embodiment one, the propagation delay of the implementation in the present embodiment will lack two-stage.
Above embodiment is only exemplary embodiment of the present invention, and be not used in restriction the present invention, protection scope of the present invention is defined by the claims.Those skilled in the art can in essence of the present invention and protection range, and make various amendment or equivalent replacement to the present invention, this amendment or equivalent replacement also should be considered as dropping in protection scope of the present invention.
Claims (4)
1. a multiphase multimode frequency dividing circuit for little divide ratio, is characterized in that, described multiphase multimode frequency dividing circuit comprises two control ends and four d type flip flops, wherein,
The input signal that the NAND logical signal of the output signal of the output signal of the 3rd d type flip flop D3 and the 4th d type flip flop D4 is held as the D of first d type flip flop D1;
The input signal that the "AND" logical signal of the control signal of first control end and the NAND logical signal of output signal of described 3rd d type flip flop D3 and the output signal of described first d type flip flop D1 is held as the D of second d type flip flop D2;
The input signal that the output signal of described second d type flip flop D2 is held as the D of described 3rd d type flip flop D3;
The input signal that " non-" logical signal of output signal of described 3rd d type flip flop D3 and the NAND logical signal of the control signal of second control end are held as the D of described 4th d type flip flop D4;
The output signal of described first d type flip flop D1 is as the output signal of described multiphase multimode frequency dividing circuit.
2. multiphase multimode frequency dividing circuit according to claim 1, it is characterized in that, the output of described 3rd d type flip flop D3 connects one in two inputs of first NAND gate, the output of the 4th d type flip flop D4 connect in two inputs of first NAND gate another, the output of this first NAND gate connects the input of the D end of described first d type flip flop D1; The output of described 3rd d type flip flop D3 is connected two inputs of second NAND gate with described first control end, the output of this second NAND gate connect one with in two inputs of door, the output of described first d type flip flop D1 connect in two inputs of this and door another, the input that the D that should be connected described second d type flip flop D2 with the output of door holds; The output of described second d type flip flop D2 connects the input of the D end of described 3rd d type flip flop D3; The output of described 3rd d type flip flop D3 connects the input of an inverter, the output of this inverter connects one in two inputs of the 3rd NAND gate, described second control end connect in two inputs of the 3rd NAND gate another, the output of the 3rd NAND gate connects the input of the D end of described 4th d type flip flop D4.
3. multiphase multimode frequency dividing circuit according to claim 2, is characterized in that, what be connected with the input that the D of described second d type flip flop D2 holds is integrated in described second d type flip flop D2 with door.
4. according to the multiphase multimode frequency dividing circuit one of claims 1 to 3 Suo Shu, it is characterized in that, when the control signal of described first control end is 0, the control signal of described second control end is 0 or 1; When the control signal of described first control end is 1, the control signal of described second control end is 0.
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| US8981822B2 (en) * | 2012-09-14 | 2015-03-17 | Intel Corporation | High speed dual modulus divider |
| CN109217867A (en) * | 2017-07-07 | 2019-01-15 | 安徽爱科森齐微电子科技有限公司 | A kind of arbitrary integer frequency divider |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US4606059A (en) * | 1983-03-31 | 1986-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Variable frequency divider |
| CN1387322A (en) * | 2001-05-18 | 2002-12-25 | 松下电器产业株式会社 | Odd factor frequency divider and 90 deg. phase splitter operated based on output signal of frequency divider |
| US20050179475A1 (en) * | 2004-01-20 | 2005-08-18 | Thales | Frequency divider |
| US20090212833A1 (en) * | 2008-02-25 | 2009-08-27 | Nec Electronics Corporation | Frequency divider circuit |
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| CN202503497U (en) * | 2011-12-23 | 2012-10-24 | 上海贝岭股份有限公司 | Multiphase multimode frequency dividing circuit with small frequency coefficient |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4606059A (en) * | 1983-03-31 | 1986-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Variable frequency divider |
| CN1387322A (en) * | 2001-05-18 | 2002-12-25 | 松下电器产业株式会社 | Odd factor frequency divider and 90 deg. phase splitter operated based on output signal of frequency divider |
| US20050179475A1 (en) * | 2004-01-20 | 2005-08-18 | Thales | Frequency divider |
| US20090212833A1 (en) * | 2008-02-25 | 2009-08-27 | Nec Electronics Corporation | Frequency divider circuit |
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