CN111835339A

CN111835339A - Frequency division unit and multi-mode frequency divider

Info

Publication number: CN111835339A
Application number: CN202010705884.6A
Authority: CN
Inventors: 黄耀; 杨海玲; 金毓奇; 王亚宁; 连夏梦
Original assignee: Shanghai IC R&D Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2020-10-27

Abstract

The invention provides a frequency division unit and a multi-mode frequency divider, wherein the frequency division unit comprises a first latch, a second latch, a first trigger, a first NAND gate, a second NAND gate, a third NAND gate, a first inverter and a second inverter; the first latch is provided with a positive phase input end for receiving a frequency division input signal, and when the frequency division input signal is a low level signal, the first latch is conducted, and the positive phase output end of the first latch starts to output the signal received by the signal input end of the first latch and outputs the signal through the first inverter to form a carry output signal. The multi-mode frequency divider formed by the frequency dividing unit provided by the invention has the advantages of higher frequency dividing accuracy and frequency dividing efficiency, lower power consumption, higher processing speed, smaller delay, simple structure, extremely small occupied area and higher transportability.

Description

Frequency division unit and multi-mode frequency divider

Technical Field

The present invention relates to the field of electronic circuit technologies, and in particular, to a frequency divider and a multi-mode frequency divider.

Background

The multi-modulus frequency divider is generally formed by cascading multiple stages of frequency dividing units, wherein each stage of frequency dividing unit can divide a frequency of a signal, so that an input signal can be generated into output signals with different frequencies according to multiple frequency dividing ratios by cascading the multiple stages of frequency dividing units.

Fig. 1 is a schematic structural diagram of a multi-modulus frequency divider provided in the related art, and as shown in fig. 1, the multi-modulus frequency divider includes n stages of cascaded frequency dividing units (n is a positive integer), each stage of frequency dividing unit has a positive signal input terminal CI, a positive signal output terminal CO, a carry input terminal MODIN, a carry output terminal MODOUT, and a frequency dividing control terminal P. The CI end of each stage of frequency division unit behind the first stage of frequency division unit is connected with the CO end of the previous stage of frequency division unit, and the MODIN end of each stage of frequency division unit ahead of the nth stage of frequency division unit is connected with the MODOUT end of the next stage of frequency division unit. And the carry input end MODIN of each stage of frequency dividing unit is used for receiving the carry input signal MODIN , the carry output end MODOUT is used for outputting the carry output signal MODOUT , the frequency dividing control end P is used for receiving the frequency dividing control signal P , the positive signal input end CI is used for receiving the frequency dividing input signal CI , and the positive signal output end CO is used for outputting the frequency dividing output signal CO . In addition, each stage of frequency dividing unit divides the frequency dividing input signal CI received by the CI terminal based on the carry input signal MODIN received by the MODIN terminal and the frequency dividing control signal P received by the P terminal to obtain the frequency dividing output signal CO and outputs the frequency dividing output signal CO through the CO terminal.

In the related art, each frequency dividing unit in the multi-modulus frequency divider generally adopts a dual D flip-flop or four D-latch structure, wherein fig. 2 and3 are schematic structural diagrams of the dual D flip-flop and the four D-latch in the related art, respectively, as shown in fig. 2, the dual D flip-flop structure includes a flip-flop dff (a), a flip-flop dff (b), an and gate ana, an and gate ANAb, a nand gate NANDa, and an inverter INVa. The four-D Latch structure comprises a Latch D Latch (a), a Latch D Latch (b), a Latch D Latch (c), a Latch D Latch (D), an AND gate ANDc, an AND gate ANAd, an NAND gate NANDb and an inverter INVb. However, it should be noted that, when each frequency dividing unit in the multi-modulus frequency divider adopts a four-D-latch structure, the processing speed is slow, the delay is high, and thus the frequency dividing efficiency is low, and meanwhile, the occupied area of the four-D-latch structure is large. And when each frequency dividing unit in the multi-mode frequency divider adopts a double-D trigger structure, a delay exists between the edge of the carry output signal MODOUT output by the carry output terminal MODOUT of each stage of frequency dividing unit and the rising edge of the received frequency dividing input signal CI , so that glitch signals exist in the carry output signals MODOUT output by the carry output terminals MODOUT of other stages of frequency dividing units, and the multi-mode frequency divider cannot perform correct frequency division on the signals.

Disclosure of Invention

The present invention provides a frequency dividing unit and a multi-modulus frequency divider, so as to solve the technical problems that the multi-modulus frequency divider in the related art cannot divide frequency correctly, has a slow processing speed, a high delay, a low frequency dividing efficiency, and a large occupied area.

In order to achieve the above technical problem, in a first aspect, the present invention provides a frequency dividing unit, where the frequency dividing unit includes a first latch, a second latch, a first flip-flop, a first nand gate, a second nand gate, a third nand gate, a first inverter, and a second inverter;

a first input end of the second nand gate is connected with an inverted output end of the first latch, a second input end of the second nand gate is used for receiving a frequency division control signal, and an output end of the second nand gate is connected with a signal input end of the second latch; the positive phase output end of the second latch is connected with the first input end of the first NAND gate; the second input end of the first NAND gate is connected with the output end of the second inverter, and the output end of the first NAND gate is connected with the signal input end of the first trigger; the inverted output end of the first flip-flop is connected with the input end of the second inverter and the first input end of the third nand gate, the inverted output end of the first flip-flop is used for outputting a frequency division output signal, the second input end of the third nand gate is used for receiving a carry input signal, and the output end of the third nand gate is connected with the signal input end of the first latch; the positive phase output end of the first latch is connected with the input end of the first phase inverter, and a carry output signal is output through the output end of the first phase inverter;

the first latch is provided with a positive phase input end for receiving a frequency division input signal, and when the frequency division input signal is a low level signal, the first latch is conducted, and the positive phase output end of the first latch starts to output the signal received by the signal input end of the first latch and outputs the signal through the first inverter to form a carry output signal.

Optionally, the first latch further includes a negative phase input terminal for receiving an inverted signal of the frequency-divided input signal;

the second latch is provided with a positive phase input end and a negative phase input end, and the positive phase input end of the second latch is used for receiving a frequency division input signal; the negative phase input end of the second latch is used for receiving an inverted signal of the frequency division input signal, wherein when the frequency division input signal is a high level signal, the second latch is conducted;

the first trigger is provided with a non-inverting input end and is used for receiving a frequency division input signal, wherein when the frequency division input signal changes from a low level signal to a high level signal, the first trigger is conducted.

Optionally, the first latch includes a first clocked transmission gate, a first clocked inverter, and a third inverter;

a first input end of the first clocked transmission gate is connected with an output end of the third nand gate, an output end of the first clocked transmission gate is respectively connected with an input end of the first inverter, an input end of the third inverter, and an output end of the first clocked inverter, and an output end of the third inverter is respectively connected with a first input end of the second nand gate and a first input end of the first clocked inverter;

the first clocked transmission gate is provided with a second input end and a third input end, the second input end of the first clocked transmission gate is used as a positive phase input end of the first latch and is used for receiving a frequency division input signal, and the third input end of the first clocked transmission gate is used as a negative phase input end of the first latch and is used for receiving an inverted signal of the frequency division input signal;

the first clocked inverter is provided with a second input end and a third input end, the second input end of the first clocked inverter is used as a negative phase input end of the first latch and is used for receiving an inverted signal of a frequency division input signal, and the third input end of the first clocked inverter is used as a positive phase input end of the first latch and is used for receiving the frequency division input signal;

when the frequency division input signal is a low level signal, the first clock control transmission gate is conducted; when the frequency division input signal is a high level signal, the first clocked inverter is conducted.

Optionally, the second latch includes a second clocked transmission gate, a second clocked inverter, and a fourth inverter;

a first input end of the second clocked transmission gate is connected with an output end of the second nand gate, an output end of the second clocked transmission gate is respectively connected with a first input end of the first nand gate, an input end of the fourth inverter and an output end of the second clocked inverter, and an output end of the fourth inverter is connected with a first input end of the second clocked inverter;

the second clocked transmission gate further has a second input terminal and a third input terminal, the second input terminal of the second clocked transmission gate serves as a negative phase input terminal of the second latch and is configured to receive an inverted signal of the frequency-divided input signal, and the third input terminal of the second clocked transmission gate serves as a positive phase input terminal of the second latch and is configured to receive the frequency-divided input signal;

the second clocked inverter is further provided with a second input terminal and a third input terminal, the second input terminal of the second clocked inverter is used as a positive phase input terminal of the second latch and is used for receiving the frequency division input signal, and the third input terminal of the second clocked inverter is used as a negative phase input terminal of the second latch and is used for receiving an inverted signal of the frequency division input signal;

when the frequency division input signal is a high-level signal, the second clock control transmission gate is conducted; and when the frequency division input signal is a low level signal, the second clocked inverter is conducted.

Optionally, the frequency dividing unit further includes a first differential circuit, and the first differential circuit includes a positive phase output terminal and a negative phase output terminal;

wherein the input terminal of the first differential circuit is connected to the output terminal of the second inverter to receive the frequency-divided output signal provided by the inverted output terminal of the first flip-flop through the second inverter, and output the frequency-divided output signal through the positive-phase output terminal of the first differential circuit, and output the inverted signal of the frequency-divided output signal through the negative-phase output terminal of the first differential circuit.

In a second aspect, the present invention further provides a multi-modulus frequency divider, where the multi-modulus frequency divider is formed by cascading a plurality of frequency dividing units;

the frequency dividing units of the other stages of frequency dividing units except the first stage frequency dividing unit in the multi-modulus frequency divider comprise the frequency dividing units of the first aspect;

the first-stage frequency division unit of the multi-mode frequency divider comprises a second trigger, a third trigger, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a fifth inverter and a sixth inverter;

a first input end of the fourth nand gate is connected to the inverted output end of the third flip-flop, a second input end of the fourth nand gate is used for receiving a frequency division control signal, and an output end of the fourth nand gate is connected to a first input end of the sixth nand gate; a second input end of the sixth nand gate is connected with an output end of the fifth inverter, an output end of the sixth nand gate is connected with a signal input end of a second flip-flop, an inverting output end of the second flip-flop is connected with an input end of the fifth inverter, the inverting output end of the second flip-flop is used for outputting a frequency division output signal, and the inverting output end of the second flip-flop is further connected with a first input end of the fifth nand gate; a second input end of the fifth nand gate is used for receiving a carry input signal, and an output end of the fifth nand gate is connected with an input end of the sixth inverter so as to output a carry output signal through the sixth inverter; and the output end of the fifth NAND gate is also connected with the signal input end of the third trigger.

Optionally, the second flip-flop and the third flip-flop are both provided with non-inverting input terminals for receiving a frequency-divided input signal, and when the frequency-divided input signal changes from a low-level signal to a high-level signal, the second flip-flop and the third flip-flop are turned on.

Optionally, the frequency dividing unit further includes a second differential circuit, and the second differential circuit includes a positive phase output terminal and a negative phase output terminal;

wherein the input terminal of the second differential circuit is connected to the output terminal of the fifth inverter to receive the frequency-divided output signal provided by the inverted output terminal of the second flip-flop through the fifth inverter, and output the frequency-divided output signal through the positive phase output terminal of the second differential circuit, and output the inverted signal of the frequency-divided output signal through the negative phase output terminal of the second differential circuit.

Optionally, the first-stage frequency dividing unit includes:

a positive signal input for receiving a frequency divided input signal;

a carry input terminal for receiving a carry input signal;

a carry output terminal for outputting a carry output signal;

the frequency division control end is used for receiving a frequency division control signal;

a positive signal output end for outputting a frequency division output signal, wherein the frequency division output signal is a frequency division signal corresponding to the frequency division input signal;

a negative signal output end for outputting an inverted signal of the frequency division output signal;

the positive-phase input end of the second flip-flop and the positive-phase input end of the third flip-flop in the first-stage frequency dividing unit are used as positive signal input ends of the first-stage frequency dividing unit; a second input end of the fifth nand gate is used as a carry input end of the first-stage frequency division unit; a second input end of the fourth nand gate is used as a frequency division control end of the first-stage frequency division unit; the output end of the sixth inverter is used as the carry output end of the first-stage frequency division unit; the positive phase output end of the second differential circuit is used as the positive signal output end of the first-stage frequency division unit; and the negative phase output end of the second differential circuit is used as the negative signal output end of the first-stage frequency division unit.

Optionally, the other sub-frequency dividing unit includes:

a positive signal input for receiving a frequency divided input signal;

a negative signal input terminal for receiving an inverted signal of the frequency-divided input signal;

a carry input terminal for receiving a carry input signal;

a carry output terminal for outputting a carry output signal;

the positive phase input end of the first latch, the positive phase input end of the second latch and the positive phase input end of the first flip-flop in the other fractional frequency unit are used as the positive signal input ends of the other fractional frequency unit; the negative phase input end of the first latch and the negative phase input end of the second latch are used as the negative signal input ends of the other stage frequency dividing units; a second input end of the second nand gate is used as a frequency division control end of the other frequency division unit; a second input end of the third nand gate is used as a carry input end of the other stage frequency dividing unit; the output end of the first inverter is used as the carry output end of the other stage frequency dividing unit; the positive phase output end of the first differential circuit in the other frequency dividing unit is used as the positive signal output end of the other frequency dividing unit; and the negative phase output end of the first differential circuit is used as the negative signal output end of the other frequency dividing unit.

Optionally, a positive signal input end of the first-stage frequency dividing unit is configured to receive an initial frequency-dividing input signal, a positive signal input end of each stage of frequency dividing unit after the first-stage frequency dividing unit is connected to a positive signal output end of a previous-stage frequency dividing unit, and a negative signal input end of each stage of frequency dividing unit after the first-stage frequency dividing unit is connected to a negative signal output end of the previous-stage frequency dividing unit;

and the carry input end of the last stage of frequency division unit is used for receiving an initial carry input signal, and the carry input end of each stage of frequency division unit before the last stage of frequency division unit is connected with the carry output end of the next stage of frequency division unit.

Optionally, the frequency-divided input signal comprises a clock signal.

In summary, in the frequency dividing unit and the multi-modulus frequency divider provided by the present invention, each of the frequency dividing units of the multi-modulus frequency divider, except for the first-stage frequency dividing unit, includes the frequency dividing unit provided by the present invention, that is, includes the first latch and the first inverter, and in the present invention, when the frequency-divided input signal received by the non-inverting input terminal of the first latch is a low-level signal, the first latch starts to be turned on and outputs the signal input by the signal input terminal of the first inverter, so that the first inverter inverts the signal and outputs the inverted signal as the carry output signal. Thus, in the present invention, even if there is some delay in the output of the signal from the first latch, the frequency dividing unit provided in the present invention is simply such that there is a delay between the edges (e.g., rising and falling edges) in the carry output signal it outputs and the falling edges of the frequency divided input signal it receives. Therefore, when the frequency division unit provided by the invention is used in each stage of frequency division units of the multi-mode frequency divider except for the first stage frequency division unit, no burr signal exists in the carry output signal output by each stage of frequency division unit, the multi-mode frequency divider can carry out correct frequency division on the signal, the pulse width of the output carry output signal can be ensured, the phenomenon that the pulse width of the carry output signal is narrow is avoided, and the accuracy of frequency division is further ensured.

In addition, the first-stage frequency division unit of the multi-mode frequency divider comprises the second trigger and the third trigger, the first-stage frequency division unit is of a double-D trigger structure, the processing speed is high, the efficiency is high, and in addition, because the carry output signal of the first-stage frequency division unit cannot be input into other stage frequency division units, even if the carry output signal of the first-stage frequency division unit is output incorrectly due to the double-D trigger structure, the frequency division correctness of other stage frequency division units cannot be influenced.

Therefore, the multi-mode frequency divider provided by the invention ensures the frequency dividing efficiency and the frequency dividing accuracy.

Meanwhile, the flip-flops (namely the first flip-flop, the second flip-flop and the third flip-flop) in the multi-mode frequency divider provided by the invention are all TSPC type D flip-flops, and the multi-mode frequency divider provided by the invention has the advantages of simple circuit structure, lower delay, lower power consumption and smaller occupied area, and has higher portability.

Drawings

Fig. 1 is a schematic structural diagram of a multi-modulus frequency divider provided in the related art;

fig. 2 and3 are schematic structural diagrams of a dual D flip-flop and four D latches in the related art, respectively;

FIG. 4 is a timing diagram of the received frequency-division input signal CI , the output carry output signal MODOUT , and the result of the AND operation of CI and MODOUT in FIG. 2, where DFF (b) is shown in FIG. 2;

FIG. 5 shows the timing diagram of the received frequency-division input signal CI , the output carry output signal MODOUT , and the timing diagram of the signals obtained after the AND operation of CI and MODOUT in FIG. 2;

fig. 6 is a schematic structural diagram of a frequency-division unit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a first clocked inverter INVa according to a first embodiment of the present invention;

FIG. 8 is a timing diagram of a frequency-division input signal CI , a timing diagram of a carry output signal MODOUT , and a timing diagram of a signal obtained after the AND operation of CI and MODOUT of the frequency-division unit in FIG. 6 according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a second clocked inverter INVb according to a first embodiment of the present invention;

fig. 10 is a schematic structural diagram of a first flip-flop DFF1 according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a frequency-division unit according to a second embodiment of the present invention;

fig. 12 is a schematic structural diagram of a multi-modulus frequency divider according to an embodiment of the present invention.

Reference numerals:

d Latch1 — first Latch; d Latch2 — second Latch; DFF 1-first flip-flop; NAND 1-first NAND gate; NAND 2-second NAND gate; NAND 3-third NAND gate; INV1 — first inverter; INV2 — second inverter; TG 1-first clocked transmission gate; INVa-a first clocked inverter; INV 3-third inverter; p1-first PMOS tube; p2-second PMOS tube; n1-first NMOS tube; n2-second NMOS tube; TG 2-second clocked transmission gate; INvb-a second clocked inverter; INV 4-fourth inverter; p3-third PMOS tube; p4-fourth PMOS tube; p5-fifth PMOS tube; p6-sixth PMOS tube; n3-third NMOS tube; n4-fourth NMOS tube; n5-fifth NMOS tube; n6-sixth NMOS tube; n7-seventh NMOS transistor; INV 7-seventh inverter; INV8 — eighth inverter; INV 9-ninth inverter; INV10 — tenth inverter; TG3 — third clock controlled transmission gate; DFF 2-second flip-flop; DFF 3-third flip-flop; NAND 4-fourth NAND gate; NAND 5-fifth NAND gate; NAND 6-sixth NAND gate; INV 5-fifth inverter; INV 6-sixth inverter; INV 11-eleventh inverter; INV 12-twelfth inverter; INV 13-thirteenth inverter; INV 14-fourteenth inverter; TG 4-fourth clocked transmission gate.

Detailed Description

As described in the background art, when each frequency dividing unit in the multi-mode frequency divider adopts a dual D flip-flop structure, a glitch signal is generated in the carry output signal MODOUT output by the carry output terminal MODOUT of each stage of the frequency dividing unit. The inventor researches and discovers that the reason of the occurrence of the glitch signal is mainly as follows:

referring to fig. 2, the first input terminal of the and gate andsb is configured to be the carry input terminal MODIN of the frequency dividing unit to receive the carry input signal MODIN , the positive phase output terminal Q of the dff (b) is configured to be the carry output terminal MODOUT of the frequency dividing unit to output the carry output signal MODOUT , the first input terminal of the nand gate NANDa is configured to be the frequency dividing control terminal P of the frequency dividing unit to receive the frequency dividing control signal P , the positive phase input terminals CK of the dff (a) and the dff (b) are configured to be the positive signal input terminal of the frequency dividing unit to receive the frequency dividing input signal CI , and the positive phase output terminal Q of the dff (a) is configured to be the positive signal output terminal of the frequency dividing unit to output the frequency dividing output signal CO , the frequency dividing output signal CO being a signal obtained by dividing the frequency dividing input signal CI < i. Wherein, when the frequency division input signal CI changes from a low level signal to a high level signal, dff (a) and dff (b) are turned on, and the positive signal output terminal Q of dff (a) and dff (b) outputs the signal inputted from the signal input terminal D.

Further referring to fig. 2, the and gate ands b is used for performing and processing on the frequency division output signal CO and the carry input signal MODIN , and inputting the and processed signal to the signal input terminal D of dff (b) to be output as the carry output signal MODOUT through dff (b). It should be noted, however, that dff (b) is turned on when the frequency-division input signal CI changes from a low level signal to a high level signal, wherein for the flip-flop and/or the latch, when it is turned on, the signal output by the non-inverting output terminal Q is the signal input by the signal input terminal D, when it is turned off, the non-inverting output terminal Q maintains the current output signal unchanged, and the output of the signal input by the signal input terminal D is not resumed until the next time it is turned on. It can be determined that, ideally, the time point at which the signal output by dff (b) changes should coincide with the time point at which the positive phase input terminal CK thereof acquires the rising edge of the frequency-division input signal CI , that is, ideally, the edge (for example, the falling edge or the rising edge) of the carry output signal MODOUT output by dff (b) is at the same time point as the rising edge of the frequency-division input signal CI received by the positive phase input terminal CK thereof. Fig. 4 is a timing chart of the received frequency division input signal CI , the output carry output signal MODOUT , and the timing chart of the signals obtained after the and of CI and MODOUT in fig. 2, where dff (b) is shown in fig. 2. As shown in fig. 4, the edge of the carry output signal MODOUT output by dff (b) is at the same time point as the rising edge of the frequency-division input signal CI received by dff.

However, it should be noted that, in practical cases, since it takes a certain time for a signal to pass through the flip-flop, after the signal input end of the flip-flop receives the signal, it takes a certain time for the output end of the flip-flop to start outputting the signal. This causes a delay of one D flip-flop between the edge of the carry output signal MODOUT output by dff (b) and the rising edge of the frequency-division input signal CI received by it. And, fig. 5 is a timing chart of the received frequency division input signal CI , the outputted carry output signal MODOUT , and the timing chart of the signals obtained after the and of CI and MODOUT in fig. 2, in practical cases. As shown in fig. 5, there is a delay between the edge of the carry output signal MODOUT output by dff (b) and the rising edge of the frequency-division input signal CI received by it. This causes glitches in the carry output signals MODOUT of the other stage frequency dividing cells.

Specifically, as can be seen from fig. 1 and fig. 2, the positive signal output terminal CO of each stage of frequency dividing unit after the first stage of frequency dividing unit is connected to the positive signal input terminal CI of the next stage of frequency dividing unit, and the carry input terminal MODIN of each stage of frequency dividing unit before the nth stage of frequency dividing unit is connected to the carry output terminal MODOUT of the next stage of frequency dividing unit. Therefore, the frequency division input signal CI of each stage of frequency division unit is substantially the frequency division output signal CO < i-1> of the previous stage of frequency division unit, and the carry output signal MODOUT of each stage of frequency division unit is substantially the carry input signal MODIN < i-1> of the previous stage of frequency division unit. Based on this, when there is a delay of one flip-flop between the edge of the carry output signal MODOUT output by the dff (b) of each stage of the frequency dividing unit and the rising edge of the received frequency dividing input signal CI , it is equivalent to there being a delay of one flip-flop between the edge of the carry input signal MODIN < i-1> received by each stage of the frequency dividing unit and the rising edge of the output frequency dividing output signal CO < i-1 >. At this time, referring to fig. 2, since the and gate andsb of each stage of frequency dividing unit needs to perform and processing on the received frequency division output signal CO and the carry input signal MODIN to obtain the carry output signal MODOUT of the current stage of frequency dividing unit, if there is a delay between an edge of the carry input signal MODIN and a rising edge of the frequency division output signal CO , and processing the MODIN and the CO , a glitch signal exists in the processed signal, so that a glitch signal exists in the finally obtained carry output signal MODOUT . For example, comparing fig. 4 and5, it is clear that a glitch signal F is present in the signals after the phase in fig. 5, which may make the multi-modulus divider unable to divide the signal correctly.

Therefore, in order to solve the above technical problem, the present invention provides a frequency dividing unit and a multi-modulus frequency divider. The following describes a frequency dividing unit and a multi-modulus frequency divider according to the present invention in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

In this embodiment, a frequency dividing unit is provided, and fig. 6 is a schematic structural diagram of a frequency dividing unit according to an embodiment of the present invention, as shown in fig. 6, the frequency dividing unit may include a first Latch D Latch1, a second Latch D Latch2, a first flip-flop DFF1, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first inverter INV1, and a second inverter INV 2.

The first input end of the second NAND gate NAND2 is connected to the inverting output end of the first Latch D Latch1, the second input end of the second NAND gate NAND2 serves as the frequency division control end P of the frequency division unit to receive the frequency division control signal P , and the output end of the second NAND gate NAND2 is connected to the signal input end of the second Latch D Latch 2. The non-inverting output terminal of the second Latch D Latch2 is connected to the first input terminal of the first NAND gate NAND 1. A second input end of the first NAND gate NAND1 is connected to the output end of the second inverter INV2, and an output end of the first NAND gate NAND1 is connected to the signal input end D of the first flip-flop DFF 1. An inverting output end-Q of the first flip-flop DFF1 is connected to an input end of the second inverter INV2 and a first input end of the third NAND gate NAND3, the inverting output end-Q of the first flip-flop DFF1 is used for outputting a frequency division output signal CO , a second input end of the third NAND gate NAND3 is used as a carry input end MODIN of the frequency division unit to receive a carry input signal MODIN , and an output end of the third NAND gate NAND3 is connected to a signal input end of the first Latch D Latch 1. The non-inverting output terminal of the first Latch D Latch1 is connected to the input terminal of the first inverter INV1, and outputs a carry output signal MODOUT through the output terminal of the first inverter INV 1.

The first Latch D Latch1 has a positive phase input end for receiving a frequency division input signal CI , and when the frequency division input signal CI is a low level signal, the first Latch turns on D Latch1, and the positive phase output end of the first Latch D Latch1 starts outputting a signal received by the signal input end of the first Latch D Latch1 and outputs the signal through the first inverter INV1 to form a carry output signal MODOUT .

The following describes in detail the structure of each component of the frequency dividing unit in the first embodiment:

first, as for the first Latch D Latch1, referring to fig. 6, the first Latch D Latch1 may specifically include a first clocked transmission gate TG1, a first clocked inverter INVa, and a third inverter INV 3.

The first input end of the first clocked transmission gate TG1 is used as the signal input end of the first Latch D Latch1 and is connected with the output end of the third NAND gate NAND3, the output end of the first clocked transmission gate TG1 is used as the positive phase output end of the first Latch D Latch1 and is connected with the input end of the first inverter INV1, meanwhile, the output end of the first clocked transmission gate TG1 is also connected with the input end of the third inverter INV3 and the output end of the first clocked inverter INVa, the output end of the third inverter INV3 is used as the inverse phase output end of the first Latch D Latch1 and is connected with the first input end of the second NAND gate 2, and the output end of the third inverter INV3 is also connected with the first input end of the first clocked inverter INVa.

The first clocked transmission gate TG1 further includes a second input terminal CI and a third input terminal CIB, the second input terminal CI of the first clocked transmission gate TG1 is used as a positive phase input terminal of the first Latch D Latch1 and is configured to receive a frequency-divided input signal CI , which may be a clock signal, for example, and the third input terminal CIB of the first clocked transmission gate TG1 is used as a negative phase input terminal of the first Latch D Latch1 and is configured to receive an inverted signal CIB of the frequency-divided input signal.

And, for the first clocked transmission gate TG1, when the frequency-divided input signal CI is low level, the first clocked transmission gate TG1 is turned on, and its output terminal outputs the signal inputted by its first input terminal; when the frequency-division input signal CI is high, the first clocked transmission gate TG1 is turned off.

The first clocked inverter INVa also has a second input terminal CIB for receiving an inverted signal CIB of the frequency-divided input signal as a negative input terminal of the first Latch D Latch1, and a third input terminal CI for receiving a frequency-divided input signal CI as a positive input terminal of the first Latch D Latch 1.

Specifically, fig. 7 is a schematic structural diagram of a first clocked inverter INVa according to a first embodiment of the present invention, and as shown in fig. 7, the first clocked inverter INVa may specifically include: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1 and a second NMOS transistor N2.

And, as shown in fig. 6 and 7, the gate of the first PMOS transistor P1 and the gate of the second NMOS transistor are used as the first input terminal of the first clocked inverter INVa, and are connected to the output terminal of the third NAND gate NAND3, the source of the first PMOS transistor P1 is connected to the voltage source VDD, the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the first node a, the first node a is used as the output terminal of the first clocked inverter INVa and is connected to the input terminal of the third inverter INV3, the first node a is further connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded. The grid electrode of the second PMOS tube is used as the second input end CIB of the first clocked inverter INVa and is used for receiving an inverted signal CIB of the frequency division input signal, and the grid electrode of the first NMOS tube is used as the third input end CI of the first clocked inverter INVa and is used for receiving the frequency division input signal CI .

Wherein, for the first clocked inverter INVa, when the frequency-division input signal CI is a low-level signal, the first clocked inverter INVa is turned off. When the frequency division input signal CI is a high level signal, the first clocked inverter INVa is turned off and an inversion function is implemented, and the specific principle is as follows:

when the frequency division input signal CI is at a low level, and an inverted signal CIB of the frequency division input signal is at a high level, the gate of the first NMOS transistor N1 receives a low level signal, the gate of the second PMOS transistor P2 receives a high level signal, the second PMOS transistor P2 and the first NMOS transistor N1 are both turned off, and the first clocked inverter INVa is turned off.

When the frequency division input signal CI is at a high level, and the inverted signal CIB of the frequency division input signal is at a low level, the gate of the first NMOS transistor N1 receives a high level signal, the gate of the second PMOS transistor P2 receives a low level signal, and both the second PMOS transistor P2 and the first NMOS transistor N1 are turned on. At this time, if the first input terminal of the first clocked inverter INVa (i.e., the gate of the first PMOS transistor P1 and the gate of the second NMOS transistor N2) receives a high level signal, the first PMOS transistor P1 is turned off, and the second NMOS transistor N2 is turned on, the first NMOS transistor N1 and the second NMOS transistor N2 pull down the potential of the first node a to a low level, so that the output terminal of the first clocked inverter INVa (i.e., the first node a) outputs a low level signal that is opposite to the high level signal input by the first input terminal thereof. And if the first input end of the first clocked inverter INVa receives a low level signal, the first PMOS transistor P1 is turned on, and the second NMOS transistor N2 is turned off, the first PMOS transistor P1 and the second PMOS transistor P2 pull up the potential of the first node a to a high level, so that the output end of the first clocked inverter INVa outputs a high level signal that is opposite to the low level signal input by the first input end thereof, thereby enabling the first clocked inverter INVa to realize an inverting function.

As can be seen from the above description and fig. 6, in the first embodiment, when the frequency-divided input signal CI is a low-level signal, the first clocked transmission gate TG1 in the first Latch D Latch1 is turned on, the first clocked inverter INVa is turned off, and at this time, after the signal output by the output terminal of the third NAND gate NAND3 passes through the first clocked transmission gate TG1, the signal is output to the first inverter INV1 through the non-inverting output terminal (i.e., the output terminal of the first clocked transmission gate TG 1) of the first Latch D Latch1, so that the first inverter INV1 inverts the signal output by the non-inverting output terminal of the first Latch D Latch1 and outputs the inverted signal as the carry output signal MODOUT ; meanwhile, after passing through the first clocked transmission gate TG1, the signal output from the output of the third NAND gate NAND3 is also inverted by the third inverter INV3 and output from the inverted output of the first Latch D Latch1 (i.e., the output of the third inverter INV 3). Thus, when the frequency-divided input signal CI is a low level signal, the inverted output terminal of the first Latch D Latch1 outputs the inverted signal of the signal received by the first input terminal thereof (i.e., the first input terminal of the first clocked transmission gate TG 1), and the non-inverted output terminal of the first Latch D Latch1 outputs the signal received by the first input terminal thereof.

And when the frequency-division input signal CI is low, the signal output by the output terminal of the third NAND gate NAND3 is also transmitted to the input terminal of the first clocked inverter INVa through the first clocked transmission gate TG1 and the third inverter INV3, and at this time, the signal output by the third NAND gate NAND3 is latched to the input terminal of the first clocked inverter INVa in view of the turning-off of the first clocked inverter INVa.

Next, when the frequency-divided input signal is a high-level signal, the first clocked transmission gate TG1 of the first Latch D Latch1 is turned off, and the first clocked inverter INVa is turned on, at this time, the first clocked inverter INVa outputs the signal latched by the input terminal thereof to the input terminal of the first inverter INV1 and the input terminal of the third inverter INV3, and the non-inverted output terminal and the inverted output terminal of the first Latch D Latch1 both maintain to output the signal output when the signal was turned on at the previous moment.

That is, in the present embodiment, when the frequency-divided input signal CI received by the non-inverting input terminal of the first Latch D Latch1 is a low level signal, the non-inverting output terminal outputs the signal inputted by the signal input terminal thereof, and the signal is outputted as a carry output signal through the first inverter INV1, and the inverting output terminal outputs an inverted signal of the signal inputted by the signal input terminal thereof. And when the frequency division input signal CI received at the non-inverting input terminal of the first Latch D Latch1 is a high level signal, the first Latch D Latch1 is turned off, which maintains the current signal output.

In this regard, since the first Latch D Latch1 is turned on when the frequency-dividing input signal CI received by the non-inverting input terminal thereof is a low-level signal, even when there is a delay in the output signal of the first Latch D Latch1 in actual situations, the edges (i.e., the rising edge and the falling edge) of the signal output by the non-inverting output terminal of the first Latch D Latch1 in the frequency-dividing unit of the present embodiment are delayed from the falling edge of the frequency-dividing input signal CI received by the first Latch D Latch1, in other words, there is a Latch delay between the edge of the carry output signal MODOUT of the frequency-dividing unit and the falling edge of the frequency-dividing input signal CI received by the frequency-dividing unit. Fig. 8 is a timing diagram of a frequency division input signal CI , a timing diagram of a carry output signal MODOUT , and a timing diagram of signals obtained after the phase-and of CI and MODOUT of the frequency division unit in fig. 6 according to an embodiment of the present invention.

Further, describing the second Latch D Latch2 in detail, referring to fig. 6, the second Latch DLatch2 includes a second clocked transmission gate TG2, a second clocked inverter INVb, and a fourth inverter INV 4.

The first input end of the second clocked transmission gate TG2 is used as the signal input end of the second Latch D Latch2 and is connected with the output end of the second NAND gate NAND2, the output end of the second clocked transmission gate TG2 is used as the positive phase output end of the second Latch D Latch2 and is connected with the first input end of the first NAND gate NAND1, meanwhile, the output end of the second clocked transmission gate TG2 is also connected with the input end of the fourth inverter INV4 and the output end of the second clocked inverter INVb, and the output end of the fourth inverter INV4 is connected with the first input end of the second clocked inverter INVb.

The second clocked transmission gate TG2 further has a second input terminal CIB and a third input terminal CI, the second input terminal CIB of the second clocked transmission gate TG2 is used as a negative phase input terminal of the second Latch D Latch2 and is configured to receive a frequency-divided input signal inverted signal CIB , and the third input terminal CI of the second clocked transmission gate TG2 is used as a positive phase input terminal of the second Latch D Latch2 and is configured to receive a frequency-divided input signal CI .

And when the frequency-divided input signal CI is a high-level signal, the second clocked transmission gate TG2 is turned on, and its output terminal outputs a signal input by its first input terminal, and when the frequency-divided input signal CI is a low-level signal, the second clocked transmission gate TG2 is turned off.

Further, the second clocked inverter INVb is also provided with a second input terminal CI and a third input terminal CIB, the second input terminal CI of the second clocked inverter INVb is used as a positive phase input terminal of the second Latch D Latch2 for receiving the frequency-divided input signal CI , and the third input terminal CIB of the second clocked inverter INVb is used as a negative phase input terminal of the second Latch DLatch2 for receiving an inverted signal CIB of the frequency-divided input signal.

Specifically, fig. 9 is a schematic structural diagram of a second clocked inverter INVb according to a first embodiment of the present invention, and referring to fig. 7 and fig. 9, the structure of the second clocked inverter INVb is the same as that of the first clocked inverter INVa, and both of them include: the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2 have the same connection relationship with the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the second NMOS transistor N2.

However, it is emphasized that, unlike the first clocked inverter INVa, in the second clocked inverter INVb, the gate of the second PMOS transistor P2 serves as the second input terminal CI of the second clocked inverter INVb for receiving the frequency-divided input signal CI , the gate of the first NMOS transistor N1 serves as the third input terminal CIB of the second clocked inverter INVb for receiving the inverted signal CIB of the frequency-divided input signal, and the gate of the first PMOS transistor P1 and the gate of the second NMOS transistor N2 serve as the first input terminal of the second clocked inverter INVb, and the first node a serves as the output terminal of the second clocked inverter INVb.

When the frequency-division input signal CI is a high-level signal, the second clocked inverter INVb is turned off. When the frequency division input signal CI is a low level signal, the second clocked inverter INVb is turned on and performs an inversion function.

Based on that the structure of the second clocked inverter INVb is the same as that of the first clocked inverter INVa, the on/off principle of the second clocked inverter INVb is also the same as that of the first clocked inverter INVa, and thus the on/off principle of the second clocked inverter INVb can be referred to in the description of the on/off principle of the first clocked inverter INVa in the above description, and this embodiment is not described herein again.

Further, describing the structure of the first flip-flop DFF1 in fig. 6 in detail, the first flip-flop DFF1 may be, for example, a TSPC type D flip-flop, and fig. 10 is a schematic structural diagram of a first flip-flop DFF1 according to an embodiment of the present invention, as shown in fig. 10, the first flip-flop DFF1 may include: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a seventh NMOS transistor N7.

Referring to fig. 6 and 10, gates of the third PMOS transistor P3 and the fifth NMOS transistor N5 are used as a signal input terminal D of the first flip-flop DFF1, a source of the third PMOS transistor P3 is connected to a voltage source VDD, a drain of the third PMOS transistor P3 is connected to a source of a sixth PMOS transistor P6, a drain of the sixth PMOS transistor P6 is connected to a second node B, the second node B is connected to a drain of the fifth NMOS transistor N5, and a source of the fifth NMOS transistor N5 is grounded. The second node B is further connected to a gate of a third NMOS transistor N3, a drain of the third NMOS transistor N3 is connected to a third node C, the third node C is further connected to a drain of the fourth PMOS transistor P4, a source of the fourth PMOS transistor P4 is connected to a voltage source VDD, a source of the third NMOS transistor N3 is connected to a drain of the sixth NMOS transistor N6, a source of the sixth NMOS transistor N6 is grounded, the third node C is further connected to a fourth node E, the fourth node E is connected to a gate of a fifth PMOS transistor P5 and a gate of a seventh NMOS transistor N7, a source of the fifth PMOS transistor P5 is connected to the voltage source VDD, a drain of the fifth PMOS transistor P5 is connected to a drain of the fourth NMOS transistor N4 and serves as an inverted output terminal-Q of the first flip-flop DFF1, a source of the fourth NMOS transistor N4 is connected to a drain of the seventh NMOS transistor N7, and a source of the seventh NMOS transistor N7 is grounded.

The gate of the fourth PMOS transistor P4, the gate of the sixth PMOS transistor P6, the gate of the fourth NMOS transistor N4, and the gate of the sixth NMOS transistor N6 are all used as the non-inverting input terminal CK of the first flip-flop DFF1, and are used for receiving the frequency-division input signal CI .

In the first embodiment, the conduction principle of the first flip-flop DFF1 is specifically as follows: when the frequency-divided input signal CI is changed from a low level signal to a high level signal, the first flip-flop DFF1 is turned on, and the inverted output terminal-Q of the first flip-flop DFF1 outputs the inverted signal of the signal input terminal D, and when the frequency-divided input signal CI is changed from a high level signal to a low level signal, the first flip-flop DFF1 is turned off, and the inverted output terminal-Q of the first flip-flop DFF1 maintains the current output signal.

The conduction principle of the first flip-flop DFF1 will be described in detail below with reference to fig. 10.

Referring to fig. 10, when the divided frequency input signal CI received by the non-inverting input terminal CK of the first flip-flop DFF1 is at a low level, the sixth PMOS transistor P6 and the fourth PMOS transistor P4 are turned on, and the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are turned off. At this time, under the action of the fifth NMOS transistor N5 or the third PMOS transistor P3, the potential of the second node B is opposite to the potential of the D end of the signal input end of the first flip-flop DFF1, specifically, if a high level signal is input to the signal input end D of the first flip-flop DFF1, the third PMOS transistor P3 is turned off, the fifth NMOS transistor N5 is turned on, and the fifth NMOS transistor N5 pulls down the voltage at the second node B to a low potential; if a low level signal is inputted to the signal input terminal D of the first flip-flop DFF1, the fifth NMOS transistor N5 is turned off, the third PMOS transistor P3 is turned on, and the third NMOS transistor P3 pulls up the voltage at the second node B to a high level.

Meanwhile, since the fourth PMOS transistor P4 is turned on and always turned on, when the potential of the third node C is always high due to the pull-up of the fourth PMOS transistor P4, the potential of the fourth node E is also always high, the fifth PMOS transistor P5 is turned off, and meanwhile, the fourth NMOS transistor N4 is also turned off, and the inverted output terminal-Q does not output a signal, that is, the first flip-flop DFF1 is turned off.

As can be seen from the above, when the frequency-divided input signal CI is low, the potential of the second node B in the first flip-flop DFF1 is opposite to the potential received at the signal input terminal D thereof, and the first flip-flop DFF1 is turned off.

Further, referring to fig. 10, when the frequency-divided input signal CI is changed from a low-level signal to a high-level signal, the sixth PMOS transistor P6 and the fourth PMOS transistor P4 are turned off, the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are turned on, and the potential at the second node B is opposite to the potential at the signal input terminal D of the first flip-flop DFF 1. On this basis, under the action of the third NMOS transistor N3, the potential of the third node C is opposite to the potential of the second node B, that is, the potential of the third node C is equal to the potential of the signal input terminal D of the first flip-flop DFF 1. Specifically, when the potential of the second node B is a high potential, the third NMOS transistor N3 is turned on, and the third NMOS transistor N3 pulls down the potential of the third node C to a low potential; when the voltage level of the second node B is low, the third NMOS transistor N3 is turned off, and the third node C maintains the original high voltage level.

And, based on the connection of the third node C with the fourth node E, the third node C should be identical to the potential of the fourth node E, that is, the potential of the fourth node E is identical to the potential of the signal input terminal D of the first flip-flop DFF. At this time, the potential of the inverting output terminal Q of the first flip-flop DFF is opposite to the potential of the fourth node E, that is, the potential of the inverting output terminal Q of the first flip-flop DFF is opposite to the potential of the signal input terminal D of the first flip-flop DFF, due to the action of the fifth PMOS transistor P5 or the seventh NMOS transistor N7. Specifically, when the potential of the fourth node E is a low potential, the seventh NMOS transistor N7 is turned off, the fifth PMOS transistor P5 is turned on, and the fifth PMOS transistor P5 pulls up the potential of the inverted output terminal-Q to a high potential; when the potential of the fourth node E is a high potential, the fifth PMOS transistor P5 is turned off, the seventh NMOS transistor N7 is turned on, and at this time, based on that the fourth NMOS transistor N4 is turned on, the fourth NMOS transistor N4 and the seventh NMOS transistor N7 pull down the potential of the inverting output terminal-Q to a low potential.

It can be seen that, when the frequency-division input signal CI changes from a low-level signal to a high-level signal, the signal output from the inverting output terminal-Q of the first flip-flop DFF1 should be the inverted signal of the signal received at the signal input terminal D.

To summarize, for the first flip-flop DFF1 in the first embodiment, when the frequency-divided input signal CI received at the non-inverting input terminal CK of the first flip-flop DFF1 changes from a high level signal to a low level signal, the first flip-flop DFF1 is turned off, the signals output from the inverting output terminal to Q of the first flip-flop DFF1 do not change, and the signal potential received at the signal input terminal D of the first flip-flop DFF1 is opposite to the signal potential at the second node B. When the frequency-divided input signal CI received by the non-inverting input terminal CK of the first flip-flop DFF1 changes from a low level signal to a high level signal, the first flip-flop DFF1 is turned on, and the inverting output terminal-Q outputs an inverted signal of the signal received by the signal input terminal D.

In addition, it should be noted that, as seen from the structure of the first trigger DFF1 shown in fig. 10, the trigger in the first embodiment of the present invention mainly adopts a nine-transistor TSPC-D trigger, which has a simple structure and a small occupied area.

Further, referring again to fig. 6, the frequency dividing unit may further include a first differential circuit 01, and the first differential circuit 01 may include: a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, and a third clocked transmission gate TG 3.

An input end of the seventh inverter INV7 is used as an input end of the first differential circuit 01, and is connected to an output end of the second inverter INV2, an output end of the seventh inverter INV7 is connected to an input end of the eighth inverter INV8, and an output end of the eighth inverter INV8 is connected to an input end of the ninth inverter INV 9.

The first input end of the third clocked transmission gate TG3 is connected to the output end of the seventh inverter INV7, the second input end of the third clocked transmission gate TG3 is connected to the voltage source VDD, the third input end of the third clocked transmission gate TG3 is grounded, wherein the third clocked transmission gate TG3 is always in an on state under the action of the voltage source VDD, and the output end of the third clocked transmission gate TG3 is connected to the input end of the tenth inverter INV 10.

Further, in the first embodiment, the first differential circuit 01 has a positive phase output terminal CO and a negative phase output terminal COB for respectively outputting the frequency-divided output signal CO and the inverse signal COB of the frequency-divided output signal. Specifically, an output end of the ninth inverter INV9 is used as the positive phase output end CO of the first differential circuit 01, and an output end of the tenth inverter INV10 is used as the negative phase output end COB of the first differential circuit 01.

The input end of the first differential circuit 01 receives the frequency-divided output signal CO provided by the inverted output end of the first flip-flop DFF1 through the second inverter INV2, outputs the frequency-divided output signal CO through the positive output end CO of the first differential circuit 01, and outputs the inverted signal COB of the frequency-divided output signal through the negative output end COB of the first differential circuit 01.

It should be noted that the non-inverting input terminal of the first Latch D Latch1, the non-inverting input terminal of the second Latch D Latch2, and the non-inverting input terminal CK of the first flip-flop DFF1 mentioned above may be all used as the positive signal input terminal of the frequency dividing unit shown in fig. 6, so as to receive the frequency dividing input signal CI . And, the negative phase input terminal of the first Latch D Latch1 and the negative phase input terminal of the second Latch D Latch2 may both serve as the negative signal input terminal of the frequency dividing unit shown in fig. 6, for receiving the inverted signal CIB of the frequency divided input signal. Meanwhile, the positive phase output terminal CO of the first differential circuit 01 may serve as the positive signal output terminal of the frequency dividing unit shown in fig. 6 to output the frequency dividing output signal CO , and the negative phase output terminal COB of the first differential circuit 01 may serve as the negative signal output terminal of the frequency dividing unit shown in fig. 6 to output the inverse signal COB of the frequency dividing output signal. Wherein the frequency division output signal CO is a signal obtained after the frequency division operation is performed on the frequency division input signal CI .

Further, the principle of the frequency dividing unit shown in fig. 6 will be described in detail with reference to the above. For the frequency dividing unit shown in fig. 6, when the frequency dividing control signal P is 0, or when the frequency dividing control signal P is 1, if the carry input signal is 0, the frequency dividing unit shown in fig. 6 may implement a divide-by-two function; when the frequency division control signal P is equal to 1 and the carry input signal is 1, the frequency division unit shown in fig. 6 can implement a frequency division function of three.

Specifically, referring to fig. 6, when the frequency-division control signal P is equal to 0, if the second input terminal of the second NAND gate NAND2 receives 0, the output terminal of the second NAND gate NAND2 always outputs 1, and correspondingly, if the signal input terminal of the second Latch D Latch2 always receives 1, the non-inverting output terminal thereof also always outputs 1, so that the first input terminal of the first NAND gate NAND1 also always receives 1, and at this time, the result based on 1 and any phase and thereafter is the number itself, so that the signal output from the output terminal of the first NAND gate NAND1 is only related to the signal input from the second input terminal of the first NAND gate NAND1, and thus, the frequency-division output signal CO output by the first flip-flop DFF1 is also only related to the signal input from the second input terminal of the first NAND gate 1. At this time, it can be determined that none of the third NAND gate 3, the first Latch D Latch1, the second NAND gate 2, and the second Latch D Latch2 should reach the frequency-divided output signal CO output by the frequency dividing unit shown in fig. 6, and the third NAND gate NAND3, the first Latch D Latch1, the second NAND gate NAND2, and the second Latch D Latch2 can be ignored.

Based on this, the principle of the frequency division unit shown in fig. 6 that realizes the divide-by-two function is described:

table 1 is a table of correspondence relationships between the frequency-division input signal in the frequency-division unit shown in fig. 6 and the received signal at the signal input terminal of the first flip-flop DFF1 and the frequency-division output signal output from the negative-phase output terminal when the frequency-division control signal is 0 according to the first embodiment.

TABLE 1

Referring to table 1, when the frequency dividing unit is just started and does not receive the frequency dividing input signal CI , the negative phase output terminal-Q output of the first flip-flop DFF1 is 0, then 0 output from the negative phase output terminal-Q of the first flip-flop DFF1 is inverted by the second inverter INV2 and becomes 1, and the 1 is input to the second input terminal of the first NAND gate NAND1, and based on that the first input terminal of the first NAND gate 1 is always 1, the signal output from the output terminal of the first NAND gate should be the inverted signal of the signal at the second input terminal thereof, that is, at this time, the signal output from the output terminal of the first NAND gate should be 0, and the signal received by the signal input terminal of the first flip-flop DFF1 should be 0. And when the frequency dividing unit is started to receive the frequency dividing input signal, if the frequency dividing input signal is 0, the first flip-flop DFF1 is turned off, and the current output signal is output at the position, that is, at this time, the inverted output terminal of the first flip-flop DFF1 should still output 0, and the signal input terminal of the first flip-flop DFF1 should also receive 0. When the frequency division input signal changes from 0 to 1, the first flip-flop turns on DFF1, and at this time, based on that the signal received by the signal input terminal of the first flip-flop DFF1 is 0, the signal output by the inverting output terminal thereof should be 1, so that the signal received by the signal input terminal of the first flip-flop DFF1 also changes to 1. Subsequently, if the frequency-division input signal changes from 1 to 0 again, the first flip-flop DFF1 is turned off, and the first flip-flop DFF1 keeps outputting 1. Thereafter, if the frequency-divided signal changes from 0 to 1 again, the first flip-flop DFF1 is turned on again, and based on the fact that the signal received at the signal input terminal is 1 at the present time, the signal output at the inverting output terminal should be 0.

By analogy, the correspondence relationship shown in table 1 can be obtained, and it can be seen from table 1 that when the signal of the frequency division input signal CI is 01010101, the frequency division output signal CO output by the inverted output terminal of the first flip-flop DFF1 should be 001100110011, wherein the period of the frequency division output signal CO is twice as long as the period of the frequency division input signal CI , and the frequency is half as long as the frequency of the frequency division input signal CI , so that the function of halving is realized.

Further, when the frequency division control signal P is equal to 1 and the carry input signal MODIN is 0, the second input terminal of the third NAND gate NAND3 always receives 0, wherein, since the result of 0 and any phase and thereafter is 0, the output end of the third NAND gate NAND3 always outputs 1, so that the output of the inverting output terminal of the first Latch D Latch1 is always 0, the first input terminal of the second NAND gate NAND2 always receives 0, this causes the input of the second NAND gate NAND2 to be always 1, and thus, the situation is similar to the situation where the frequency division control signal is 0, then, referring to the above description of "when the frequency division control signal is 0, the frequency division unit implements the frequency division by two function", it can be determined that when the frequency division control signal P is equal to 1 and the carry input signal is 0, the frequency division unit also implements the frequency division by two function.

And when the frequency division control signal P is equal to 1 and the carry input signal is 1, the frequency division unit shown in fig. 6 implements a three-frequency division function, and the specific principle is as follows:

in the first Latch D Latch1, when the frequency-divided input signal CI is at a low level, the first Latch D Latch1 is turned on, and the inverted output terminal outputs the inverted signal of the signal received at the signal input terminal, and when the frequency-divided input signal CI is at a high level, the first Latch D Latch1 is turned off, and the inverted output terminal maintains the current output signal. For second Latch D Latch2, when the divided input signal CI is high, second Latch DLatch2 is turned on and the non-inverting output terminal outputs the signal received at its signal input terminal, and when the divided input signal is low, second Latch D Latch2 is turned off and the non-inverting output terminal maintains the current output signal.

Thus, in conjunction with fig. 6, it can be determined that the expressions for the input signal and the output signal of each device are:

D1＝～((～Q0)·MODIN)＝Q0+～MODIN＝Q0

D2＝～((～Q1)·P)＝Q1+～P＝Q1

D0＝～(Q2·Q0)

wherein "+" represents an or operation, "-" represents an and operation, "-" represents a negation, and D1 is a signal received at the signal input terminal of the first Latch DLatch1, "-Q0 is a signal output from the inverting output terminal-Q of the first flip-flop DFF1, i.e., the frequency-divided output signal CO , D2 is a signal received at the signal input terminal of the second Latch D Latch2," -Q1 is a signal output from the inverting output terminal of the first Latch D Latch1, D0 is a signal received at the signal input terminal D of the first flip-flop DFF, and Q2 is a signal output from the non-inverting output terminal of the second Latch D Latch 2.

Based on this, table 2 is a correspondence table among D0, Q0, D1, Q1, D2, and Q2.

TABLE 2

Referring to table 2, when the frequency dividing unit is just activated and has not received the frequency dividing input signal CI , the Q0 of the first flip-flop outputs a high level signal 1, the Q1 of the first latch outputs a high level signal 1, and the Q2 of the second latch outputs a low level signal 0, at this time, the D0 of the first flip-flop should be the high level signal 1, then the D0 is 1, the D1 is 0, and the D2 is 0. When the divided-frequency input signal CI is 0, the first flip-flop DFF1 and the second Latch D Latch2 are turned off, and the first Latch D Latch1 is turned on, so that Q0 of the first flip-flop DFF1 should maintain the current output signal output 1, Q2 of the second Latch D Latch2 should maintain the current output signal output 0, and Q1 of the first Latch D Latch1 should output the inverted signal of D1, that is, should output 1, and at this time, D2 should maintain 1. And when the frequency-division input signal CI is switched from 0 to 1, the first flip-flop DFF1 and the second Latch D Latch2 are turned on, and the first Latch D Latch1 is turned off, so that the Q0 of the first flip-flop DFF1 should output an inverted signal of D0, so that the Q0 should be 0, the Q2 of the second Latch D Latch2 should also output D2, that is, the Q2 should be 0, and the first Latch D Latch1 is turned off, so that the Q1 of the first Latch D Latch1 should maintain output 1. In this case, D0 is 1, D1 is 1, and D2 is 0. And when the frequency-divided input signal CI is switched from 1 to 0 again, the first flip-flop DFF1 and the second Latch D Latch2 are turned off, and the first Latch D Latch1 is turned on, then the Q0 of the first flip-flop DFF1 should maintain the current output signal output of 0, the Q2 of the second Latch D Latch2 should maintain the current output signal output of 0, and the Q1 of the first Latch D Latch1 should output the inverted signal of D1, that is, should output 0.

By analogy, the correspondence shown in table 2 can be obtained, and it can be seen from table 2 that when the signal of the frequency division input signal CI is 01010101, the frequency division output signal CO output by the inverting output terminal of the first flip-flop DFF1 should be 100001100001100001, wherein the period of the frequency division output signal CO is three times that of the frequency division input signal CI , and the frequency is one third of the frequency division input signal CI , so that the function of three-frequency division is realized.

Therefore, in combination with the above, the frequency dividing unit mainly divides the frequency-divided input signal CI based on the received frequency-divided control signal P and the carry input signal MODOUT to output the frequency-divided output signal CO , and the frequency-divided output signals CO with different frequency-dividing ratios can be obtained by adjusting the values of the frequency-divided control signal P and the carry input signal MODOUT .

It should be noted that, in the frequency dividing unit provided in fig. 6 in the first embodiment, even if there is a certain delay in the output of the signal from the Latch, there is only a delay between the edge of the carry output signal MODOUT output by the first Latch D Latch1 and the falling edge of the received frequency-dividing input signal CI . Therefore, when the frequency dividing unit provided in the first embodiment is applied to the multi-modulus frequency divider, the glitch signal is not present in the frequency-divided output signal MODOUT , and the accuracy of frequency division is ensured, wherein for the explanation that the frequency dividing unit provided in the first embodiment is applied to the multi-modulus frequency divider to ensure the accuracy of frequency division, reference may be specifically made to the description in the third embodiment.

In addition, in the frequency dividing unit provided in the first embodiment of the present invention, the frequency dividing unit includes one flip-flop (i.e., the first flip-flop DFF1), and two latches (i.e., the first Latch D Latch1 and the first Latch D Latch2), so that the structure is simple and the occupied area is small. Also, since the first flip-flop DFF1 is a TSPC type D flip-flop, it has low delay, high efficiency, and low power consumption.

In summary, in the first embodiment of the present invention, when the frequency dividing unit provided in fig. 6 is applied to a multi-modulus frequency divider, the multi-modulus frequency divider can be ensured to divide frequency correctly, and the frequency dividing unit provided in fig. 6 has low delay, low power consumption, high efficiency, and small occupied area.

Example two

Further, another frequency dividing unit is provided in the second embodiment, fig. 11 is a schematic structural diagram of the frequency dividing unit provided in the second embodiment of the present invention, and as shown in fig. 11, the frequency dividing unit may include a second flip-flop DFF2, a third flip-flop DFF3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a sixth NAND gate NAND6, a fifth inverter INV5, and a sixth inverter INV 6.

A first input end of the fourth NAND gate NAND4 is connected to the inverted output end-Q of the third flip-flop DFF3, a second input end of the fourth NAND gate NAND4 is configured to receive a frequency division control signal P , and an output end of the fourth NAND gate NAND4 is connected to a first input end of the sixth NAND gate NAND 6. A second input end of the sixth NAND gate NAND6 is connected to the output end of the fifth inverter INV5, an output end of the sixth NAND gate NAND6 is connected to the signal input end D of the second flip-flop DFF2, inverted output ends-Q of the second flip-flop DFF2 are connected to the input end of the fifth inverter INV5 for outputting a frequency-divided output signal CO , and inverted output ends-Q of the second flip-flop DFF2 are further connected to the first input end of the fifth NAND gate NAND 5. A second input end of the fifth NAND gate NAND5 is configured to receive a carry input signal, and an output end of the fifth NAND gate NAND5 is connected to an input end of the sixth inverter INV6, so as to output a carry output signal MODTOUT through the sixth inverter INV 6. And the output end of the fifth NAND gate NAND5 is also connected with the signal input end of the third flip-flop DFF 3.

In the second embodiment, the structures of the second flip-flop DFF2 and the third flip-flop DFF3 are the same as the structure of the first flip-flop DFF1, and may be all nine-transistor TSPC-D flip-flops, and the conduction principles of the second flip-flop DFF2 and the third flip-flop DFF3 are also the same as the conduction principle of the first flip-flop DFF1, so the structures and the conduction principles of the second flip-flop DFF2 and the third flip-flop DFF3 may be specifically referred to the description of the first flip-flop DFF1 in the first embodiment, and the second embodiment is not repeated herein.

Further, referring to fig. 11, the frequency dividing unit may further include a second differential circuit 02, and the second differential circuit 02 may include: an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, and a fourth clocked transmission gate TG 4.

An input end of the eleventh inverter INV11 is connected to an output end of the fifth inverter INV5, an output end of the eleventh inverter INV11 is connected to an input end of the twelfth inverter INV12, and an output end of the twelfth inverter INV12 is connected to an input end of the thirteenth inverter IVN 13.

A signal input end of the fourth clocked transmission gate TG4 is connected to an output end of the eleventh inverter INV11, and an output end of the fourth clocked transmission gate TG4 is connected to an input end of the fourteenth inverter INV 14.

Still further, in the second embodiment, the second differential circuit 02 includes a positive phase output terminal CO and a negative phase output terminal COB for respectively outputting the frequency-divided output signal CO and the inverse phase signal COB of the frequency-divided output signal. Specifically, in the second differential circuit 02, an output end of the thirteenth inverter IVN13 is used as a non-inverting output end CO of the second differential circuit 02, and an output end of the fourteenth inverter INV14 is used as an inverting output end COB of the second differential circuit 02.

The input end of the second differential circuit 02 receives the frequency-divided output signal CO provided by the inverted output end-Q of the second flip-flop DFF2 through the fifth inverter INV5, outputs the frequency-divided output signal CO through the positive output end CO of the second differential circuit 02, and outputs the inverted signal COB of the frequency-divided output signal through the negative output end COB of the second differential circuit 02.

In addition, it should be noted that the non-inverting input terminal CK of the second flip-flop DFF2 and the non-inverting input terminal CK of the third flip-flop DFF3 mentioned above can be used as the positive signal input terminal of the frequency dividing unit shown in fig. 11 for receiving the frequency dividing input signal CI . The positive phase output terminal CO of the second differential circuit 02 may serve as the positive signal output terminal of the frequency dividing unit shown in fig. 11 to output the frequency-divided output signal CO , and the negative phase output terminal COB of the second differential circuit 02 may serve as the negative signal output terminal of the frequency dividing unit shown in fig. 11 to output the inverted signal COB of the frequency-divided output signal. Wherein the frequency division output signal CO is a signal obtained after the frequency division operation is performed on the frequency division input signal CI .

It should be noted that, for the frequency dividing unit shown in fig. 11, the function is similar to that of the frequency dividing unit shown in fig. 6. Specifically, the frequency dividing unit shown in fig. 11 can implement the divide-by-two function when its received frequency division control signal P -0, or when its received frequency division control signal P -1 and MODIN -0. The frequency dividing unit shown in fig. 11 can implement a three-frequency dividing function when its received frequency dividing control signal P is 1 and MODIN is 1.

In view of the fact that the principle of the function of the frequency dividing unit shown in fig. 11 is similar to the principle of the function of the frequency dividing unit shown in fig. 6, reference may be specifically made to the description of the principle of the function of the frequency dividing unit shown in fig. 6 with respect to the principle of the function of the frequency dividing unit shown in fig. 11, and no further description is given here in the second embodiment of the present invention.

In summary, for the frequency dividing unit provided in fig. 11 of the present invention, since the carry output signal MODOUT is directly output from the output terminal of the fifth NAND gate NAND5, it is not required to pass through the third flip-flop DFF3, thereby reducing the output delay and improving the operating efficiency of the frequency dividing unit. In addition, based on the fact that the second flip-flop DFF2 and the third flip-flop DFF3 in the frequency dividing unit provided in fig. 11 are both simple nine-transistor TSPC-D flip-flops, the structure is simple and the occupied area is small. In addition, the frequency division unit shown in fig. 11 is substantially a dual D flip-flop structure, and has a faster processing speed and lower power consumption.

In addition, in this embodiment, the inverters in the first differential circuit 01 and the second differential circuit 02 may specifically serve as buffers to reduce the rising and falling time of the frequency-divided output signal CO and the inverted signal COB of the frequency-divided output signal, thereby improving the working efficiency. And, the transmission gates in the first and second

differential circuits

01 and 02 may delay the inverted signal COB of the frequency-divided output signal to have a phase difference of about 180 ° with the frequency-divided output signal CO , so as to ensure that the frequency dividing unit can operate correctly.

EXAMPLE III

Fig. 12 is a schematic structural diagram of a multi-modulus frequency divider according to a third embodiment of the present invention, and as shown in fig. 12, the multi-modulus frequency divider is formed by cascading a plurality of frequency dividing units. The first-stage frequency dividing unit of the multi-modulus frequency divider may include the frequency dividing unit shown in fig. 11 (i.e., the frequency dividing unit provided in embodiment two), and the frequency dividing units shown in fig. 6 (i.e., the frequency dividing units provided in embodiment one) are included in the other frequency dividing units of the multi-modulus frequency divider except for the first-stage frequency dividing unit.

And, referring to fig. 12, the first stage frequency dividing unit may include:

and a positive signal input terminal CI for receiving the frequency-divided input signal CI .

And a carry input terminal MODIN for receiving a carry input signal MODIN .

And a carry output terminal MODOUT for outputting a carry output signal MODOUT .

And the frequency division control end P is used for receiving the frequency division control signal P .

And the positive signal output end CO is used for outputting a frequency division output signal CO , and the frequency division output signal CO is a frequency division signal of the frequency division input signal CI .

And the negative signal output end COB is used for outputting an inverted signal COB of the frequency division output signal.

Wherein, the non-inverting input terminal CK of the second flip-flop DFF2 and the non-inverting input terminal CK of the third flip-flop DFF3 in the first stage frequency dividing unit can be used as the positive signal input terminal CI of the first stage frequency dividing unit; a second input terminal of the fifth NAND gate NAND5 can be used as a carry input terminal MODIN of the first-stage frequency dividing unit; a second input end of the fourth NAND gate NAND4 may serve as a frequency division control end P of the first-stage frequency division unit; an output end of the sixth inverter INV6 may be used as a carry output end MODOUT of the first-stage frequency dividing unit; a positive phase output end CO of a second differential circuit 02 in the first frequency division unit is used as a positive signal output end CO of the first-stage frequency division unit; the negative phase output end COB of the second differential circuit 02 in the first frequency dividing unit can be used as the negative signal output end COB of the first-stage frequency dividing unit.

Optionally, the other sub-frequency dividing unit may include:

And the negative signal input end CIB is used for receiving an inverted signal CIB of the frequency division input signal.

And the positive signal output end CO is used for outputting a frequency division output signal CO , and the frequency division output signal CO is a frequency division signal corresponding to the frequency division input signal CI .

The positive phase input terminal of the first Latch D Latch1, the positive phase input terminal of the second Latch DLatch2, and the positive phase input terminal CK of the first flip-flop DFF1 in the other fractional frequency unit may be used as the positive signal input terminal CI of the other fractional frequency unit; the negative phase input end of the first Latch D Latch1 and the negative phase input end of the second Latch DLatch2 in the other fractional frequency unit can be used as the negative signal input end CIB of the other fractional frequency unit; a second input end of the second NAND gate NAND2 can be used as a frequency division control end P of the other frequency division unit; a second input terminal of the third NAND gate NAND3 can be used as a carry input terminal MODIN of the other fractional frequency unit; an output end of the first inverter INV1 is used as a carry output end MODOUT of the other stage frequency dividing unit; the positive phase output terminal CO of the first differential circuit 01 in the other sub-frequency dividing unit can be used as the positive signal output terminal CO of the other sub-frequency dividing unit; the negative phase output terminal COB of the first differential circuit 01 in the other fractional frequency unit can be used as the negative signal output terminal COB of the other fractional frequency unit.

Optionally, referring to fig. 12, a positive signal input terminal CI of the first-stage frequency dividing unit is configured to receive an initial frequency dividing input signal CI <0>, a positive signal input terminal CI of each stage of frequency dividing unit after the first-stage frequency dividing unit is connected to a positive signal output terminal CO of the previous-stage frequency dividing unit, and a negative signal input terminal CIB of each stage of frequency dividing unit after the first-stage frequency dividing unit is connected to a negative signal output terminal COB of the previous-stage frequency dividing unit.

And the carry input terminal MODIN of the last stage of frequency dividing unit is used for receiving an initial carry input signal MODIN <0>, and the carry input terminal MODIN of each stage of frequency dividing unit before the last stage of frequency dividing unit is connected with the carry output terminal MODOUT of the next stage of frequency dividing unit.

As can be seen from the above, in the multi-mode frequency divider provided in this embodiment three, the frequency-division input signal CI of each stage of frequency dividing unit except the first-stage frequency dividing unit is the frequency-division output signal CO < i-1> of the previous-stage frequency dividing unit, that is, CI -CO < i-1>, and the carry output signal MODOUT of each stage of frequency dividing unit except the last-stage frequency dividing unit is the carry input signal MODIN < i-1> of the previous-stage frequency dividing unit, that is, MODIN -1 >.

Based on this, since each stage of frequency dividing units of the multi-modulus frequency divider in the embodiment of the present invention except for the first stage of frequency dividing unit includes the frequency dividing unit provided in the first embodiment, the edge of the carry output signal MODOUT of each stage of frequency dividing unit except for the first stage of frequency dividing unit and the falling edge of the frequency dividing input signal CI of the current stage of frequency dividing unit have a delay of one latch. That is, it is equivalent to that there is a delay of one latch between the edge of the carry input signal MODIN of each stage of frequency dividing unit except the first stage of frequency dividing unit and the falling edge of the frequency dividing input signal CI of the current stage of frequency dividing unit (for example, refer to fig. 8). At this time, when the third NAND gate NAND3 in each stage of frequency dividing unit except the first stage frequency dividing unit performs and processing on the carry input signal MODIN and the frequency dividing input signal CI , which are received by the third NAND gate NAND3, no glitch signal occurs in the signal obtained after the and processing, for example, refer to fig. 8. Therefore, no glitch signal exists in the signal output from the third NAND gate NAND3 to the first Latch D Latch1, and no glitch signal exists in the carry output signal MODOUT output from the carry output terminal MODOUT of each stage of frequency dividing unit except the first stage of frequency dividing unit, so that the occurrence of the phenomenon of "glitch exists in the carry output signal output from the frequency dividing unit" in the related art is avoided, and the frequency dividing correctness of the multi-modulus frequency divider is ensured.

In addition, since the first-stage frequency dividing unit of the multi-modulus frequency divider divides the initial frequency division input signal for the first time, it is more demanding on the frequency, and thus, when the first-stage frequency dividing unit is set as the frequency dividing unit shown in fig. 11, the processing speed based on the frequency dividing unit shown in fig. 11 is faster, the operating efficiency is higher, and the frequency dividing efficiency of the multi-modulus frequency divider can be improved.

In addition, since the carry output signal MODOUT <0> of the first stage frequency dividing unit is not input to the other stage frequency dividing units, even if a glitch signal exists in the carry output signal MODOUT <0> of the first stage frequency dividing unit, the frequency dividing effect of the multi-mode frequency divider is not affected.

In summary, in the multi-modulus frequency divider provided by the present invention, the first-stage frequency dividing unit of the multi-modulus frequency divider includes the frequency dividing unit shown in fig. 11, and the processing speed is higher. Meanwhile, each stage of frequency division units except the first stage of frequency division unit in the multi-mode frequency divider comprises the frequency division unit shown in fig. 6, so that no burr signal exists in the carry output signal output by each stage of frequency division units except the first stage of frequency division unit, and the multi-mode frequency divider can perform normal frequency division on the signal. The multi-mode frequency divider can ensure the frequency dividing accuracy while ensuring the frequency dividing speed, and has low power consumption.

Meanwhile, the multi-mode frequency divider has the advantages of small delay, small occupied area, layout space saving and high transportability.

Finally, in the invention, under the worst process angle, the working frequency of the front simulation and the working frequency of the rear simulation of the multi-mode frequency divider are both higher, wherein the front simulation can reach 6.6GHz, and the rear simulation can also reach 4.2GHz, thereby further improving the accuracy of frequency division processing.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A frequency division unit is characterized by comprising a first latch, a second latch, a first trigger, a first NAND gate, a second NAND gate, a third NAND gate, a first inverter and a second inverter;

2. The frequency divider cell of claim 1, wherein the first latch further has a negative phase input for receiving an inverted signal of the frequency divided input signal;

3. The frequency-dividing cell of claim 2, wherein the first latch comprises a first clocked transmission gate, a first clocked inverter, and a third inverter;

4. The frequency-dividing cell of claim 2, wherein the second latch comprises a second clocked transmission gate, a second clocked inverter, and a fourth inverter;

5. The frequency divider block of claim 1, further comprising a first differential circuit having a positive phase output and a negative phase output;

6. The multi-mode frequency divider is characterized in that the multi-mode frequency divider is formed by cascading a plurality of frequency dividing units;

the frequency division units of the other stages except the first stage frequency division unit in the multi-modulus frequency divider comprise the frequency division unit of any one of claims 1 to 5;

7. The multi-modulus divider of claim 6, wherein the second flip-flop and the third flip-flop each have a non-inverting input for receiving a divided input signal, and wherein the second flip-flop and the third flip-flop are turned on when the divided input signal changes from a low level signal to a high level signal.

8. The multi-modulus divider of claim 6, wherein the frequency-dividing unit further comprises a second differential circuit having a positive phase output and a negative phase output;

9. The multi-modulus divider of any of claims 6-8, wherein the first stage frequency-dividing unit comprises:

a positive signal input for receiving a frequency divided input signal;

a carry input terminal for receiving a carry input signal;

a carry output terminal for outputting a carry output signal;

10. The multi-modulus divider of claim 6, wherein the other stage frequency dividing unit comprises:

a positive signal input for receiving a frequency divided input signal;

a carry input terminal for receiving a carry input signal;

a carry output terminal for outputting a carry output signal;

11. The multi-modulus divider of claim 10,

the positive signal input end of the first-stage frequency division unit is used for receiving an initial frequency division input signal, the positive signal input end of each stage of frequency division unit behind the first-stage frequency division unit is connected with the positive signal output end of the previous-stage frequency division unit, and the negative signal input end of each stage of frequency division unit behind the first-stage frequency division unit is connected with the negative signal output end of the previous-stage frequency division unit;

12. The multi-modulus divider of claim 6, wherein the divided input signal comprises a clock signal.