CN117674824A - Low-jitter clock frequency division implementation circuit - Google Patents
Low-jitter clock frequency division implementation circuit Download PDFInfo
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Abstract
The invention discloses a low-jitter clock frequency division realizing circuit, which uses the phase relation between an external clock and each stage of frequency division clocks, takes the external clock as a switch enabling signal to control the transmission of each stage of frequency division clocks, removes the correlation of the edge jitter of an output frequency division clock and an internal frequency division clock, realizes the effect of low-jitter frequency division output, and comprises at least two stages of triggers, wherein the clock input end of each stage of trigger is connected with an inverter; the data input end of each stage of trigger is short-circuited with the reverse phase output end of the stage of trigger, the normal phase output end of the former stage of trigger is connected with the input end of the inverter connected with the clock input end of the latter stage of trigger, and the inverter connected with the clock input end of the first stage of trigger is connected with an external clock; the non-inverting output end of each stage of trigger is also connected with a transmission gate through an inverter, and the output of the transmission gate is output through at least one stage of inverter to obtain a low-jitter frequency division clock.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-jitter clock frequency division realization circuit.
Background
High-speed ADCs often have a high input bandwidth, typically over 1.5 times the sampling frequency, when in actual use. This high input frequency condition is more sensitive to sample clock jitter, the larger jitter resulting in a larger aperture error introduced when the ADC samples.
The sampling clock of the high-speed ADC is typically obtained by passing an external high-frequency clock through a local frequency divider circuit. Besides the jitter of the external clock itself, the jitter introduced by the frequency dividing circuit is also critical. The most common frequency division circuit implementation is a cascade of multiple stages of D flip-flops, each stage of D flip-flop outputting a corresponding divide by 2N clock. Thus, the higher the division multiple, the more D flip-flops included on the division path, and the greater the jitter accumulated to the output clock per stage of D flip-flops. One way to reduce jitter is to optimize the D flip-flop, which tends to be less jitter than that introduced by the static D flip-flop. However, optimizing the dynamic D flip-flop increases the design difficulty relative to directly invoking the static D flip-flop in the standard cell library, and the dynamic D flip-flop itself introduces jitter.
Disclosure of Invention
The invention aims to provide a low-jitter clock frequency division realization circuit, which uses the phase relation between an external clock and each stage of frequency division clocks, takes the external clock as a switch enabling signal to control the transmission of each stage of frequency division clocks, removes the correlation of the edge jitter of an output frequency division clock and an internal frequency division clock, and realizes the effect of low-jitter frequency division output.
The invention is realized by the following technical scheme: a low-jitter clock frequency division implementation circuit comprises N stages of flip-flops, wherein an inverter is connected to the clock input end of each stage of flip-flop; the data input end of each stage of trigger is short-circuited with the reverse phase output end of the stage of trigger, the normal phase output end of the former stage of trigger is connected with the input end of the inverter connected with the clock input end of the latter stage of trigger, and the inverter connected with the clock input end of the first stage of trigger is connected with an external clock.
Further, in order to better realize the low-jitter clock frequency division implementation circuit, the following arrangement mode is adopted: the non-inverting output end of each stage of trigger is also connected with a transmission gate through an inverter, and the output of the transmission gate is output through at least one stage of inverter to obtain a low-jitter frequency division clock.
Further, in order to better realize the low-jitter clock frequency division implementation circuit, the following arrangement mode is adopted: the output of the transmission gate is connected with a three-stage inverter, but is not limited thereto.
Further, in order to better realize the low-jitter clock frequency division implementation circuit, the following arrangement mode is adopted: the clock signals of the transmission gate are the external clock and the inverted external clock of the external clock after passing through the inverter.
Further, in order to better realize the low-jitter clock frequency division implementation circuit, the following arrangement mode is adopted: the transmission gate consists of an NMOS tube and a PMOS tube, wherein the source electrode of the NMOS tube and the drain electrode of the PMOS tube are connected together and connected to the positive output end of the previous stage trigger to output signals after being inverted by the inverter; the grid electrode of the NMOS tube is connected with an external clock, the drain electrode of the NMOS tube and the source electrode of the PMOS tube are connected together and serve as the output end of the transmission gate, and the external clock is connected with the grid electrode of the PMOS tube through the inverted external clock after passing through the inverter.
Further, in order to better realize the low-jitter clock frequency division implementation circuit, the following arrangement mode is adopted: and N is a natural number greater than or equal to 2.
Further, in order to better realize the low-jitter clock frequency division implementation circuit, the following arrangement mode is adopted: the trigger adopts a D trigger or a T trigger and the like.
Compared with the prior art, the invention has the following advantages:
(1) The invention uses the phase relation between the external clock and each stage of frequency division clock, uses the external clock as a switch enabling signal to control the transmission of each stage of frequency division clock, removes the correlation of the edge jitter of the output frequency division clock and the internal frequency division clock, and realizes the effect of low-jitter frequency division output.
(2) The invention realizes the optimization of not introducing other jitter except the jitter of the external clock under the condition of almost no extra hardware cost, and greatly reduces the design difficulty.
(3) The invention effectively solves the problem of performance deterioration caused by extra clock jitter introduced by the high-speed ADC sampling clock generation circuit.
Drawings
Fig. 1 is a schematic circuit diagram (internal divided clock generation section) of the present invention.
Fig. 2 is a schematic circuit diagram (output divided clock generation section) of the present invention.
FIG. 3 is a timing diagram of the generation and triggering of each stage of divided clocks.
Detailed Description
The present invention will be described in further detail with reference to examples, but embodiments of the present invention are not limited thereto.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
Example 1:
the invention designs a low-jitter clock frequency division realization circuit, which uses the phase relation between an external clock and each stage of frequency division clocks, takes the external clock as a switch enabling signal to control the transmission of each stage of frequency division clocks, removes the correlation of the edge jitter of an output frequency division clock and an internal frequency division clock, realizes the effect of low-jitter frequency division output, and comprises N stages of triggers, wherein an inverter is connected to the clock input end of each stage of triggers; the data input end of each stage of trigger is short-circuited with the reverse phase output end of the stage of trigger, the normal phase output end (output is internal frequency division clock) of the former stage of trigger is connected with the input end of the inverter connected with the clock input end of the latter stage of trigger, and the inverter connected with the clock input end of the first stage of trigger is connected with an external clock.
As a preferred design scheme, the low-jitter clock frequency division implementation circuit comprises at least two stages of triggers, wherein an inverter is connected to the clock input end of each stage of trigger, and the output end of the inverter is connected to the clock input end of the stage of trigger when the inverter is connected; the data input end of each stage of flip-flop is short-circuited with the inverting output end of the stage of flip-flop, the positive phase output end (output is internal frequency division clock) of the previous stage of flip-flop is connected with the input end of the inverter connected with the clock input end of the next stage of flip-flop (namely, the positive phase output (internal frequency division clock) of the previous stage of flip-flop is used as the input of the inverter connected with the clock input end of the next stage of flip-flop), and the signal accessed by the inverter connected with the clock input end of the first stage of flip-flop is an external clock signal.
When the internal frequency division clock signal is in operation, the external clock signal of the first stage is divided into two parts through the trigger to form an internal frequency division clock signal, the internal frequency division clock signal is used as the clock input signal of the clock input end of the trigger of the next stage after passing through an inverter, and the subsequent circuits are the same.
Example 2:
the embodiment is further optimized based on the above embodiment, and the same features as the foregoing technical solutions are not described herein, so as to further better implement the low jitter clock frequency division implementation circuit according to the present invention, and particularly, the following setting manner is adopted: the non-inverting output end of each stage of trigger is also connected with a transmission gate through an inverter, and the output of the transmission gate is output through at least one stage of inverter to obtain a low-jitter frequency division clock (output frequency division clock).
Example 3:
the embodiment is further optimized based on any one of the embodiments, and the same features as the foregoing technical solutions are not described herein, so as to better implement the low-jitter clock frequency division implementation circuit according to the present invention, and particularly adopt the following setting manner: the output of the transmission gate is connected with a three-stage inverter, and can also be a four-stage inverter or a five-stage inverter, but is not limited to the three-stage inverter, and the three-stage inverter is determined according to the requirements of the output clock phase and the driving capability.
Example 4:
the embodiment is further optimized based on any one of the embodiments, and the same features as the foregoing technical solutions are not described herein, so as to better implement the low-jitter clock frequency division implementation circuit according to the present invention, and particularly adopt the following setting manner: the clock signals of the transmission gate are the external clock and the inverted external clock of the external clock after passing through the inverter.
Example 5:
the embodiment is further optimized based on any one of the embodiments, and the same features as the foregoing technical solutions are not described herein, so as to better implement the low-jitter clock frequency division implementation circuit according to the present invention, and particularly adopt the following setting manner: the transmission gate consists of an NMOS tube and a PMOS tube, wherein the source electrode of the NMOS tube and the drain electrode of the PMOS tube are connected together and connected to the positive output end of the previous stage trigger to output signals after being inverted by the inverter; the grid electrode of the NMOS tube is connected with an external clock, the drain electrode of the NMOS tube and the source electrode of the PMOS tube are connected together and serve as the output end of the transmission gate, and the external clock is connected with the grid electrode of the PMOS tube through the inverted external clock after passing through the inverter.
Example 6:
the embodiment is further optimized based on any one of the embodiments, and the same features as the foregoing technical solutions are not described herein, so as to better implement the low-jitter clock frequency division implementation circuit according to the present invention, and particularly adopt the following setting manner: and N is a natural number greater than or equal to 2.
Example 7:
the embodiment is further optimized based on any one of the embodiments, and the same features as the foregoing technical solutions are not described herein, so as to better implement the low-jitter clock frequency division implementation circuit according to the present invention, and particularly adopt the following setting manner: the trigger adopts a D trigger or a T trigger and the like, and when other triggers are adopted, the connection mode is the same as that of the D trigger.
Example 8:
a low-jitter clock frequency division implementation circuit is shown in fig. 1 and 2, and comprises N stages of flip-flops (each stage of flip-flop adopts a D flip-flop, namely D flip-flop DFF 1-D flip-flop DFFN, wherein N is a natural number greater than or equal to 2), and an inverter is connected to a clock input end (clk end) of each stage of flip-flop (namely, the output of the inverter is connected to the clk end of the D flip-flop); the input end (D end) of each stage D trigger is in short circuit with the reverse phase output end (Q end) of the stage D trigger, the forward phase output end (Q end) of the previous stage D trigger is connected with the input end of an inverter connected with the clock input end (clk end) of the next stage D trigger, and the inverter connected with the clock input end (clk end) of the first stage D trigger (DFF 1) is connected with an external clock (clk_in); the positive phase output end (Q end) of each stage D flip-flop is also connected with a transmission gate (TG 0) through an inverter (INV 1), the output of the transmission gate (TG 0) passes through three stages of inverters (namely an inverter INV2, an inverter INV3 and an inverter INV4 respectively), wherein the output of the transmission gate (TG 0) is taken as the input of the inverter INV2, the output of the inverter INV2 is taken as the input of the inverter INV3, the output of the inverter INV3 is taken as the input of the inverter INV 4) and the low-jitter frequency division clock (the output frequency division clock clk_div2_lj, N is a natural number which is not zero) is obtained.
The transmission gate TG0 is composed of an NMOS tube and a PMOS tube, the source electrode of the NMOS tube and the drain electrode of the PMOS tube are connected together and connected with a signal (internal frequency division clock clk_div2++N, N is a natural number which is not zero) which is output by a positive phase output end (Q end) of a previous stage trigger and is inverted by an inverter (INV 1); the grid electrode of the NMOS tube is connected with an external clock (clk_in), the drain electrode of the NMOS tube and the source electrode of the PMOS tube are connected together and serve as the output end of the transmission gate TG0, and the external clock (clk_in) is connected with the grid electrode of the PMOS tube through an inverted external clock (clk_in) after passing through an inverter.
As shown in connection with fig. 3, it is assumed that the initial values of all clocks are at the "0" level. First, the external clock clk_in triggers the first stage D flip-flop DFF1 upon arrival of the first falling edge, causing its normal phase output Q to jump from the initial state "0" level to the "1" level, after which the level remains unchanged. Then, when the second falling edge of the external clock clk_in arrives, the first stage D flip-flop DFF1 is triggered again, so that the positive phase output Q of the first stage D flip-flop DFF1 jumps from the level of 1 to the level of 0, and the level is kept unchanged until the next falling edge of the external clock clk_in arrives to trigger the positive phase output Q of the first stage D flip-flop DFF1 to jump. The non-inverting output Q of the first stage D flip-flop DFF1 is the divided clock clk_div2 with respect to the external clock clk_in.
The two divided clocks clk_div2 are simultaneously used as the input clocks of the second stage D flip-flop DFF2, and the operation mechanism is the same as that of the first stage D flip-flop DFF1, and the positive output clock clk_div4 of the second stage D flip-flop DFF2 is a divided clock with respect to clk_div2 and a four divided clock with respect to the external clock clk_in. The working mechanism of the later stage D flip-flops DFF 3-DFFN and so on, the output clocks are 8-2-N (N is a natural number excluding 0, 1, 2 and 3) divided clocks relative to the external clock clk_in respectively.
When the external clock clk_in is at the level of "1", the transmission gate TG0 is turned on, and the output divided clock clk_div2N (N is a natural number other than zero) of each stage is sent out after passing through the three stages of inverters, that is, the low-jitter divided clock clk_div2 n_lj (N is a natural number other than zero), that is, the rising edge of the external clock clk_in triggers the transition of clk_div2 n_lj.
Since the D flip-flops of each stage contribute jitter, as the frequency division multiple increases, the number of cascaded D flip-flops through which the external clock clk_in passes increases, so that the jitter introduced by the D flip-flops of each stage is accumulated into the final internal frequency division clock clk_div2 ζ, which is a main cause of the additional jitter generated by the conventional frequency division circuit. In the present invention, the internal divided clock clk_div2N is in a stable "0" or "1" state during each "1" level, so that the jitter of clk_div2 n_lj is independent of the jitter of clk_div2N itself, but is only related to the jitter of the rising edge of the external clock clk_in, i.e., the stage D flip-flops do not contribute additional jitter to clk_div2 n_lj.
The above-mentioned manner that the rising edge of clk_in triggers the D flip-flop and the rising edge turns on the transmission gate TG0 is merely illustrative, and is not limited to the protection scope, that is, the manner that the rising edge of clk_in triggers the D flip-flop and the falling edge turns on the transmission gate TG0 is still within the protection scope of the present invention.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent variation, etc. of the above embodiment according to the technical matter of the present invention fall within the scope of the present invention.
Claims (7)
1. A low-jitter clock frequency division implementation circuit is characterized in that: the device comprises N stages of triggers, wherein an inverter is connected to the clock input end of each stage of trigger; the data input end of each stage of trigger is short-circuited with the reverse phase output end of the stage of trigger, the normal phase output end of the former stage of trigger is connected with the input end of the inverter connected with the clock input end of the latter stage of trigger, and the inverter connected with the clock input end of the first stage of trigger is connected with an external clock.
2. The low jitter clock division implementation circuit of claim 1 wherein: the non-inverting output end of each stage of trigger is also connected with a transmission gate through an inverter, and the output of the transmission gate is output through at least one stage of inverter to obtain a low-jitter frequency division clock.
3. The low jitter clock division implementation circuit of claim 2 wherein: and the output of the transmission gate is connected with a three-stage inverter.
4. The low jitter clock division implementation circuit of claim 2 wherein: the clock signals of the transmission gate are the external clock and the inverted external clock of the external clock after passing through the inverter.
5. The low jitter clock division implementation circuit of claim 4 wherein: the transmission gate consists of an NMOS tube and a PMOS tube, wherein the source electrode of the NMOS tube and the drain electrode of the PMOS tube are connected together and connected to the positive output end of the previous stage trigger to output signals after being inverted by the inverter; the grid electrode of the NMOS tube is connected with an external clock, the drain electrode of the NMOS tube and the source electrode of the PMOS tube are connected together and serve as the output end of the transmission gate, and the external clock is connected with the grid electrode of the PMOS tube through the inverted external clock after passing through the inverter.
6. A low jitter clock division implementation circuit as claimed in claim 1 or 2 or 3 or 4 or 5, wherein: and N is a natural number greater than or equal to 2.
7. A low jitter clock division implementation circuit as claimed in claim 1 or 2 or 3 or 4 or 5, wherein: the trigger adopts a D trigger or a T trigger.
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| CN202410140220.8A CN117674824B (en) | 2024-02-01 | 2024-02-01 | Low-jitter clock frequency division implementation circuit |
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