CN114567302A

CN114567302A - Dynamic D trigger for improving pseudo static loop based on negative feedback

Info

Publication number: CN114567302A
Application number: CN202210076158.1A
Authority: CN
Inventors: 刘素娟; 刘堃; 葛傲冉
Original assignee: Beijing University of Technology
Current assignee: Beijing University of Technology
Priority date: 2022-01-24
Filing date: 2022-01-24
Publication date: 2022-05-31

Abstract

The invention relates to a dynamic D trigger based on negative feedback improvement pseudo-static loop. The conventional dynamic D flip-flop utilizes the charge to store data information, so that the charge can be discharged through a resistor under a low-frequency clock to cause data loss. The traditional optimization is to add a small-sized inverter to charge and discharge the capacitor to keep the data stable. However, the two-stage inverter cascade forms a positive feedback register structure, and when data is changed, stronger writing capacity or longer writing time is needed. The structure provided by the invention has the advantages that through time sequence control, when data are written in, the pseudo static loop is disconnected with the main circuit, and self-discharge or self-charging is carried out in advance through negative feedback, so that the transmission delay of the data is reduced. And when the data is kept, the pseudo static loop is connected with the main road to keep the data stable. The invention ensures the stability of low-frequency data without influencing the high-frequency characteristic of the dynamic D trigger.

Description

Dynamic D trigger for improving pseudo static loop based on negative feedback

Technical Field

The invention relates to a dynamic D trigger based on negative feedback improvement pseudo-static loop.

Background

The conventional CMOS dynamic D flip-flop is different from the CMOS static D flip-flop which requires 4 inverters and 4 transmission gates, while the dynamic D flip-flop retains data by adding an input stage capacitor to store charge. However, if the data input by the next clock beat is different from the stored data, the input stage capacitor may be charged and discharged, which may cause bit errors. To solve the problem of unstable storage charge, the conventional methodThe method maintains charge through the addition of a pseudo-static loop. As shown in fig. 1, a register structure is constructed by adding a small-sized inverter and an inverter in the dynamic D flip-flop. The design of the pseudo static loop greatly improves the noise resistance of the storage node, and the storage node is forced to be locked on 0 or 1 by the positive feedback loop. In fig. 1, a first transmission gate TG1 has one end connected to the input signal D and the other end connected to the input terminals of the first charge storage capacitor C1 and the first inverter INV 1; the other end of the first charge storage capacitor C1 is grounded, the NMOS gate of the first transmission gate TG1 is connected with the first positive clock CLK, and the PMOS gate is connected with the first positive clock CLK

The first inverter INV1 and the input and output of the first feedback inverter SINV1 are connected end to form a register structure with positive feedback. The output end of the first inverter INV1 is connected with the input end of the second transmission gate TG2, and the output end of the second transmission gate TG2 is connected with the second charge storage capacitor C2 and the second inverter INV 2; the second charge storage capacitor is grounded from the other end of C2, and the NMOS gate of the second transmission gate TG2 is connected with the second reverse clock

The PMOS gate is terminated with the first positive clock CLK. The second inverter INV2 and the input and output of the second feedback inverter SINV2 are connected end to form a register structure with positive feedback. The output of the second inverter INV2 is the output Q stage of the dynamic D flip-flop.

However, the addition of a pseudo-static loop also causes corresponding problems. First, the pseudo-static loop increases the setup time of the D flip-flop, thereby increasing the delay of data transmission. The dynamic D trigger has the advantages of simple structure and time delay far smaller than that of other types of D triggers, so that the dynamic D trigger can be widely applied to digital integrated circuits of high-frequency clocks. If the pseudo-static loop design is not reasonable, the delay is increased. Secondly, the pseudo-static loop can locally form a positive feedback closed loop. The local positive feedback loop is broken when different data are written in the previous stage every time, and the charges of the storage nodes are refreshed. If the size of the pseudo-static loop is too large, different data cannot be written into the D flip-flop, thereby disabling the function of the D flip-flop.

Disclosure of Invention

The invention provides a structure based on time sequence control and negative feedback control to solve the problem of a pseudo-static loop of a dynamic D trigger. The inventive structure is shown in fig. 2.

In fig. 2, a first transmission gate TG1 has one end connected to the input signal D and the other end connected to the input terminals of the first charge storage capacitor C1 and the first inverter INV 1; the other end of the first charge storage capacitor C1 is grounded, the NMOS gate of the first transmission gate TG1 is connected with the first forward clock CLK, and the PMOS gate is connected with the second reverse clock

The input end of the first inverter INV1 is connected to the source of the first transistor MOS1, and the drain of the first transistor MOS1 is connected to the output of the third inverter INV 3; an output end of the first inverter INV1 is connected to a drain of the second transistor MOS2, and a source of the second transistor MOS2 is connected to an input of the third inverter INV 3. An input of the third inverter INV3 is connected to the drain of the third transistor MOS3, and an output of the third inverter INV3 is connected to the source of the third transistor MOS 3. The gates of the first and second transistors MOS1 and MOS2 are connected to the second inverted clock

The gate of the third transistor MOS3 is connected to the first forward clock CLK.

The output end of the first inverter INV1 is connected with the input end of the second transmission gate TG2, and the output end of the second transmission gate TG2 is connected with the second charge storage capacitor C2 and the second inverter INV 2; the second charge storage capacitor is grounded from the other end of C2, and the NMOS gate of the second transmission gate TG2 is connected with the second reverse clock

The PMOS gate is terminated with the first positive clock CLK. The input end of the second inverter INV2 is connected to the source of the fourth transistor MOS4, and the drain of the fourth transistor MOS4 is connected to the output of the fourth inverter INV 4; output of second inverter INV2An output terminal is connected to the drain of the fifth transistor MOS5, and a source of the fifth transistor MOS5 is connected to the input of the fourth inverter INV 4. An input of the fourth inverter INV4 is connected to the drain of the sixth transistor MOS6, and an output of the fourth inverter INV4 is connected to the source of the sixth transistor MOS 6. The gate of the fourth transistor MOS4 and the gate of the fifth transistor MOS5 are connected to the first forward clock CLK, and the gate of the sixth transistor MOS6 is connected to the second backward clock

The output of the second inverter INV2 is the output stage Q of the improved dynamic D flip-flop. The arrows in fig. 2 represent the direction of signal transmission, and "+" and "-" represent positive feedback and negative feedback, respectively.

The operation of the dynamic D flip-flop based on negative feedback control is described as follows.

Step 1: when the data is transmitted to the input D end of the dynamic D trigger and the first forward clock CLK is high, the second backward clock

At low, the first transmission gate TG1 is turned on to transmit the D-side data into the dynamic D flip-flop. The first transistor MOS1 and the second transistor MOS2 are turned off, the output stage writing only needs to charge the first charge storage capacitor C1 without breaking the closed loop positive feedback formed by the first inverter INV1 and the third inverter INV3, in the working process, the INV1 adopts a larger width-length ratio, the width-length ratio of the NMOS transistor is about 250 mu m to 0.18 mu m, the width-length ratio of the PMOS transistor is about 500 mu m to 0.18 mu m, the C1 is a parasitic capacitor, the size of the parasitic capacitor is about ten-one-hundred-femtofarads, and therefore additional layout area is not needed. At this time, the third transistor MOS3 is turned on, which is equivalent to short-circuiting the input and output of the third inverter INV3 in principle, and a self-discharging or self-charging negative feedback structure is formed, so that the voltage value of the input and output of the third inverter INV3 is stabilized at half of the power supply voltage, and the voltage signal is transmitted as indicated by the arrow marked with "-" in fig. 2.

Step 2: when the first forward clock CLK is low, the second backward clockClock

At a high level, the first transfer gate TG1 is turned off, the first transistor MOS1 and the second transistor MOS2 are turned on, and the third transistor MOS3 is turned off. At this time, the closed loop negative feedback of the third transistor MOS3 is terminated, and the input and output of the third inverter INV3 are shorted with the output and input of the first inverter INV1, forming a register structure of closed loop positive feedback, thereby stabilizing the charge of the first charge storage capacitor C1. The voltage signal is passed as indicated by the "+" arrows labeled in fig. 2. At this stage, when the written data has a jump, the first inverter INV1 only needs to pull up the input terminal of the third inverter INV3 from half the power voltage to the power supply or to the ground, instead of pulling down from the power supply to the ground or from the ground to the power supply, thereby reducing half the charging and discharging time and reducing the delay of data transmission.

And step 3: when the first forward clock CLK is low, the second backward clock

At high level, the second transmission gate TG2 is turned on, and the signal transmitted to the second transmission gate TG2 is turned on. At this time, the sixth transistor MOS6 is turned on, and the input and output of the fourth inverter INV4 are shorted, so that a self-discharge or self-charge negative feedback structure is formed, and the voltage value of the input and output of the fourth inverter INV4 is stabilized at half of the power supply voltage, thereby reducing the stress of writing data by self-charging or self-discharging.

And 4, step 4: when the first forward clock CLK is high, the second backward clock

When the voltage is low, the second transmission gate TG2 is turned off, and data is transmitted to the output Q of the dynamic D flip-flop. The fourth transistor MOS4 and the fifth transistor MOS5 are turned on, and the sixth transistor MOS6 is turned off. At this time, the closed loop negative feedback of the sixth transistor MOS6 is terminated, and the input and output of the fourth inverter INV4 are shorted with the output and input of the second inverter INV2 to form a register structure of closed loop positive feedback, therebyThe charge of the second charge storage capacitor C2 is stabilized. The voltage signal is passed as indicated by the "+" arrows labeled in fig. 2. At this stage, when the written data has a jump, the second inverter INV2 only needs to pull the input terminal of the fourth inverter INV4 from half the power voltage to the power voltage or from ground to 0 potential, instead of from the power voltage to ground or from ground to the power voltage, which reduces half the charging and discharging time and thus reduces the delay of data transmission.

Advantageous effects

The invention provides a dynamic D trigger structure based on time sequence control and negative feedback control, which is essentially characterized in that a pseudo static loop is greatly optimized, the function of the pseudo static loop is ensured, and the problems of time delay and data writing of the pseudo static loop are solved. Compared with the conventional dynamic D flip-flop, the following advantageous effects are provided.

1. The improved pseudo-static loop is based on time sequence control, and on the basis of guaranteeing data stability, the register structure in a positive feedback loop is avoided from being encountered when data is written in principle. In the conventional D flip-flop structure, in order to ensure data stability, a small-sized inverter is added to form a pseudo-static loop. However, the register structure formed by the end-to-end connection of the two inverters will add difficulty to the writing of data because the input load is no longer a pure capacitor, and a resistor is also included, thereby increasing the requirement on the load capacity of the previous stage and increasing the corresponding delay. According to the invention, the connection between the pseudo static circuit and the main circuit is disconnected in the data writing stage through the control of the time sequence switch, so that the requirement on writing capability is reduced, and the high-speed advantage of the dynamic D trigger is ensured.

2. The improved pseudo-static loop is based on negative feedback control, further reducing the write capability requirements. The first transistor MOS1 is taken as an example and is abbreviated as MOS 1. Physically, the MOS tube constitutes a switch, and the equivalent resistance of the MOS tube is controlled by the grid voltage. When the written data changes, for example, from "0" to "1", the MOS1 with the low gate voltage is in the high impedance state, thereby disconnecting the input of the INV1 and the output of the INV 3. But in practice there is still a slight current through the MOS 1. But through the negative feedback junction of the MOS3Accordingly, the output terminal of the INV3 rapidly changes to half the power supply voltage, and the current passing therethrough can be described by the following equations (1) and (2). R_offThe equivalent resistance when MOS1 is turned off is i, the current flowing through MOS1 is controlled without adding negative feedback, i' is the current flowing through MOS1 with adding negative feedback, and VDD is the power supply voltage.

As is known from equation (1) and equation (2), in principle, the negative feedback control can increase the equivalent resistance of the MOS1 by two times when it is turned off. Thereby further reducing the requirements on write capability.

3. The improved pseudo-static loop is based on negative feedback control, and reduces the delay of data transmission. The second transmission gate TG2 is taken as an example, and abbreviated as TG 2. When the TG2 is turned on, data is output from the first inverter INV1 to the Q terminal through the second inverter INV 2. The main delay is reflected in the time to charge and discharge the capacitance across TG 2. For the second charge storage capacitor C2, keeping strong "1" and strong "0" means keeping the data stable, while the parasitic capacitance at the input of the third inverter INV3 introduces unnecessary delay. In the previous clock cycle when TG2 was on, the negative feedback loop keeps the input and output terminals of the third inverter INV3 at half the supply voltage. When the TG2 is turned on, which is also the second transistor MOS2 is turned on, taking the data change from "0" to "1" at the TG2 as an example, the first inverter INV1 does not need to charge the fan-in capacitance of the third inverter INV3 from 0 to VDD, but from

Charging to VDD reduces the charging time by half, thereby reducing the latency of data transfer.

4. The improved pseudo-static loop is based on time sequence control and negative feedback control, and reduces the size requirement on the pseudo-static loop, thereby reducing the design difficulty. In fig. 1, the size selection of the first feedback inverter SINV1 and the second feedback inverter SINV2 is a dilemma, and if the size selection of the feedback inverters is too large, a register structure with strong positive feedback is formed, and it is difficult for the outside to change the state of the register structure. If the size of the feedback inverter is too small, the charge of the charge storage capacitor is unstable, thereby reducing the stability of data. Based on the architecture in fig. 2, there are two operation states for the first inverter INV1, one is a data write state, where the first transistor MOS1 and the second transistor MOS2 are not conductive, and the INV3 is in a negative feedback state, which reduces the requirement of write capability and the delay of data transmission. The second is a data holding state, at this time, the first transistor MOS1 and the second transistor MOS2 are turned on, and the first inverter INV1 and the third inverter INV3 form a register structure with positive feedback, so that stability of data is maintained. For a designer, the first inverter INV1 and the third inverter INV3 include other transistors, and may have the same size to ensure matching of layout layouts; the size can also be designed flexibly to meet the requirements of different application scenes.

Drawings

FIG. 1 shows a conventional dynamic D flip-flop and a conventional pseudo-static circuit

FIG. 2 is a diagram of the internal structure of a dynamic D flip-flop based on negative feedback pseudo-static loop improvement according to the present invention

FIG. 3 is a 4-bit pseudo-random sequence generator composed of dynamic D flip-flops proposed by the present invention

FIG. 4 is a frequency divider for dividing two frequencies using dynamic D flip-flops according to the present invention

FIG. 5 is a time domain waveform of a pseudo-random sequence generator at a clock signal of 4.95GHz

FIG. 6 is a time domain waveform of a pseudo-random sequence generator at a clock signal of 0.5Hz

FIG. 7 is a time domain waveform of a divide-by-two frequency divider at a clock signal of 5GHz

FIG. 8 is a time domain waveform of a divide-by-two frequency divider at a 0.5Hz clock signal

Fig. 9 is a time domain waveform of a frequency divider formed by a dynamic D flip-flop with a pseudo-static loop removed at a clock signal of 0.5Hz to verify the improvement of the low frequency characteristic of the present invention.

Detailed Description

The dynamic circuit structure improved by the pseudo static loop based on negative feedback control, namely the circuit structure shown in fig. 2, is packaged into a dynamic D flip-flop, which is embodiment 1. And the dynamic D flip-flop is applied to the 4-bit pseudo-random sequence generator in example 2 and the divide-by-two frequency divider in example 3, respectively. Embodiments use a station accumulation TSMC180nm process library for actual design and simulation verification.

Detailed description of the preferred embodiment 1

Specific circuit connections and embodiments of the present invention and device parameters are described below in conjunction with fig. 2.

The invention provides a circuit based on time sequence control and negative feedback control to solve the problem of a pseudo-static loop of a dynamic D trigger. The whole circuit consists of a transmission gate, a charge storage, an inverter and a MOS transistor. The first stored charge C1 and the second stored charge C2 in fig. 2 are replaced by parasitic capacitances of gates in the input stages of the first inverter INV1 and the second INV 2. The parasitic capacitor is used as the capacitor for storing the electric charge, so that the data writing time can be reduced on one hand, and the layout area can be reduced on the other hand.

The connection relationship of the specific embodiment 1 is as follows: a first transmission gate TG1, one end of which is connected to the input signal D and the other end of which is connected to the input end of the first inverter INV 1; the NMOS gate of the first transmission gate TG1 is connected with the first forward clock CLK, and the PMOS gate is connected with the second backward clock

The input end of the first inverter INV1 is connected to the source of the first transistor MOS1, and the drain of the first transistor MOS1 is connected to the output of the third inverter INV 3; an output end of the first inverter INV1 is connected to a drain of the second transistor MOS2, and a source of the second transistor MOS2 is connected to an input of the third inverter INV 3. An input of the third inverter INV3 is connected to the drain of the third transistor MOS3, and an output of the third inverter INV3 is connected to the source of the third transistor MOS 3. First, theThe gate of a transistor MOS1 and the gate of a second transistor MOS2 are connected to the second inverted clock

The output end of the first inverter INV1 is connected with the input end of the second transmission gate TG2, and the output end of the second transmission gate TG2 is connected with the second inverter INV 2; the NMOS gate of the second transmission gate TG2 is connected with the second reverse clock

The PMOS gate is terminated with the first positive clock CLK. The input end of the second inverter INV2 is connected to the source of the fourth transistor MOS4, and the drain of the fourth transistor MOS4 is connected to the output of the fourth inverter INV 4; an output end of the second inverter INV2 is connected to the drain of the fifth transistor MOS5, and a source of the fifth transistor MOS5 is connected to an input of the fourth inverter INV 4. An input of the fourth inverter INV4 is connected to the drain of the sixth transistor MOS6, and an output of the fourth inverter INV4 is connected to the source of the sixth transistor MOS 6. The gate of the fourth transistor MOS4 and the gate of the fifth transistor MOS5 are connected to the first forward clock CLK, and the gate of the sixth transistor MOS6 is connected to the second backward clock

The output of the second inverter INV2 is the output stage Q of the improved dynamic D flip-flop.

The inverters INV1 and INV2 and the transmission gates TG1 and TG2 in the circuit are all composed of one PMOS and one NOMS transistor. The inverters INV3 and INV4 are designed separately, and the NMOS and PMOS of the inverters are both 220.0nm in length and 180.0nm in width. The NMOS and PMOS transistors of inverters INV1, INV2 have a length of 1.95 μm and a width of 180.0 nm. The NMOS and PMOS transistors of the transmission gates TG1 and TG2 are both 1.9 μm in length and 180.0nm in width. The lengths and the widths of the rest MOS transistors are the same, and the lengths and the widths of the rest MOS transistors are 220.0nm and 180.0nm respectively. The detailed parameters of each device are shown in table 1.

TABLE 1 parameter table of each device

The operation of the dynamic D flip-flop feedback upon negative feedback is described below.

Step 2: when the first forward clock CLK is low, the second backward clock

At a high level, the first transmission gate TG1 is turned off, the first transistor MOS1 and the second transistor MOS2 are turned on, and the third transistor MOS3 is turned off. At this time, the closed loop negative feedback of the third transistor MOS3 is terminated, and the input and output of the third inverter INV3 and the first inverter INV1To form a closed loop positive feedback register structure to stabilize the charge of the first charge storage capacitor C1. The voltage signal is passed as indicated by the "+" arrows labeled in fig. 2. At this stage, when the written data has a jump, the first inverter INV1 only needs to pull up the input terminal of the third inverter INV3 from half the power voltage to the power supply or to the ground, instead of pulling down from the power supply to the ground or from the ground to the power supply, thereby reducing half the charging and discharging time and reducing the delay of data transmission.

And 3, step 3: when the first forward clock CLK is low, the second backward clock

At high level, the second transmission gate TG2 is turned on, and the signal transmitted to the second transmission gate TG2 is turned on. At this time, the sixth transistor MOS6 is turned on, and the input and output of the fourth inverter INV4 are shorted, so that a self-discharging or self-charging negative feedback structure is formed, and the voltage value of the input and output of the fourth inverter INV4 is stabilized at half of the power supply voltage, and the pressure of writing data is reduced by self-charging or self-discharging.

When the voltage is low, the second transmission gate TG2 is turned off, and data is transmitted to the output Q of the dynamic D flip-flop. The fourth transistor MOS4 and the fifth transistor MOS5 are turned on, and the sixth transistor MOS6 is turned off. At this time, the closed loop negative feedback of the sixth transistor MOS6 is terminated, and the input and output of the fourth inverter INV4 are shorted with the output and input of the second inverter INV2, thereby forming a closed loop positive feedback register structure, and stabilizing the charge of the second charge storage capacitor C2. The voltage signal is passed as indicated by the "+" arrows labeled in fig. 2. At this stage, when the written data has a jump, the second inverter INV2 only needs to pull the input terminal of the fourth inverter INV4 from half the power voltage to the power voltage or from ground to 0, instead of from the power voltage to ground or from ground to the power voltage, which is reduced by halfThe charging and discharging time is shortened, and the delay of data transmission is reduced.

Example 2

Fig. 3 is a logical structure diagram of pseudo-random sequence generation, in which input D terminals and output Q terminals of a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3 and a fourth D flip-flop DFF4 are cascaded, that is, an output Q1 terminal of the first D flip-flop DFF1 is connected to an input D2 terminal of the second D flip-flop DFF2, an output Q2 terminal of the second D flip-flop DFF2 is connected to an input D3 terminal of the third D flip-flop DFF3, an output Q3 terminal of the third D flip-flop DFF3 is connected to an input D4 terminal of the fourth D flip-flop DFF4, an output Q3 terminal of the third D flip-flop DFF1 and an output Q4 terminal of the fourth flip-flop f4 are connected to an input terminal of an exclusive or gate XOR in the diagram, and an exclusive or operation is performed, and an output XOR input terminal of the exclusive or gate of the first D flip-flop DFF 36 is connected to an input terminal 1 of the exclusive or gate. The clocks of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3 and the fourth D flip-flop DFF4 are connected with a first positive clock CLK with the same frequency, and the output ends Q1, Q2, Q3 and Q4 of the four are signal output ends of a pseudo-random sequence.

The invention has the greatest advantage that the frequency application range of the dynamic D trigger is greatly widened through clock control and negative feedback control. The working frequency of the dynamic D flip-flop mainly refers to the working frequency of a switch inside the D flip-flop controlled by a clock signal. Fig. 5 shows the time domain waveform of the 4-bit pseudo-random sequence generator constructed based on the present invention in a clock period of 202ps, i.e., a clock frequency of 4.95GHz, and it can be known from simulation results that the pseudo-random sequence generator can still work normally under a higher switching frequency close to 5G. Fig. 6 shows that the 4-bit pseudo random sequence formed by the invention occurs in a clock period of 2s and a time domain waveform with a clock frequency of 0.5Hz, and a simulation result shows that under the condition of a low frequency of 0.5Hz, the pseudo static circuit works normally and the data stability of the dynamic D trigger is ensured. Fig. 5 and 6 show that the dynamic D flip-flop improved based on the negative feedback pseudo-static loop according to the present invention has a higher frequency adaptability, and can work normally at low frequency or high frequency.

Example 3

Fig. 4 shows a frequency divider formed by using the dynamic D flip-flop of the present invention. The clock end of the first D flip-flop DFF1 is connected to the first positive clock CLK, the output Q1 is connected to the input end of the first inverter INV1 and the input end of the second inverter INV2, the output end of the first inverter INV1 is connected to the input D1 end of the first D flip-flop, and the output end of the second inverter INV2 is the frequency-divided signal OUT for outputting the first positive clock CLK.

The frequency-divided buffer stage of the second inverter INV2 improves the driving capability of frequency division. Fig. 7 shows the time domain waveforms of a dynamic D flip-flop structure constituting a divide-by-two divider based on negative feedback pseudo-static loop improvement. A high-frequency 5GHz clock signal is input, and a frequency-halving signal of 2.5GHz is output. Fig. 8 shows a clock signal of 0.5Hz as input and a halved frequency signal of 0.25Hz as output. The first transistor MOS1, the second transistor MOS2, the third transistor MOS3, the fourth transistor MOS4, the fifth transistor MOS5, the sixth transistor MO6, the third inverter INV3 and the fourth inverter INV4 in fig. 2 are removed, that is, the pseudo-static circuit is removed, and the dynamic D flip-flop is returned to the conventional dynamic D flip-flop, and is packaged and applied in the divide-by-two frequency divider shown in fig. 4, so that the waveform shown in fig. 9 is obtained, the clock signal of 0.5Hz is input, but an error waveform is output. This means that in the low frequency case, the conventional dynamic D flip-flop loses the trigger function due to the loss of the stored charge, which results in the loss of data. As can be seen from fig. 8 and 9, the low frequency characteristic of the dynamic D flip-flop of the present invention can be significantly improved, and the dynamic D flip-flop has a wider frequency application range.

Claims

1. A dynamic D flip-flop based on negative feedback to improve pseudo-static loop is characterized in that:

a first transmission gate TG1, having one end connected to the input signal D and the other end connected to the first charge storage capacitor C1 and the input end of the first inverter INV 1; the other end of the first charge storage capacitor C1 is grounded, the NMOS gate of the first transmission gate TG1 is connected with the first forward clock CLK, and the PMOS gate is connected with the second reverse clock

The input end of the first inverter INV1 is connected to the source of the first transistor MOS1, and the drain of the first transistor MOS1 is connected to the output of the third inverter INV 3;the output end of the first inverter INV1 is connected to the drain of the second transistor MOS2, and the source of the second transistor MOS2 is connected to the input of the third inverter INV 3; an input of the third inverter INV3 is connected to the drain of the third transistor MOS3, and an output of the third inverter INV3 is connected to the source of the third transistor MOS 3; the gates of the first and second transistors MOS1 and MOS2 are connected to the second inverted clock

The gate of the third transistor MOS3 is connected to the first forward clock CLK;

The grid of the PMOS is connected with the first positive clock CLK; the input end of the second inverter INV2 is connected to the source of the fourth transistor MOS4, and the drain of the fourth transistor MOS4 is connected to the output of the fourth inverter INV 4; an output end of the second inverter INV2 is connected to a drain of the fifth transistor MOS5, and a source of the fifth transistor MOS5 is connected to an input of the fourth inverter INV 4; an input of the fourth inverter INV4 is connected to the drain of the sixth transistor MOS6, and an output of the fourth inverter INV4 is connected to the source of the sixth transistor MOS 6; the gate of the fourth MOS4 and the gate of the fifth MOS5 are connected to the first forward clock CLK, and the gate of the sixth MOS6 is connected to the second backward clock

2. The dynamic D flip-flop based on negative feedback improvement pseudo-static loop of claim 1, wherein:

step 1: when data is transmitted toThe second backward clock is at the input D end of the dynamic D flip-flop when the first forward clock CLK is at high level

At low level, the first transmission gate TG1 is turned on, and data at the D end is transmitted into the dynamic D flip-flop; the first transistor MOS1 and the second transistor MOS2 are turned off, the output stage writing only needs to charge the first charge storage capacitor C1, the third transistor MOS3 is turned on, which is equivalent to short-circuit the input and output of the third inverter INV3, and a self-discharging or self-charging negative feedback structure is formed, so that the voltage value of the input and output of the third inverter INV3 is stabilized at one-half of the power supply voltage;

step 2: when the first forward clock CLK is low, the second backward clock

At a high level, the first transmission gate TG1 is turned off, the first transistor MOS1 and the second transistor MOS2 are turned on, and the third transistor MOS3 is turned off; at this time, the closed-loop negative feedback of the third transistor MOS3 is terminated, the input and output of the third inverter INV3 are shorted with the output and input of the first inverter INV1, a closed-loop positive feedback register structure is formed, and thus the charge of the first charge storage capacitor C1 is stabilized; when the written data jumps, the first inverter INV1 only needs to pull up the input end of the third inverter INV3 from half of the power supply voltage to the power supply or to the ground, so that half of the charging and discharging time is reduced, and the delay of data transmission is reduced;

and step 3: when the first forward clock CLK is low, the second backward clock

At high level, the second transmission gate TG2 is turned on, and the signal transmitted to the second transmission gate TG2 is turned on; at this time, the sixth transistor MOS6 is turned on, short-circuits the input and output of the fourth inverter INV4, and forms a self-discharging or self-charging negative feedback structure, so that the voltage value of the input and output of the fourth inverter INV4 is stabilized at one-half of the power supply voltage,reducing the pressure of writing data by self-charging or self-discharging;

When the voltage is low, the second transmission gate TG2 is turned off, and data is transmitted to the output end Q of the dynamic D flip-flop; the fourth transistor MOS4 and the fifth transistor MOS5 are turned on, and the sixth transistor MOS6 is turned off; at this time, the closed-loop negative feedback of the sixth transistor MOS6 is terminated, and the input and output of the fourth inverter INV4 are shorted with the output and input of the second inverter INV2, so as to form a closed-loop positive feedback register structure, thereby stabilizing the charge of the second charge storage capacitor C2; when the written data jumps, the second inverter INV2 only needs to pull the input terminal of the fourth inverter INV4 from half the power voltage to the power voltage or from the input terminal to the ground 0, which reduces half the charging and discharging time and thus reduces the delay of data transmission.