KR102024470B1 - Low Power Flip-Flop - Google Patents

Abstract

Disclosed is a flip-flop enabling a low power operation and a high speed operation. At a low level of a clock signal, a data signal is stored in a reverse data storage unit of a first circuit unit and, at a high level, a master signal is set. The master signal at the high level is not transmitted to a second circuit unit. The second circuit unit maintains an output of the previous state as an output of the current state through a latch operation. At the high level of the clock signal, the reverse data storage unit generates the master signal and the master signal is generated as the output of the current state through a buffering operation in the second circuit unit.

Description

Low Power Flip-Flop

The present invention relates to a flip-flop, and more particularly, to a flip-flop that can operate at low power and operate at low power even with a quick data change.

A flip-flop is an electronic device that stores one bit of binary information and maintains an output state of a circuit as long as an input signal is not changed. This flip-flop acts as a component of the basic synchronization logic of the microprocessor.

In addition, as the design rule is reduced in the semiconductor manufacturing process, circuits constituting the electronic device require low power driving. This is related to the reduction in the size of the transistor, which is a basic element of the electronic device. Reducing the size of the transistor reduces the spacing of the channel region, thereby creating a path for unwanted current in the channel region in the event of a voltage difference between the source and drain. This is called a short channel effect. In order to prevent the short channel effect, it is necessary to keep the interval of the channel region constant, but there is a problem that the size of the transistor increases. To solve this, a pin-pet has been proposed. The pin-pet has an active region protruding from the surface of the substrate, in which a channel is formed. Therefore, the short channel effect can be prevented while reducing the size of the transistor.

When a transistor is manufactured using a pin-pet or the like, low power driving is possible. In particular, in order to realize low power driving, the transistor needs to be driven at a low voltage. However, when the transistor is driven at a low voltage, the high speed operation is restricted.

When the flip-flop, which is the core circuit of the synchronous logic, is composed of a pin-pet or the like, the flip-flop needs to satisfy the requirements of low power and high speed operation. In particular, semiconductor chips mounted in mobile products have very limited energy use. Among the semiconductor chips used in mobile products, many flip-flop circuits are applied to system on chips (SoCs), and the power consumed by the flip-flop accounts for a large portion of the power consumed by the SoC.

Thus, a flip-flop circuit operating at high speed and low power consumption will be required.

An object of the present invention is to provide a flip-flop capable of low power operation and high speed operation.

According to an aspect of the present invention, a data signal is received, the data signal is stored as an inverted data signal at a low level of a clock signal, and a high level master signal is output at a low level of the clock signal. A first circuit portion for performing; And receiving a master signal of the first circuit unit, generating an output signal of a previous state as an output signal of a current state through a latch operation at a low level of the clock signal, and performing a buffering operation at a high level of the clock signal. Provided is a flip-flop including a second circuit portion for generating a master signal as an output signal.

According to the present invention described above, the change of the data signal D in the section where the clock signal CK is at the low level does not affect the master signal M by the master signal generator. That is, regardless of the level of the data signal D in the section where the clock signal CK is at the low level, the master signal M is set to the high level, the second circuit unit does not transmit the master signal M, and maintains the output signal of the previous state.

In addition, the change of the data signal D in the section where the clock signal CK is at the high level is blocked by the operation of the input unit of the first circuit section. The input unit of the first circuit unit does not transmit the data signal D to the inverted data storage unit in a section where the clock signal CK is at a high level.

In addition, the data signal D is stored in the form of the inverted data signal / D in the inversion data storage unit in the low level period of the clock signal CK. The stored inverted data signal / D may turn on the seventh transistor M7 of the inverted data storage unit in the high level period of the clock signal CK that follows, thereby switching the master signal M to a low level. That is, the data signal D is stored, and the stored signal does not appear directly as the master signal M, but is input to the gate terminal of the transistor and used to generate the master signal M. This can reduce power consumption and enable high-speed operation.

1 is a circuit diagram illustrating a flip-flop according to a preferred embodiment of the present invention.
2 is an equivalent circuit diagram of FIG. 1 when the clock signal is at a low level according to a preferred embodiment of the present invention.
3 is an equivalent circuit diagram of FIG. 1 when the clock signal is at a high level according to a preferred embodiment of the present invention.
4 is a timing diagram illustrating an operation of the flip flop of FIG. 1 according to an exemplary embodiment of the present invention.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a circuit diagram illustrating a flip-flop according to a preferred embodiment of the present invention.

Referring to FIG. 1, the flip-flop according to the present embodiment receives a data signal D, a first circuit unit 100 for generating a master signal M, and a second circuit unit for receiving a master signal M, and generating an output signal Q. Has 200.

The first circuit unit 100 and the second circuit unit 200 use only one clock CK as a clock signal. In addition, the first circuit unit 100 and the second circuit unit 200 are supplied with a positive power supply voltage VDD and a negative power supply voltage VSS in a rail-to-rail type. 1 and the other drawings below, the positive power supply voltage VDD may be referred to as high level, and the negative power supply voltage VSS may be described as low level or equivalent to ground.

In addition, the first circuit unit 100 stores the data signal D of the current state at the low level of the clock signal CK as / D, which is an inverted data signal, and outputs the master signal M at a high level. That is, the master signal M is output at a high level while the clock signal CK is at a low level.

If the clock signal CK is at the high level, the first circuit unit 100 maintains the storage of the inverted data signal / D stored in the previous state, and the master signal M is provided only when the data signal D in the previous state is at the low level. Output the low level in the current state. If the data signal D is at the high level in the previous state, the master signal M is at the high level in the current state.

As a result, the first circuit unit 100 outputs a low level only when the data signal D input in the low level section, which is the previous state, in the current section in which the clock signal CK rises to the high level. In addition, the first circuit unit 100 stores the data signal D input in a section in which the clock signal CK is at a low level in the form of an inverted data signal / D. In the period where the clock signal CK is at a high level, the variation of the data signal D is not stored or transmitted.

When the clock signal CK is at the low level, the second circuit unit 200 maintains the output signal Q formed in the previous state by the storage operation according to the latch structure. In addition, when the clock signal CK is at a high level, the second circuit unit 200 forms a master signal M, which is input through a buffering operation, as an output signal Q.

For the above-described operation, the first circuit unit 100 includes an input unit 110, a master signal generator 120, and an inverted data storage unit 130.

The input unit 110 has a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

The first transistor M1 is connected between the positive power supply voltage VDD and the second transistor M2 and has a configuration of a PMOS. In addition, the source terminal of the first transistor M1 is connected to the positive power supply voltage VDD, the drain terminal is connected to the second transistor M2, and the input signal D is applied to the gate terminal.

In addition, the second transistor M2 is connected between the first transistor M1 and the first node N1, has a configuration of a PMOS, and receives a clock signal CK. To this end, the source terminal of the second transistor M2 is connected to the drain terminal of the first transistor, the clock signal CK is applied to the gate terminal, and the source terminal is connected to the first node N1.

The third transistor M3 is connected between the first node N1 and the fourth transistor M4 and is composed of an NMOS. The drain terminal of the third transistor is connected to the first node N1, the source terminal is connected to the fourth transistor M4, and the master signal M of the second node N2 is applied to the gate terminal.

The fourth transistor M4 is connected between the third transistor M3 and the negative power supply voltage VSS and has a configuration of an NMOS. The drain terminal of the fourth transistor M4 is connected to the third transistor M3, the data signal D is applied to the gate terminal, and the source terminal is connected to the negative power supply voltage VSS.

The input unit 110 transmits the data signal D to the inverted data storage unit 130 through the inverter configuration by the clock signal CK, or the inverter configuration is released to block the transmission of the data signal D.

If the clock signal CK is at a low level, the second transistor M2 is turned on, and the third transistor M3 is also turned on by the turned-on fifth transistor M5 so that the input unit 110 forms an equivalent circuit with the inverter. Therefore, at the low level of the clock signal CK, the input signal D transfers the inverted data signal / D to the inverted data storage 130.

If the clock signal CK is at a high level, the second transistor M2 is turned off. Therefore, the change in the level of the data signal D does not cause the change in the level of the first node N1. It can be understood that the data signal D is not substantially transmitted to the first node N1. Therefore, in the period where the clock signal CK is at the high level, the data signal D is blocked from being transferred to the inverted data storage unit 130, and the inverted data storage unit 130 is the inverted data signal / D input at the low level in the previous state. Keep the store.

The master signal generator 120 is composed of a fifth transistor M5 which is a PMOS, a source terminal is connected to a positive power supply voltage VDD, a clock signal CK is applied to a gate terminal, and a drain terminal is connected to a second node N2. . If the clock signal CK is at the low level, the fifth transistor M5 is turned on and the positive power supply voltage VDD is output to the second node N2 to form a high level master signal M.

In addition, when the clock signal CK is at a high level, the fifth transistor M5 is turned off. By the fifth transistor M5 turned off, the second node N2 maintains the high level set at the low level of the clock signal CK in the previous state, or according to the inverted data signal / D of the previous state stored in the inversion data storage unit 130. Can be set to a low level. If the inverted data signal / D maintained in the previous state is at the high level, the second node N2 is set at the low level and the master signal M is set at the low level.

The inversion data storage unit 130 has a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a first inverter INV1.

The sixth transistor M6 is connected between the first node N1 and the third node N3 and is composed of an NMOS. The drain terminal of the sixth transistor M5 is connected to the first node N1, the gate terminal is connected to the output terminal of the first inverter INV1, and the source terminal is connected to the third node N3.

The seventh transistor M7 is connected between the second node N2 and the third node N3 and is composed of NMOS. The drain terminal of the seventh transistor M7 is connected to the second node N2, the gate terminal is connected to the first node N1, and the source terminal is connected to the third node N3.

In addition, the eighth transistor is connected between the third node N3 and the negative power supply voltage VSS, and is composed of an NMOS. The clock signal CK is applied to the gate terminal of the eighth transistor M8, the drain terminal is connected to the third node N3, and the source terminal is connected to the negative power supply voltage VSS.

When the clock signal CK is at the low level, the third node N3 is disconnected from the negative power supply voltage VSS. In addition, the data signal D applied from the input unit 110 is stored in the second node N2 in the form of the data signal / D inverted through the configuration of the inverter. If the second node N2 is at the high level, the seventh transistor M7 may be turned on, but this does not affect the level of the second node N2, and when the second node N2 is at the low level, the first inverter INV1 may be turned on. The sixth transistor M6 is turned on but remains at a low level. Therefore, while the clock signal CK is at the low level, the inversion data storage unit 130 stores the data signal D applied in the current state in the form of the inverted data signal / D.

If the clock signal CK is at a high level, the third node N3 is set to a low level by turning on the eighth transistor M8. Transmission of the data signal D applied in the current state from the input unit 110 is also cut off. Thus, the inverted data signal / D stored in the previous state stored in the first node N1 is maintained. However, when the inverted data signal / D stored in the previous state is at the high level, the seventh transistor M7 is turned on and the master signal M of the second node N2 is output at the low level.

The second circuit unit 200 has a variable inverter unit 210 and a latch unit 220.

The variable inverter unit 210 includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.

The ninth transistor M9 is disposed between the positive power supply voltage VDD and the fourth node N4 and receives the master signal M. The source terminal of the ninth transistor M9 is connected to the positive power supply voltage VDD, the source terminal is connected to the fourth node N4, and the master signal M is applied to the gate terminal. Preferably, the ninth transistor M9 is composed of a PMOS.

The tenth transistor M10 is an NMOS connected between the fourth node N4 and the fifth node N5 and receives a clock signal CK. The drain terminal of the tenth transistor M10 is connected to the fourth node N4, the clock signal CK is applied to the gate terminal, and the source terminal is connected to the fifth node N5.

The eleventh transistor M11, which is an NMOS, is connected between the fifth node N5 and the negative power supply voltage VSS and receives the master signal M of the second node N2. To this end, the drain terminal of the eleventh transistor M11 is connected to the fifth node N5, the gate terminal is connected to the second node N2, and the source terminal is connected to the negative power supply voltage VSS.

The latch unit 220 has a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a second inverter INV2.

The twelfth transistor M12 is connected between the positive power supply voltage VDD and the thirteenth transistor M13 and has a configuration of a PMOS. The source terminal of the twelfth transistor is connected to the positive power supply voltage VDD, the clock signal CK is applied to the gate terminal, and the drain terminal is connected to the source terminal of the thirteenth transistor M13.

The thirteenth transistor M13 is connected between the twelfth transistor M12 and the fourth node N4 and has a configuration of a PMOS. The output signal Q is applied to the gate terminal of the thirteenth transistor M13, the source terminal is connected to the drain terminal of the twelfth transistor M12, and the drain terminal is connected to the fourth node N4.

The fourteenth transistor M14 is connected between the fourth node N4 and the fifth node N5 and has a configuration of an NMOS. In addition, the drain terminal of the fourteenth transistor M14 is connected to the fourth node N4, the output signal Q is applied to the gate terminal, and the source terminal is connected to the fifth node N5.

The second inverter INV2 inverts the signal of the fourth node N4 to form the output signal Q. The second inverter INV2 has a latch configuration together with the thirteenth transistor M13 and the fourteenth transistor M14.

The tenth transistor M10 of the variable inverter unit 210 is turned off in the section where the clock signal CK is at the low level. Thus, the ninth transistor M9 and the eleventh transistor M11 do not constitute an inverter. In addition, the master signal M, which is the output of the first circuit unit 100, outputs only the high level regardless of the level of the data signal D in the period where the clock signal CK is at the low level. Thus, the eleventh transistor M11 is turned on and the fifth node N5 is set to the negative power supply voltage VSS. The twelfth transistor M12 is also turned on by the clock signal CK having the low level. Through this, the latch structures of the thirteenth transistor M13, the fourteenth transistor M14, and the second inverter INV2 are completed, and the signal stored in the previous state is output as the output signal Q in the current state. That is, the master signal M is not transmitted to the second circuit unit 200 in the period where the clock signal CK is at the low level, and the second circuit unit 200 converts the data stored and output in the previous state into the output signal Q through a latch operation. Form.

If the clock signal CK is at a high level, the tenth transistor M10 of the variable inverter unit 210 is turned on, and the variable inverter unit 210 completes the inverter structures of the ninth transistor M9 and the eleventh transistor M11. Since the second inverter INV2 is connected to the fourth node N4 of the variable inverter unit 210 in which the inverter structure is completed, the variable inverter unit 210 and the second inverter INV form a buffer structure. Therefore, in the period where the clock signal CK is at the high level, the master signal M, which is the output of the first circuit unit 100, forms the output signal Q.

2 is an equivalent circuit diagram of FIG. 1 when the clock signal is at a low level according to a preferred embodiment of the present invention.

Referring to FIG. 2, when the clock signal CK is at a low level, the second transistor M2 and the fifth transistor M5 of FIG. 1 are turned on and the eighth transistor M8 is turned off. Accordingly, the input unit 110 has an inverter structure, and the second node N2 receives the positive power supply voltage VDD and the master signal M is set to a high level. In addition, the inverted data signal / D, which is the output of the input unit 110, is applied to the first node N1.

The inverted data signal / D is stored in the first node N1, and more specifically, in the form of electric charge in the input terminal of the first inverter INV1 and the gate terminal of the seventh transistor M7. In the structure of the transistor, a gate dielectric layer may be formed between the gate and the source, may form a predetermined capacitance, and may have a charge storage capability. In addition, since the first node N1 may be formed of metal wires in the semiconductor manufacturing process, charges may be stored through the metal wires. When storing the inverted data signal / D, the current path directly from the positive power supply voltage VDD to the negative power supply voltage VSS does not appear, and power consumption is only caused by the inverter operation of the input unit 110 and the operation of the first inverter INV1. Is generated. Therefore, the power consumption can be extremely reduced in the storage operation of the input signal / D inverted at the low level of the clock signal CK.

In addition, since the third node N3 is in a floating state, the second node N2 outputs a high level regardless of whether the seventh transistor M7 is on or off. That is, in the period where the clock signal CK is at the low level, the master signal M is set to a high level regardless of the level of the data signal D.

When the master signal M is set to the high level, the eleventh transistor M11 of the variable inverter unit 210 of the second circuit unit 200 is turned on and the fifth node N5 is set to the negative power supply voltage VSS. The tenth transistor M10 is turned off and the twelfth transistor M12 is turned on by the clock signal CK having the low level. Therefore, a positive power supply voltage is applied to the source terminal of the thirteenth transistor M13, and a negative power supply voltage VSS is applied to the source terminal of the fourteenth transistor M14. As a result, the latch structure of the latch unit 220 is completed. Accordingly, the master signal M is not transmitted to the fourth node N4, and the latch unit 220 forms the output signal Q as data output and stored in the previous state.

After all, when the clock signal CK is at the low level, the first circuit unit 100 stores the data signal D as the inverted data signal / D and outputs the high level master signal M. In addition, the latch structure of the second circuit unit 200 is completed, and the high level master signal M contributes only to the completion of the latch structure of the second circuit unit 200 and does not act as an input of the latch unit 220. Accordingly, the second circuit unit 200 generates data output and stored in the latch unit 220 as the output signal Q in the previous state.

3 is an equivalent circuit diagram of FIG. 1 when the clock signal is at a high level according to a preferred embodiment of the present invention.

Referring to FIG. 3, the second transistor M2 and the fifth transistor M5 are turned off by the clock signal CK having the high level. Therefore, the positive power supply voltage VDD supplied to the second node N2 is cut off. In addition, the eighth transistor M8 is turned on and the third node N3 is connected to the negative power supply voltage VSS.

Regardless of the level of the data signal D, the first node N1 maintains the inverted input signal / D stored in the previous state. When looking at the first inverter INV1 and the sixth transistor M6 at the first node N1, it is interpreted that the two inverters are connected in series and form a loop. Thus, the signal previously stored at the first node N1 is stored via a latch operation.

The seventh transistor M7 is the only path that forms the signal of the second node N2. Accordingly, the master signal M, which is a signal of the second node N2, may be set to a low level by turning on the seventh transistor M7, and may maintain the high level set to the previous state when the seventh transistor M7 is in an off state. This can be interpreted from another viewpoint in the circuit diagram of FIG. 1, and the seventh transistor M7 and the eighth transistor M8 constitute a NAND circuit. The output terminal is the second node N2. That is, when the clock signal CK is at the high level, the value of the NAND operation of the signal of the first node N1 and the clock signal CK is output to the second node N2 at the second node N2. Therefore, when the clock signal CK is high level, the low level signal appears at the second node N2 only when the signal of the first node N1 is high level and is output in the form of the master signal M. If the signal of the first node N1 is at the low level, the signal of the second node N2 shown in the previous state is maintained and the high level is output.

That is, in the period where the clock signal CK is at the high level, the data signal D is cut off from the inverted data storage 130 through the input unit 100. In addition, the inversion data storage unit 130 maintains the storage of the inverted data signal / D stored in the previous state. If the inverted data signal / D stored in the previous state is a low level, the master signal M maintains a high level, and if the inverted data signal / D stored in the previous state is a high level, the inverted data storage unit 130 The second node N2 is switched to the low level, and a low level master signal M is generated.

In addition, the second circuit unit 200 has a configuration of a buffer in which two inverters are connected in series.

Since the clock signal CK is at a high level, the tenth transistor M10 of the variable inverter unit 210 is turned on. Thus, the ninth transistor M9 and the eleventh transistor M11 constitute an inverter. In addition, the second inverter INV2 is connected to the variable inverter unit 210 in series to configure a buffer. Therefore, the master signal M forms the output signal Q in a section where the clock signal CK is at a high level.

4 is a timing diagram illustrating an operation of the flip flop of FIG. 1 according to an exemplary embodiment of the present invention.

Hereinafter, a description will be given with reference to FIGS. 1 to 3 with reference to FIG. 4.

The clock signal CK is at the low level below the initial time T0, and the data signal D is also at the low level. Thus, the first node N1 receives and stores the high level inverted data signal / D. In addition, the master signal M which is the output of the second node N2 of the first circuit unit 100 is set to a high level. Since the clock signal CK is at a low level, the second circuit unit 200 performs a latch operation. Thus, the output signal Q outputs a low level.

Between time T0 to T1, clock signal CK has a high level, and data signal D transitions from low level to high level. On the other hand, since the input unit 110 of the first circuit unit 100 does not transmit the data signal D, the first node N1 maintains the high level stored in the previous state. Since the first node N1 is high level, the seventh transistor M7 is turned on, and the master signal M of the second node N2 transitions to a low level. In addition, since the second circuit unit 200 performs the buffering operation, the low level master signal M is represented by the low level output signal Q.

Between time T1 and T2, clock signal CK has a low level, and data signal D maintains a high level. The data signal D is stored as the data signal / D inverted by the inversion data storage unit 130 of the first circuit unit 100 by the low level clock signal CK. Thus, the first node N1 transitions to a low level, and the master signal M of the second node N2 is set to a high level. Since the master signal M is at a high level, the second circuit unit 200 performs a latch operation. Therefore, the output signal Q remains at the previous state and has a low level.

Between the times T2 to T3, the clock signal CK has a high level and the data signal D maintains a high level. Since the low level is stored in the first node N1 in the previous state, the master signal M of the second node N2 maintains the high level. In addition, since the second circuit unit 200 performs the buffering operation, the second circuit unit 200 receives the high level master signal M to form the high level output signal Q.

The clock signal CK has a low level between the times T3 to T4, and the data signal D transitions from the high level to the low level. Thus, the signal stored in the first node N1 transitions from the low level to the high level. On the other hand, the second node N2 is set to a high level by the turned-on master signal generator 120. The high level master signal M is not transmitted to the second circuit unit 200, and the second circuit unit 200 forms a high level of the previous state as the output signal Q through a latch operation.

Between time T4 and T5, clock signal CK has a high level and data signal D has a low level. Since the data signal D is not transmitted to the inverted data storage 130, the first node N1 maintains the high level of the previous state. However, the seventh transistor M7 of the inversion data storage unit 130 is turned on, and the second node N2 generates the master signal M having a low level. In addition, since the second circuit unit 200 performs a buffering operation, the output signal Q is switched to the low level by the low level master signal M. FIG.

Between time T5 and T6, clock signal CK has a low level and data signal D maintains a low level. Since the clock signal CK is at the low level, the first node N1 stores the high level signal. In addition, the master signal M of the second node N2 is switched to the high level. Since the second circuit unit 200 performs the latch operation, the second circuit unit 200 generates the low level output of the previous state as the output signal Q.

In the above-described operation of the flip-flop, the first circuit unit stores the input data signal D in the inverted data storage unit in the form of the inverted data signal / D during the low level period of the clock signal CK. In addition, the master signal M, which is the output of the first circuit portion, is output at a high level regardless of the data signal D.

In addition, the variable inverter part of the second circuit part does not transmit the master signal M to the latch part by the low level clock signal CK, and performs only a latch operation. Thus, the second circuit portion generates the output signal transmitted and output in the previous state as the output signal Q in the current state.

In addition, when the clock signal CK has a high level, the data signal D is not transmitted to the inversion data storage unit, and the inversion data storage unit sets the master signal M of the second node N2 according to the data stored in the previous state. For example, when the data of the first node N1 is at the high level at the time when the clock signal CK in the previous state is transitioned to the high level in the current state, the inversion data storage unit low-levels the master signal M of the second node N2. When the signal stored in the first node N1 is at the low level, the master signal M of the second node N2 is maintained at the high level. This means that when the clock signal CK is at the low level, the stored data is used to generate the master signal at the high level of the clock signal CK. That is, the low level data in the previous state is stored at the high level in the inversion data storage, and the master signal M is converted to the low level in the current state where the clock signal CK is at the high level.

In addition, the variable inverter of the second circuit part transmits the master signal M to the latch part through the inverter operation by the high level clock signal CK. Since the latch unit performs the inversion operation, the second circuit unit performs the buffering operation as a whole. This implements a data storage operation of the flip flop.

In addition, in the present invention, the change of the data signal D in the section where the clock signal CK is at the low level does not affect the master signal M by the master signal generator. That is, regardless of the level of the data signal D in the section where the clock signal CK is at the low level, the master signal M is set to the high level, the second circuit unit does not transmit the master signal M, and maintains the output signal of the previous state.

In addition, the change of the data signal D in the section where the clock signal CK is at the high level is blocked by the operation of the input unit of the first circuit section. The input unit of the first circuit unit does not transmit the data signal D to the inverted data storage unit in a section where the clock signal CK is at a high level.

In addition, the data signal D is stored in the form of the inverted data signal / D in the inversion data storage unit in the low level period of the clock signal CK. The stored inverted data signal / D may turn on the seventh transistor M7 of the inverted data storage unit in the high level period of the clock signal CK that follows, thereby switching the master signal M to a low level. That is, the data signal D is stored, and the stored signal does not appear directly as the master signal M, but is input to the gate terminal of the transistor and used to generate the master signal M. This can reduce power consumption and enable high-speed operation.

100: first circuit unit 110: input unit
120: master signal generator 130: inverted data storage unit
200: second circuit portion 210: variable inverter portion
220: latch portion

Claims (15)

A first circuit unit for receiving a data signal, storing the data signal in the form of an inverted data signal at a low level of a clock signal, and outputting a high level master signal at a low level of the clock signal; And
Receiving the master signal of the first circuit portion, and generates an output signal of the previous state as an output signal of the current state through a latch operation at a low level of the clock signal, or the buffering operation at a high level of the clock signal A second circuit portion for generating a signal as an output signal,
The first circuit unit,
A data signal connected between an input terminal of the data signal and a first node and inverting the data signal at a low level of the clock signal to output an inverted data signal to the first node, or at a high level of the clock signal; An input unit for maintaining a state of a node;
It is connected between the positive power supply voltage and the second node that the master signal is generated, receives the positive power supply voltage at the low level of the clock signal and outputs the high level master signal to the second node, A master signal generator for disconnecting a positive power voltage from a second node in the clock signal at a level; And
A connection between the first node and the second node, storing the inverted data signal of the first node at a low level of the clock signal, and storing the data signal of a previous state at a high level of the clock signal; And a reverse data storage unit outputting the master signal to the second node. delete delete delete The method of claim 1, wherein the input unit
A first transistor coupled to a positive power supply voltage for receiving said data signal through a gate terminal;
A second transistor connected between the first transistor and the first node and configured to receive the clock signal and perform an on / off operation;
A third transistor connected to the first node and configured to receive the master signal and perform an on / off operation; And
And a fourth transistor coupled between the third transistor and a negative power supply voltage and receiving the data signal through a gate terminal. The method of claim 1, wherein the master signal generator
Connected between a positive supply voltage and a second node, receiving the clock signal, being turned on at a low level of the clock signal to set the master signal to a high level, or turned off at a high level of the clock signal; A flip-flop comprising 5 transistors. The data storage device of claim 1, wherein the inversion data storage unit is configured.
A first inverter for inverting the inverted data signal stored in the first node;
A sixth transistor configured to receive an output signal of the first inverter and be coupled between the first node and a third node;
A seventh transistor connected between the second node and the third node and receiving the inverted data signal stored in the first node; And
And an eighth transistor coupled between the third node and a negative power supply voltage and configured to receive the clock signal. 8. The method of claim 7, wherein if the inverted data signal stored at the first node at the high level of the clock signal is at the high level, the seventh transistor is turned on and the master signal of the second node transitions to the low level. Flip-flop, characterized in that. The method of claim 1, wherein the second circuit portion
A variable inverter unit for receiving the master signal, selectively inverting and outputting the master signal to a fourth node; And
And a latch unit for inverting or storing the signal of the fourth node through a latch operation to generate an output signal. The flip-flop of claim 9, wherein the variable inverter unit does not transmit the master signal to the fourth node at a low level of the clock signal. The flip-flop according to claim 10, wherein the latch unit performs a latch operation for outputting and maintaining an output signal of a previous state as an output signal of a current state at a low level of the clock signal. The method of claim 9, wherein the second circuit unit buffers the master signal at a high level of the clock signal to form an output signal.
The variable inverter unit inverts the master signal at a high level of the clock signal and transfers the master signal to the fourth node, and the signal of the fourth node is inverted by the latch unit to form the output signal. Flop. The method of claim 9, wherein the variable inverter unit
A ninth transistor coupled between a positive power supply voltage and the fourth node and configured to receive the master signal;
A tenth transistor connected between the fourth node and a fifth node and configured to receive the clock signal and perform an on / off operation; And
And an eleventh transistor connected between the fifth node and a negative power supply voltage and receiving the master signal. The method of claim 13, wherein the tenth transistor is turned on at a high level of the clock signal, and the ninth transistor and the eleventh transistor form an inverter structure to invert and output the master signal to the fourth node. Featuring flip flops. The flip-floor of claim 13, wherein the tenth transistor is turned off at the low level of the clock signal, and the variable inverter unit releases the inverter configuration to release the master signal to the fourth node. Flop.

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