CN102427363A - Multiphase multimode frequency-dividing circuit with small frequency coefficient - Google Patents
Multiphase multimode frequency-dividing circuit with small frequency coefficient Download PDFInfo
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- CN102427363A CN102427363A CN2011104408054A CN201110440805A CN102427363A CN 102427363 A CN102427363 A CN 102427363A CN 2011104408054 A CN2011104408054 A CN 2011104408054A CN 201110440805 A CN201110440805 A CN 201110440805A CN 102427363 A CN102427363 A CN 102427363A
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Abstract
The invention discloses a multiphase multimode frequency-dividing circuit with a small frequency coefficient, comprising two control ends and four D triggers, wherein the NAND logical signals of the output signals of the third D trigger and the fourth D trigger are served as the input signals of the first D trigger; the NAND logical signals of the control signal of the first control end and the output signal of the third D trigger, and the logical AND of the output signal of the first D trigger are served as the input signals of the second D trigger; the output signal of the second D trigger is served as the input signal of the third D trigger; the logical NOT of the output signal of the third D trigger and the NAND logical signal of the control signal of the second control end are served as the input signal of the fourth D trigger; and the output signal of the first D trigger is served as the output signal of the multiphase multimode frequency-dividing circuit.
Description
Technical field
The present invention relates to a kind of frequency dividing circuit, design a kind of heterogeneous multimode frequency dividing circuit of little divide ratio especially.
Background technology
Clock exhibition technology frequently is the important way of a kind of reduction EMI of system (electromagnetic interference), and the divide ratio of the frequency dividing circuit that adopts usually at present is higher, does not wait from tens to several thousand.Also require low system EMI in TFT-LCD (thin-film transistor-LCDs) display system, except that the mode that adopted system design, utilize have in the TFT-LCD display system exhibition frequently time schedule controller (TCON) chip of function also be a kind of important solutions.But in this application system, the divide ratio of clock multiplier system is very low to be a special system requirements, and this gives the band exhibition new requirement of clock multiplier system proposition of function frequently.For the clock multiplier system, require frequency dividing circuit wherein to satisfy following two requirements: the one, frequency dividing circuit must dynamically switch in 3 kinds of frequency dividing ratios, and insensitive to the sequential of switching signal; The 2nd, the operating frequency of frequency dividing circuit is high as far as possible, so the structure of frequency dividing circuit should be tried one's best simply, feedback path is short as far as possible.
Summary of the invention
In order to solve the problems referred to above of prior art, the purpose of this invention is to provide a kind of heterogeneous multimode frequency dividing circuit of little divide ratio, so that frequency dividing circuit can dynamically switch in 3 kinds of frequency dividing ratios, and also insensitive to the sequential of switching signal.
To achieve these goals, the invention provides a kind of heterogeneous multimode frequency dividing circuit of little divide ratio, said heterogeneous multimode frequency dividing circuit comprises two control ends and four d type flip flops, wherein,
The NAND logical signal of the output signal of the 3rd d type flip flop and the 4th d type flip flop is as the input signal of first d type flip flop;
The logical AND of the NAND logical signal of the output signal of the control signal of first control end and said the 3rd d type flip flop and the output signal of said first d type flip flop is as the input signal of second d type flip flop;
The output signal of said second d type flip flop is as the input signal of said the 3rd d type flip flop;
The NAND logical signal of the logic NOT of the output signal of said the 3rd d type flip flop and the control signal of second control end is as the input signal of said the 4th d type flip flop;
The output signal of said first d type flip flop is as the output signal of said heterogeneous multimode frequency dividing circuit.
As preferably, the output of said the 3rd d type flip flop and the 4th d type flip flop is connected two inputs of first NAND gate, and the output of this first NAND gate connects the input of said first d type flip flop; The output of said the 3rd d type flip flop is connected two inputs of second NAND gate with said first control end; The output of this second NAND gate is connected two inputs with door with the output of said first d type flip flop, should be with the output of door be connected the input of said second d type flip flop; The output of said second d type flip flop connects the input of said the 3rd d type flip flop; The output of said the 3rd d type flip flop connects the input of an inverter; The output of this inverter is connected two inputs of the 3rd NAND gate with said second control end, the output of the 3rd NAND gate connects the input of said the 4th d type flip flop.
As preferably, saidly be integrated in said second d type flip flop with door.
As preferably, when the control signal of said first control end was 0, the control letter of said second control end was 0 or 1; When the control signal of said first control end was 1, the control letter of said second control end was 0.
Compared with prior art, the present invention has following beneficial effect: the heterogeneous multimode frequency dividing circuit of little divide ratio provided by the invention can be dynamically removes 6/ and remove in 7 these 3 kinds of frequency dividing ratios and switch removing 5/, and insensitive to the sequential of switch-over control signal; Through improvement to the concrete implementation of circuit, make the simple in structure of frequency dividing circuit, feedback path is short, improves the operating frequency of frequency dividing circuit.
Description of drawings
Fig. 1 is the structural representation of heterogeneous multimode frequency dividing circuit of the present invention.
Fig. 2 is that heterogeneous multimode frequency dividing circuit shown in Figure 1 is worked as k1=0, the structural representation during k2=0.
Fig. 3 is that heterogeneous multimode frequency dividing circuit shown in Figure 1 is worked as k1=0, the structural representation during k2=1.
Fig. 4 is the structural representation of heterogeneous multimode frequency dividing circuit when k2=0 shown in Figure 1.
Fig. 5 be in the heterogeneous multimode frequency dividing circuit shown in Figure 1 with a kind of implementation of door and second d type flip flop.
Fig. 6 be in the heterogeneous multimode frequency dividing circuit shown in Figure 1 with the another kind of implementation of door and second d type flip flop.
Embodiment
Below in conjunction with accompanying drawing specific embodiment of the present invention is elaborated.
Embodiment one:
Fig. 1 is the structural representation of heterogeneous multimode frequency dividing circuit of the present invention.As shown in Figure 1, heterogeneous multimode frequency dividing circuit of the present invention comprises two control ends and four d type flip flops, wherein,
The output signal Q3 of the 3rd d type flip flop D3 and the 4th d type flip flop D4, the NAND logical signal of Q4 are as the input signal of first d type flip flop D1;
The logical AND of the NAND logical signal of the output signal Q3 of the control signal k1 of first control end and the 3rd d type flip flop D3 and the output signal Q1 of first d type flip flop D1 is as the input signal of second d type flip flop D2;
The output signal Q2 of second d type flip flop D2 is as the input signal of the 3rd d type flip flop D3;
The NAND logical signal of the logic NOT of the output signal Q3 of the 3rd d type flip flop D3 and the control signal k2 of second control end is as the input signal of the 4th d type flip flop D4;
The output signal Q1 of first d type flip flop D1 is as the output signal Out of said heterogeneous multimode frequency dividing circuit.
In the present embodiment, the output of the 3rd d type flip flop D3 and the 4th d type flip flop D4 is connected two inputs of first NAND gate, and the output of this first NAND gate connects the input of first d type flip flop D1; The output of the 3rd d type flip flop D3 is connected two inputs of second NAND gate with first control end; The output of the output of this second NAND gate and first d type flip flop D1 is connected two inputs with door, should be with the output of door be connected the input of second d type flip flop D2; The output of second d type flip flop D2 connects the input of the 3rd d type flip flop D3; The output of the 3rd d type flip flop D3 connects the input of an inverter, and the output of this inverter is connected two inputs of the 3rd NAND gate with second control end, and the output of the 3rd NAND gate connects the input of the 4th d type flip flop D4.
Fig. 2 is that heterogeneous multimode frequency dividing circuit shown in Figure 1 is worked as k1=0, the structural representation during k2=0.As shown in Figure 2, work as k1=0, during k2=0, heterogeneous multimode frequency dividing circuit of the present invention can be realized removing 6 function, and wherein the output signal Q4 of the 4th d type flip flop D4 is constantly equal to 1, and the conversion process of the output signal Q1 of other three d type flip flops, Q2, Q3 is:
Fig. 3 is that heterogeneous multimode frequency dividing circuit shown in Figure 1 is worked as k1=0, the structural representation during k2=1.As shown in Figure 3, work as k1=0, during k2=1, heterogeneous multimode frequency dividing circuit of the present invention can be realized removing 7 function, and the conversion process of the output signal Q1 of four d type flip flops, Q2, Q3, Q4 is:
Fig. 4 is the structural representation of heterogeneous multimode frequency dividing circuit when k2=0 shown in Figure 1.As shown in Figure 4, when k2=0,, can realize removing 5 and remove 6 function respectively through regulating k1; When k1=0, the circuit structure among its circuit structure and Fig. 2 is identical, can realize removing 6 function; When k1=1, can realize removing 5 function, wherein the output signal Q4 of the 4th d type flip flop D4 is constantly equal to 1, and the conversion process of the output signal Q1 of other three d type flip flops, Q2, Q3 is:
Can find out that through above-mentioned analysis when the control signal k1 of said first control end was 0, the control of said second control end letter k2 was 0 or 1; When the control signal k1 of said first control end was 1, the control of said second control end letter k2 was 0.Through the control signal of two control ends is set, obtain different frequency dividing ratios, if the setting of frequency dividing ratio immobilizes, the heterogeneous multimode frequency dividing circuit that present embodiment provides can correctly be worked.
Following surface analysis once, when the frequency dividing ratio dynamic change, whether the heterogeneous multimode frequency dividing circuit that present embodiment provides can operate as normal in the front and back of switching.Table 1 has been listed the change situation of the output signal of each d type flip flop in the heterogeneous multimode frequency dividing circuit that present embodiment provides, and the change situation of the output signal through each listed d type flip flop of table 1 is analyzed below.
Table 1
With initial as a frequency division cycle of the rising edge of the output signal Q1 of first d type flip flop,, remove 6/ and remove 7 these 3 patterns and be not always the case for removing 5/ so No. 2 states (state number=2) are first beats in frequency division cycle.
At first relatively except that 5 with except that 6 two patterns.The first count of these two patterns, second count and triple time the situation of output signal of (be state number=2,3,4) each d type flip flop in full accord.Therefore,, confirm to remove 5/ and remove 6 control signal, promptly confirm the value of good k1 and k2, just can realize correct except that 5 with except that the frequency division under 6 two patterns as long as before triple time (be state number=4) finishes.In other words, remove 5/ remove 6 control signal effective time be to clap to current frequency division end cycle since the 4th, and in effective time, to remain unchanged.
Then relatively except that 6 with except that 7 two patterns.The first count of these two patterns, second count and triple time (be state number=2,3,4), except Q4, output signal Q1, Q2 and the Q3 of other three d type flip flops were all identical.Wherein, At first count and second count (is state number=2; 3), because the output signal Q3 of the 3rd d type flip flop D3 equals 0, so no matter the value of the output signal Q4 of the 4th d type flip flop D4 is 0 or 1; Do not influence the input signal of first d type flip flop D1, the input signal of first d type flip flop D1 is constantly equal to 1.Therefore,, confirm to remove 6/ and remove 7 control signal, promptly confirm the value of good k1 and k2, just can realize correct except that 6 with except that the frequency division under 7 two patterns as long as before second count (be state number=3) finishes.In other words, remove 6/ remove 7 control signal effective time be since triple time to current frequency division end cycle, and in effective time, to remain unchanged.Remove 5 identical with it with the situation of removing 7 two patterns.
In sum, the heterogeneous multimode frequency dividing circuit that present embodiment provides can correct response dynamics frequency dividing ratio when meeting the following conditions, can operate as normal in the front and back of switching:
1) output of said heterogeneous multimode frequency dividing circuit is the rising edge of the output signal Q1 of first d type flip flop D1;
2) in 2 beats that begin to export from said heterogeneous multimode frequency dividing circuit, the control signal k1 of two control ends and k2 will be ready to.
Fig. 5 be in the heterogeneous multimode frequency dividing circuit shown in Figure 1 with a kind of implementation of door and second d type flip flop D2.As shown in Figure 5; The said input signal of two inputs with door is respectively A and B; In this implementation; All adopt usual manner to realize with door and second d type flip flop D2, signal A and signal B carry out logical AND through said with door earlier, and then send into second d type flip flop D2 and sample.
Embodiment two:
The similar of the structure of the heterogeneous multimode frequency dividing circuit that present embodiment provides and the heterogeneous multimode frequency dividing circuit of embodiment one, its difference only is the concrete implementation with door and second d type flip flop D2 in the heterogeneous multimode frequency dividing circuit shown in Figure 1 is improved.
The heterogeneous multimode frequency dividing circuit that embodiment two provides also comprises two control ends and four d type flip flops, wherein,
Be integrated among second d type flip flop D2 with door, this makes that the input of second d type flip flop promptly is " with logic ", and this " with " input of single " D " of logical AND end compares, and all has only 1 grade, do not have extra propagation delay;
The NAND logical signal of the output signal of the 3rd d type flip flop D3 and the 4th d type flip flop D4 is as the input signal of first d type flip flop D1;
The output signal of the NAND logical signal of the output signal of the control signal k1 of first control end and said the 3rd d type flip flop D3 and said first d type flip flop D1 is as the input signal of said second d type flip flop D2;
The output signal of said second d type flip flop D2 is as the input signal of said the 3rd d type flip flop D3;
The NAND logical signal of the logic NOT of the output signal of said the 3rd d type flip flop D3 and the control signal of second control end is as the input signal of said the 4th d type flip flop D4;
The output signal of said first d type flip flop D1 is as the output signal of said heterogeneous multimode frequency dividing circuit.
Fig. 6 be in the heterogeneous multimode frequency dividing circuit shown in Figure 1 with the another kind of implementation of door and second d type flip flop D2.As shown in Figure 6; The said input signal of two inputs with door is respectively A and B; In this implementation, to optimizing with the concrete circuit structure of door and second d type flip flop D2, with the input of second d type flip flop D2 be transformed into one " with " logic.And this " with " input of single " D " of logical AND end compares, and all has only 1 grade, do not have extra propagation delay, compares with the implementation among the embodiment one, the propagation delay of the implementation in the present embodiment will lack two-stage.
Above embodiment is merely exemplary embodiment of the present invention, is not used in restriction the present invention, and protection scope of the present invention is defined by the claims.Those skilled in the art can make various modifications or be equal to replacement the present invention in essence of the present invention and protection range, this modification or be equal to replacement and also should be regarded as dropping in protection scope of the present invention.
Claims (4)
1. the heterogeneous multimode frequency dividing circuit of a little divide ratio is characterized in that, said heterogeneous multimode frequency dividing circuit comprises two control ends and four d type flip flops, wherein,
The NAND logical signal of the output signal of the 3rd d type flip flop and the 4th d type flip flop is as the input signal of first d type flip flop;
The logical AND of the NAND logical signal of the output signal of the control signal of first control end and said the 3rd d type flip flop and the output signal of said first d type flip flop is as the input signal of second d type flip flop;
The output signal of said second d type flip flop is as the input signal of said the 3rd d type flip flop;
The NAND logical signal of the logic NOT of the output signal of said the 3rd d type flip flop and the control signal of second control end is as the input signal of said the 4th d type flip flop;
The output signal of said first d type flip flop is as the output signal of said heterogeneous multimode frequency dividing circuit.
2. heterogeneous multimode frequency dividing circuit according to claim 1; It is characterized in that; The output of said the 3rd d type flip flop and the 4th d type flip flop is connected two inputs of first NAND gate, and the output of this first NAND gate connects the input of said first d type flip flop; The output of said the 3rd d type flip flop is connected two inputs of second NAND gate with said first control end; The output of this second NAND gate is connected two inputs with door with the output of said first d type flip flop, should be with the output of door be connected the input of said second d type flip flop; The output of said second d type flip flop connects the input of said the 3rd d type flip flop; The output of said the 3rd d type flip flop connects the input of an inverter; The output of this inverter is connected two inputs of the 3rd NAND gate with said second control end, the output of the 3rd NAND gate connects the input of said the 4th d type flip flop.
3. heterogeneous multimode frequency dividing circuit according to claim 1 is characterized in that, said and door is integrated in said second d type flip flop.
4. according to the described heterogeneous multimode frequency dividing circuit of one of claim 1 to 3, it is characterized in that when the control signal of said first control end was 0, the control letter of said second control end was 0 or 1; When the control signal of said first control end was 1, the control letter of said second control end was 0.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105122649A (en) * | 2012-09-14 | 2015-12-02 | 英特尔公司 | Method of switching a semiconductor device |
| CN109217867A (en) * | 2017-07-07 | 2019-01-15 | 安徽爱科森齐微电子科技有限公司 | A kind of arbitrary integer frequency divider |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4606059A (en) * | 1983-03-31 | 1986-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Variable frequency divider |
| CN1387322A (en) * | 2001-05-18 | 2002-12-25 | 松下电器产业株式会社 | Odd factor frequency divider and 90 deg. phase splitter operated based on output signal of frequency divider |
| US20050179475A1 (en) * | 2004-01-20 | 2005-08-18 | Thales | Frequency divider |
| US20090212833A1 (en) * | 2008-02-25 | 2009-08-27 | Nec Electronics Corporation | Frequency divider circuit |
| CN202503497U (en) * | 2011-12-23 | 2012-10-24 | 上海贝岭股份有限公司 | Multiphase multimode frequency dividing circuit with small frequency coefficient |
-
2011
- 2011-12-23 CN CN201110440805.4A patent/CN102427363B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4606059A (en) * | 1983-03-31 | 1986-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Variable frequency divider |
| CN1387322A (en) * | 2001-05-18 | 2002-12-25 | 松下电器产业株式会社 | Odd factor frequency divider and 90 deg. phase splitter operated based on output signal of frequency divider |
| US20050179475A1 (en) * | 2004-01-20 | 2005-08-18 | Thales | Frequency divider |
| US20090212833A1 (en) * | 2008-02-25 | 2009-08-27 | Nec Electronics Corporation | Frequency divider circuit |
| CN202503497U (en) * | 2011-12-23 | 2012-10-24 | 上海贝岭股份有限公司 | Multiphase multimode frequency dividing circuit with small frequency coefficient |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105122649A (en) * | 2012-09-14 | 2015-12-02 | 英特尔公司 | Method of switching a semiconductor device |
| CN105122649B (en) * | 2012-09-14 | 2018-06-26 | 英特尔公司 | High-speed dual mode frequency divider |
| CN109217867A (en) * | 2017-07-07 | 2019-01-15 | 安徽爱科森齐微电子科技有限公司 | A kind of arbitrary integer frequency divider |
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