CN108173537B - Restart circuit and electronic equipment - Google Patents
Restart circuit and electronic equipment Download PDFInfo
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- CN108173537B CN108173537B CN201810002411.2A CN201810002411A CN108173537B CN 108173537 B CN108173537 B CN 108173537B CN 201810002411 A CN201810002411 A CN 201810002411A CN 108173537 B CN108173537 B CN 108173537B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K2017/226—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in bipolar transistor switches
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- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
Abstract
The invention relates to a restart circuit and an electronic device. The restarting circuit comprises a control module for outputting a control signal according to the level states of a received first clock signal and a second clock signal; the input end of the timing module is connected with the output end of the control module; when the first clock signal and the second clock signal are both at a high level, the control module outputs a conduction control signal to the timing module; the timing module receives the conduction control signal and outputs a trigger signal after a preset time; the reset module is connected with the output end of the timing module, and controls to output a reset signal according to the trigger signal so as to restart a circuit to be restarted, wherein the circuit to be restarted is connected with the output end of the reset module. When the circuit to be restarted is a level shifter, the first clock signal and the second clock signal are respectively a clock signal and an inverted clock signal thereof; when the short-term false triggering starts the protection mechanism, the clock signal and the inverted clock signal are both high level, and the restart circuit outputs the reset signal to restart the level shifter.
Description
Technical Field
The present invention relates to the field of restart technologies, and in particular, to a restart circuit and an electronic device.
Background
The LCD panel is developing towards no Gate Driver, i.e. the Gate Driver is directly processed on the Array substrate (GOA) by TFT technology to control the Gate signal. The timing control board (T/con) is the control center of the panel normal display, which generates the Gate signal and the pixel Data signal, the Gate signal generally needs higher level to realize the fast control of the TFT, the Gate signal of high level 30V and low level-8V are generated by the level shifter (L/S), so the L/S is very important for the panel display.
The L/S generally has an over-voltage/over-current protection mechanism, that is, if there is a short circuit at the output signal terminal or an external voltage is connected in series, the protection mechanism will activate the L/S, and the protection mechanism is triggered by detecting the voltage variation state of XAO pin, which is very sensitive to the tiny voltage variation, so that the output signal always follows the high level of 30V once the protection mechanism is triggered, regardless of the long-term trigger source or the short-term trigger source, thereby causing the panel to display an abnormal condition. However, on the timing control board (T/con), if the level shifter starts the overvoltage/overcurrent protection due to external sudden reasons, such as human static electricity, short circuit caused by instant impact, etc., the level shifter needs to be restarted, but the conventional L/S only has a protection mechanism but cannot restart the L/S in a short period of time when the source of the trigger protection is short.
Disclosure of Invention
The invention aims to provide a restart circuit and an electronic device, which are used for restarting a level shifter when a short-term false triggering start protection mechanism occurs to the level shifter.
The embodiment of the invention adopts the following technical scheme:
a restart circuit, comprising: the control module comprises a first input end for receiving a first clock signal and a second input end for receiving a second clock signal, and is used for outputting a corresponding control signal according to the level states of the received first clock signal and the second clock signal; the input end of the timing module is connected with the output end of the control module, and the timing module is used for receiving a conduction control signal transmitted by the control module and outputting a trigger signal after a preset time; the reset module is used for controlling and outputting a reset signal according to a trigger signal transmitted by the timing module so as to restart a circuit to be restarted, wherein the circuit to be restarted is connected with the output end of the reset module; when the first clock signal and the second clock signal received by the control module are both at a high level, the control module outputs a conduction control signal to the timing module, and after a preset time, the timing module outputs a trigger signal to the reset module, so that the reset module outputs a reset signal to a circuit to be restarted according to the trigger signal.
In one embodiment, the reset module comprises a switch control unit and a reset unit; the input end of the switch control unit is connected with the output end of the timing module, and the output end of the switch control unit is connected with the input end of the reset unit; the switch control unit is used for outputting a starting signal to the reset unit when receiving a trigger signal transmitted by the timing module; and the reset unit outputs a reset signal when receiving the starting signal so as to restart a circuit to be restarted, which is connected with the output end of the reset unit.
In one embodiment, the reset unit is a low level reset unit; the low-level reset unit outputs a low-level reset signal when receiving the start signal.
In one embodiment, the switch control unit includes a photo coupler; the low-level reset unit comprises a first high-level end, a first resistor, a first follow current capacitor and a first low-level end; the positive electrode of the transmitting end of the photoelectric coupler is connected with the output end of the timing module, and the negative electrode of the transmitting end of the photoelectric coupler is grounded; a collector of the receiving end of the photoelectric coupler is connected with the first high level end through the first resistor, and an emitter of the receiving end of the photoelectric coupler is connected with the first low level end; the first follow current capacitor is respectively connected with the collector and the emitter; the output end of the low-level reset unit is connected with the collector electrode; so as to output a low level reset signal when receiving the starting signal; or the switch control unit comprises an NPN type triode; the low-level reset unit comprises a second high-level end, a second resistor, a second follow current capacitor and a second low-level end; the control end of the NPN type triode is connected with the output end of the timing module; a collector of the NPN type triode is connected with the second high level end through the second resistor, and an emitter of the NPN type triode is connected with the second low level end; the second follow current capacitor is respectively connected with the collector and the emitter; the output end of the low-level reset unit is connected with the collector electrode, so that a low-level reset signal is output when the starting signal is received; or the switch control unit comprises a PNP type triode; the low-level reset unit comprises a third high-level end, a third resistor, a third freewheeling capacitor and a third low-level end; the control end of the PNP type triode is connected with the output end of the timing module; the collector of the PNP type triode is connected with the third low level end through the third resistor, and the emitter of the PNP type triode is connected with the third high level end; the third follow current capacitor is respectively connected with the collector and the emitter; and the output end of the low-level reset unit is connected with the collector electrode, so that a low-level reset signal is output when the starting signal is received.
In one embodiment, the system further comprises a counting module; the input end of the counting module is connected with the output end of the timing module, and the output end of the counting module is connected with the resetting module; the counting module is used for calculating the times of the trigger signals output by the timing module so as to terminate the output of the trigger signals when the times of the trigger signals output by the timing module reach preset times.
In one embodiment, the control module comprises an and gate; a first input end of the AND gate is used for receiving the first clock signal, and a second input end of the AND gate is used for receiving the second clock signal; and the AND gate outputs corresponding control signals according to the level states of the received first clock signal and the second clock signal.
In one embodiment, the device further comprises a voltage conversion module; the voltage conversion module comprises a first voltage conversion unit and a second voltage conversion unit; the input end of the first voltage conversion unit is used for receiving the first clock signal, the output end of the first voltage conversion unit is connected with the first input end of the control module, and the first voltage conversion unit is used for converting the voltage of the first clock signal into the processing voltage of the control module; the input end of the second voltage conversion unit is used for receiving the second clock signal, the output end of the second voltage conversion unit is connected with the second input end of the control module, and the second voltage conversion unit is used for converting the voltage of the second clock signal into the processing voltage of the control module.
In one embodiment, the first voltage conversion unit includes a first MOS transistor, a fourth high-level terminal, a fourth low-level terminal, and a fourth resistor; the control end of the first MOS transistor is configured to receive the first clock signal, the input end of the first MOS transistor is connected to the fourth high-level end, and the output end of the first MOS transistor is connected to the fourth low-level end through the fourth resistor; the output end of the first MOS tube is connected with the first input end of the control module; the second voltage conversion unit comprises a second MOS tube, a fifth high-level end, a fifth low-level end and a fifth resistor; the control end of the second MOS transistor is configured to receive the second clock signal, the input end of the second MOS transistor is connected to the fifth high-level end, and the output end of the second MOS transistor is connected to the fifth low-level end through the fifth resistor; and the output end of the second MOS tube is connected with the second input end of the control module.
In one embodiment, the device further comprises a current limiting module; the input end of the current limiting module is connected with the output end of the timing module, and the output end of the current limiting module is connected with the output end of the resetting module; the current limiting module is used for controlling the input current flowing into the reset module.
An electronic device comprising the restart circuit according to any of the above embodiments.
According to the restarting circuit provided by the invention, when the first clock signal and the second clock signal received by the control module are both in a high level, the control module outputs the conduction control signal to the timing module, and after the preset time, the timing module outputs the trigger signal to the reset module, so that the reset module outputs the reset signal to the circuit to be restarted according to the trigger signal. That is, the clock signal and the inverted clock signal of the level shifter are connected to the control module, and the output terminal of the restart circuit is connected to the level shifter. When the short-term false triggering of the level shifter starts the protection mechanism, the clock signal and the inverted clock signal are both high level, and at the moment, the restart circuit outputs a reset signal to the level shifter after the preset time so as to restart the level shifter.
Furthermore, the restart circuit of the present invention is further provided with a counting module, which is used for controlling the timing module not to output the trigger signal any more after receiving the preset times of the conduction control signal transmitted by the timing module. That is, after the number of restart times of the level shifter reaches the preset number of times, the reset module is controlled not to output the reset signal any more, and the level shifter is not restarted any more. Therefore, the restart circuit can further determine whether the source of the trigger protection belongs to a long-term trigger source or a short-term trigger source (the preset times in the counting module can be set according to the long-term trigger source and the short-term trigger source), and perform corresponding operations (restarting the level shifter or not restarting the level shifter) according to the source of the trigger protection.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
FIG. 1 is a block diagram of an exemplary embodiment of a restart circuit according to the present invention;
FIG. 2 is a block diagram of a restart circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a restart circuit according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of an embodiment of a restart circuit according to the present invention;
FIG. 5 is a circuit diagram of an embodiment of a reset module, a timing module and a counting module according to the present invention;
fig. 6 is a circuit diagram of a reset module, a timing module and a counting module according to another embodiment of the present invention.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a restart circuit. As shown in fig. 1, the restart circuit 30 includes a control module 100, a timing module 200, and a reset module 300. The control module 100 comprises a first input 101 for receiving the first clock signal 10 and a second input 103 for receiving the second clock signal 20. The control module 100 is configured to output a corresponding control signal according to the level states of the received first clock signal 10 and the second clock signal 20.
The input of the timing module 200 is connected to the output of the control module 100. The timing module 200 is configured to receive the conduction control signal sent by the control module 100 and output a trigger signal after a preset time. The input terminal of the reset module 300 is connected to the output terminal of the timing module 200. The reset module 300 is configured to control to output a reset signal according to the trigger signal transmitted by the timing module 200, so as to restart the circuit 40 to be restarted, which is connected to the output terminal of the reset module 300.
When the first clock signal 10 and the second clock signal 20 received by the control module 100 are both at a high level, the control module 100 outputs a turn-on control signal to the timing module 200, and after a preset time, the timing module 200 outputs a trigger signal to the reset module 300, so that the reset module 300 outputs a reset signal to the circuit to be restarted 40 according to the trigger signal.
In one embodiment, the reset module 300 includes a switch control unit and a reset unit (not shown). The input end of the switch control unit is connected with the output end of the timing module 200, and the output end of the switch control unit is connected with the input end of the reset unit. The switch control unit is configured to output a start signal to the reset unit when receiving the trigger signal transmitted by the timing module 200, and the reset unit outputs a reset signal when receiving the start signal to restart the circuit to be restarted 40 connected to the output terminal of the reset unit. In the present embodiment, the reset unit is a low-level reset unit. The low-level reset unit outputs a low-level reset signal when receiving the start signal, so that the circuit to be restarted 40 performs reset restart according to the low-level reset signal. In other embodiments, the reset unit may also be a high level reset unit. The high-level reset unit outputs a high-level reset signal when receiving the start signal, so that the circuit to be restarted 40 performs reset restart according to the high-level reset signal. That is, when the circuit to be restarted 40 is reset at a low level, the reset unit is a low-level reset unit. When the circuit to be restarted 40 is reset at a high level, the reset unit is a high-level reset unit.
In the restart circuit 30 of the present invention, when the first clock signal 10 and the second clock signal 20 received by the control module 100 are both at a high level, the control module 100 outputs a turn-on control signal to the timing module 200, and after a preset time, the timing module 200 outputs a trigger signal to the reset module 300, so that the reset module 300 outputs a reset signal to the circuit to be restarted 40 according to the trigger signal. That is, the clock signal and the inverted clock signal of the level shifter are connected to the control module 100, and the output terminal of the restart circuit 30 is connected to the level shifter. When the short-term false triggering of the level shifter starts the protection mechanism, the clock signal and the inverted clock signal are both high level, and at the moment, the restart circuit outputs a reset signal to the level shifter after the preset time so as to restart the level shifter.
In one embodiment, as shown in FIG. 2, the restart circuit 30 further includes a counting module 400. The input end of the counting module 400 is connected with the output end of the timing module 200, and the output end of the counting module 400 is connected with the resetting module 300. The counting module 400 is configured to count the number of times of the trigger signal output by the timing module 200, and terminate the reset module 300 to output the trigger signal when the number of times of the trigger signal output by the timing module 200 reaches a preset number. That is, after the number of times of restarting the level shifter reaches the preset number of times, the restart circuit 30 controls the reset module 300 not to output the reset signal to the level shifter any more, i.e., the level shifter is not restarted any more. Therefore, the restart circuit 30 can further determine whether the source of the trigger protection belongs to a long-term trigger source or a short-term trigger source (the preset times in the counting module 400 can be set according to the long-term trigger source and the short-term trigger source), and perform corresponding operations (restarting the level shifter or interrupting the restarting the level shifter) according to the source of the trigger protection.
In one embodiment, as shown in fig. 3, the restart circuit 30 further includes a voltage conversion module 500. The voltage converting module 500 includes a first voltage converting unit and a second voltage converting unit (not shown). The input end of the first voltage conversion unit is configured to receive the first clock signal 10, the output end of the first voltage conversion unit is connected to the first input end 101 of the control module 100, and the first voltage conversion unit is configured to convert the voltage of the first clock signal 10 into the processing voltage of the control module 100. The input terminal of the second voltage conversion unit is configured to receive the second clock signal 20, and the output terminal of the second voltage conversion unit is connected to the second input terminal 103 of the control module 100. The second voltage conversion unit is used for converting the voltage of the second clock signal 20 into the processing voltage of the control module 100.
In one embodiment, the restart circuit 30 further includes a current limiting module 600. The input end of the current limiting module 600 is electrically connected to the output end of the timing module 200, and the output end of the current limiting module 600 is electrically connected to the output end of the reset module 300. The current limiting module 600 is used to control the input current flowing into the reset module 300 to perform current limiting protection on the reset module 300.
In one embodiment, as shown in FIG. 4, the control module 100 includes an AND gate U1. The circuit to be restarted 40 is a starting circuit in the level shifter. The timing module 200 and the counting module 400 are integrated into a timer/counter U2. The first clock signal 10 is a clock signal CLK and the second clock signal 20 is an inverted clock signal CLK'. The first input 1 of the and gate U1 is for receiving a clock signal and the second input 2 of the and gate U1 is for receiving an inverted clock signal. The and gate U1 outputs a corresponding control signal according to the level states of the received clock signal and the inverted clock signal.
Output 3 of and gate U1 is connected to the input of timer/counter U2. The output of the timer/counter U2 is connected to the input of the reset module 300. The output terminal of the reset module 300 is used for connecting with a start circuit of the level shifter to output a reset signal to the level shifter for resetting.
The clock signal input end and the inverted clock signal input end are both used for being connected with the output end of the level shifter and receiving the output signal of the level shifter. When the level shifter works normally, the signals received by the clock signal input end and the inverted clock signal input end are inverted. When the level shifter is triggered and protected, signals received by the clock signal input end and the inverted clock signal input end are high level signals.
When the level shifter is triggered and protected, the signal received by the clock signal input end and the signal received by the inverted clock signal input end are both high level signals, and at this time, the output end 3 of the and gate U1 outputs a conduction control signal for triggering the timer/counter U2 to start.
The timer/counter U2 is set with a preset time T. The timer/counter U2 outputs a trigger signal to the reset module 300 after receiving the on control signal outputted from the and gate U1 for a predetermined time T, so as to trigger the module 300 to operate.
The reset module 300 outputs a reset signal to the level shifter after receiving the trigger signal output by the timer/counter U2, so that the level shifter is reset to operate normally. In this embodiment, the preset time T is determined according to the short-term abnormal triggering time. The preset time T may be in the order of milliseconds.
In this embodiment, the timer/counter U2 is also set with a preset number n. When the reset number of the level shifter exceeds the preset number n, the timer/counter U2 no longer outputs the trigger signal to trigger the reset module 300. That is, when the number of times of resetting of the level shifter exceeds n times, the restart circuit does not output the reset signal any more, and the level shifter does not perform the reset start any more. The preset number n is determined according to the short-term abnormal triggering time and the long-term abnormal triggering time. For example, if the short-term trigger time is T and the long-term trigger time is n × T, the level shifter is not reset after n times of resetting. That is, the restart circuit in this embodiment outputs a reset signal to reset the level shifter when short-term abnormal triggering occurs in the level shifter. When the level shifter is triggered abnormally for a long time, the reset signal is output to reset the level shifter for n times, and then the reset signal is not output any more. Namely, when the level shifter is subjected to long-term abnormal protection, the protection mechanism is kept to protect the level shifter. Therefore, the restart circuit can further determine whether the source of the trigger protection belongs to the long-term trigger source or the short-term trigger source, and perform corresponding operations (restarting the level shifter or not restarting the level shifter) according to the source of the trigger protection. In one embodiment of this embodiment, the preset number n is less than or equal to 3, so that device damage possibly caused by the repeated trigger protection and reset operations of the restart circuit according to the trigger source can be avoided.
In the present embodiment, as shown in fig. 4, the switch control unit includes a photo coupler U3. The low level reset unit includes a first high level terminal VCC2, a first resistor R3, a first freewheeling capacitor C1, and a first low level terminal. In the present embodiment, the first low-level terminal is the GND2 terminal. The positive electrode of the emitting end of the photoelectric coupler U3 is connected with the output end of the timer/counter U2, and the negative electrode of the emitting end of the photoelectric coupler U3 is grounded. The collector of the receiving end of the photoelectric coupler U3 is connected with the first high-level VCC2 end through a first resistor R3, and the emitter of the receiving end of the photoelectric coupler U3 is connected with the GND2 end. The first freewheeling capacitor C1 is connected to the collector and the emitter of the receiving terminal of the optocoupler U3, respectively. The output terminal RST of the low level reset circuit is connected with the collector of the receiving terminal of the photocoupler U3 for outputting a low level reset signal to enable the level shifter to perform a reset operation. In this embodiment, the current limiting module 600 includes a current limiting resistor R4. The current limiting resistor R4 is connected between the negative electrode of the emitting end of the photoelectric coupler U3 and the ground end to control the current of the emitting end of the photoelectric coupler U3.
In another embodiment of this embodiment, as shown in fig. 5, the switch control unit includes an NPN transistor Q1. The low level reset unit includes a second high level terminal VCC21, a second resistor R31, a second freewheeling capacitor C11, and a second low level terminal. In the present embodiment, the second low-level terminal is the GND21 terminal. A control end of the NPN transistor Q1 is connected to the output end of the timer/counter U2, a collector of the NPN transistor Q1 is connected to the second high-level terminal VCC21 through the second resistor R31, and an emitter of the NPN transistor Q1 is connected to the GND2 terminal. The second freewheeling capacitor C11 is connected to the collector and emitter of the NPN transistor Q1, respectively. The output terminal RST of the low level reset circuit is connected to the collector of an NPN transistor Q1 for outputting a low level reset signal to cause the level shifter to perform a reset operation. In this embodiment, the current limiting module 600 further includes a current limiting resistor R41. A current limiting resistor R41 is connected between the timer/counter U2 and the control terminal of the NPN transistor Q1 to control the current at the control terminal of the NPN transistor Q1.
In another implementation of this embodiment, as shown in fig. 6, the switch control unit includes a PNP transistor Q2. The low level reset unit includes a third high level terminal VCC22, a third resistor R32, a third freewheeling capacitor C12 and a third low level terminal. In this embodiment, the control terminal of the PNP transistor Q2 is connected to the output terminal of the timer/counter U2. The collector of the PNP transistor Q2 is connected to the GND22 terminal through the third resistor R32, and the emitter of the PNP transistor Q2 is connected to the third high-level terminal VCC 22. The third freewheeling capacitor C12 is connected to the collector and emitter of the PNP transistor Q2, respectively. The output terminal RST of the low level reset circuit is connected to the collector of the PNP transistor Q2 for outputting a low level reset signal to cause the level shifter to perform a reset operation. In this embodiment, the current limiting module 600 further includes a current limiting resistor R42. The current limiting resistor R42 is connected between the timer/counter U2 and the control terminal of the PNP transistor Q2 to control the current of the control terminal of the PNP transistor Q2.
In this embodiment, the restart circuit further includes a first voltage conversion circuit. As shown in fig. 4, the first voltage conversion unit includes a first MOS transistor M1, a fourth high-level terminal VCC1, a fourth low-level terminal, and a fourth resistor R1. In the present embodiment, the fourth low-level terminal is the GND1 terminal. The control terminal of the first MOS transistor M1 is connected to the clock signal input terminal (CLK terminal shown in fig. 4), the input terminal of the first MOS transistor M1 is connected to the fourth high-level terminal VCC1, and the output terminal of the first MOS transistor M1 is connected to the GND1 through the fourth resistor R1. The first input terminal 1 of the and gate U1 is connected to the output terminal of the first MOS transistor M1.
The second voltage conversion unit includes a second MOS transistor M2, a fifth high-level terminal VCC1, a fifth low-level terminal, and a fifth resistor R2. In this embodiment, the fifth high-level terminal and the fourth high-level terminal are the same terminal, and are both terminals VCC 1. The fifth low-level terminal and the fourth low-level terminal are the same level terminal and are both GND1 terminals. The control terminal of the second MOS transistor M2 is connected to the inverted clock signal input terminal (CLK' terminal shown in fig. 4), the input terminal of the second MOS transistor M2 is connected to the VCC1 terminal, and the output terminal of the second MOS transistor M2 is connected to the GND1 terminal through the fifth resistor R2. The second input terminal 2 of the and gate U1 is connected to the output terminal of the second MOS transistor M2.
In this embodiment, the first voltage conversion unit converts the high level voltage inputted from the clock signal input terminal into a high level for processing by the and gate U1. The second voltage conversion unit converts the high level voltage input from the inverted clock signal input terminal into a high level for processing by the and gate U1. The second MOS transistor M2 and the first MOS transistor M1 are both N-type MOS transistors.
In other embodiments, the fifth high level terminal and the fourth high level terminal may be different level terminals, and the fifth low level terminal and the fourth low level terminal may be different level terminals. The second MOS transistor M2 and the first MOS transistor M1 may also be P-type MOS transistors.
A specific circuit configuration of the restart circuit according to the present invention will be described in detail below. The restart circuit is used for a timing control board (T/con) of an LCD liquid crystal display panel. The following "0" and "1" each represent "0" and "1" in the logical concept.
As shown in fig. 4. CLK and CLK' are output signals of L/S (level shifter), and the signals are inverted during normal operation. RST is the input signal to the L/S, which controls the reset of the L/S. M1 and M2 are N-type MOS transistors, U1 is AND logic, U2 is timing/counting logic, U3 is a photoelectric coupler, R1-R4 are resistors, and C1 is a capacitor. VCC1 and VCC2, GND1 and GND2 may be isolated power supplies or the same power supply.
During normal display of the screen of the LCD liquid crystal panel, CLK and CLK' are inverted in the display region, i.e., "1" and "0" or "0" and "1", and are both low, i.e., "0", in the Blanking region. Since the high levels of CLK and CLK' are 30V and the logic high level of the U1 and gate circuit is VCC1, the 30V high level of the CLK signal is converted to the high level VCC1 for U1 processing by M1 and R1. Similarly, M2 and R2 translate the 30V high level of the CLK' signal to a high level VCC1 for U1 processing. Therefore, at least one of the input pins 1 and 2 of the U1 is always at logic "0", so the output pin 3 is at "0", the timing function of the U2 is not triggered, the U3 does not work, the RST always maintains a high level signal of the VCC2, and the L/S is not reset.
When the L/S is triggered and protected, the screen display of the LCD panel is abnormal, and the CLK and CLK ' outputs are both high level, namely both ' 1 '. If the set time is T, and T is determined according to the short-term abnormal trigger time, and may be in the millisecond level, after the time T, the transmitting end of U3 inputs a high level to operate U3, and the receiving end is turned on, and then the RST signal is turned on with GND2 through the receiving end, and RST is a low level, so that L/S reset is completed, where R3 and R4 are current-limiting resistors, and C1 is a freewheeling capacitor.
After the reset is completed, if the source triggering the L/S is short-term, after 1 reset, the L/S can normally work again after being restarted. If the source of the trigger L/S is long-term, after 1 reset, the L/S will be triggered to protect again, and the restart of the circuit of FIG. 4 is repeated again to reset the L/S for the 2 nd time, and then the L/S will be triggered again after restarting again, and the loop is infinite. To avoid possible device damage due to L/S cycling protection and reset from long-term triggering sources, the number of protections is counted in U2. And when the protection times exceed the counting times, judging as a long-term trigger source.
For example, assuming that the count n is 1, the RST signal is reset only 1 time, and even if pin 3 of U1 outputs "1" again, U2 does not output "1" and U3 operates. The time of the short-term trigger source is n x T and the time exceeding n x T is considered as the long-term trigger source. If n is 2, the RST signal will be reset for 2 times if the RST signal is a long-term trigger source, and likewise, the time exceeding n x T is considered as the long-term trigger source, the value of n is not suitable to be set too large, and generally n is less than or equal to 3, so as to avoid repeated trigger protection and reset of the circuit.
The invention also provides electronic equipment. The electronic device comprises a level shifter and further comprises a restart circuit 30 according to any of the embodiments described above. The clock signal input terminal and the inverted clock signal input terminal of the restart circuit 30 are both connected to the output terminal of the level shifter, and are configured to receive the output signal of the level shifter. The output end of the reset circuit of the restart circuit is connected with the level shifter and used for outputting a reset signal to the level shifter for resetting. The level shifter obtains a reset signal from the reset circuit to restart.
The electronic device can be an electronic product with a restart circuit, such as a liquid crystal display panel, an electronic mobile device or a computer.
The above description is only a preferred embodiment of the present invention, and for those skilled in the art, the present invention should not be limited by the description of the present invention, which should be interpreted as a limitation.
Claims (10)
1. A restart circuit for connection to a level shifter, comprising:
the control module comprises a first input end for receiving a first clock signal and a second input end for receiving a second clock signal, and is used for outputting a corresponding control signal according to the level states of the received first clock signal and the second clock signal; wherein the first clock signal and the second clock signal are generated by the level shifter, and phases of the first clock signal and the second clock signal in a normal working state are opposite;
the input end of the timing module is connected with the output end of the control module, and the timing module is used for receiving a conduction control signal transmitted by the control module and outputting a trigger signal after a preset time;
the reset module is used for controlling and outputting a reset signal according to a trigger signal transmitted by the timing module so as to restart a circuit to be restarted, wherein the circuit to be restarted is connected with the output end of the reset module;
when the first clock signal and the second clock signal received by the control module are both at a high level, the control module outputs a conduction control signal to the timing module, and after a preset time, the timing module outputs a trigger signal to the reset module, so that the reset module outputs a reset signal to a circuit to be restarted according to the trigger signal.
2. The restart circuit of claim 1, wherein the reset module comprises a switch control unit and a reset unit; the input end of the switch control unit is connected with the output end of the timing module, and the output end of the switch control unit is connected with the input end of the reset unit; the switch control unit is used for outputting a starting signal to the reset unit when receiving a trigger signal transmitted by the timing module; and the reset unit outputs a reset signal when receiving the starting signal so as to restart a circuit to be restarted, which is connected with the output end of the reset unit.
3. The restart circuit of claim 2, wherein the reset unit is a low level reset unit; the low-level reset unit outputs a low-level reset signal when receiving the start signal.
4. The restart circuit of claim 3, wherein the switching control unit comprises a photo coupler; the low-level reset unit comprises a first high-level end, a first resistor, a first follow current capacitor and a first low-level end; the positive electrode of the transmitting end of the photoelectric coupler is connected with the output end of the timing module, and the negative electrode of the transmitting end of the photoelectric coupler is grounded; a collector of the receiving end of the photoelectric coupler is connected with the first high level end through the first resistor, and an emitter of the receiving end of the photoelectric coupler is connected with the first low level end; the first follow current capacitor is respectively connected with the collector and the emitter; the output end of the low-level reset unit is connected with the collector so as to output a low-level reset signal when receiving the starting signal; or
The switch control unit comprises an NPN type triode; the low-level reset unit comprises a second high-level end, a second resistor, a second follow current capacitor and a second low-level end; the control end of the NPN type triode is connected with the output end of the timing module; a collector of the NPN type triode is connected with the second high level end through the second resistor, and an emitter of the NPN type triode is connected with the second low level end; the second follow current capacitor is respectively connected with the collector and the emitter; the output end of the low-level reset unit is connected with the collector so as to output a low-level reset signal when receiving the starting signal; or
The switch control unit comprises a PNP type triode; the low-level reset unit comprises a third high-level end, a third resistor, a third freewheeling capacitor and a third low-level end; the control end of the PNP type triode is connected with the output end of the timing module; the collector of the PNP type triode is connected with the third low level end through the third resistor, and the emitter of the PNP type triode is connected with the third high level end; the third follow current capacitor is respectively connected with the collector and the emitter; and the output end of the low-level reset unit is connected with the collector so as to output a low-level reset signal when receiving the starting signal.
5. The restart circuit of claim 1, further comprising a counting module; the input end of the counting module is connected with the output end of the timing module, and the output end of the counting module is connected with the resetting module; the counting module is used for calculating the times of the trigger signals output by the timing module so as to terminate the output of the trigger signals when the times of the trigger signals output by the timing module reach preset times.
6. The restart circuit of claim 1, wherein said control module comprises an and gate; a first input end of the AND gate is used for receiving the first clock signal, and a second input end of the AND gate is used for receiving the second clock signal; and the AND gate outputs corresponding control signals according to the level states of the received first clock signal and the second clock signal.
7. The restart circuit of claim 1, further comprising a voltage conversion module; the voltage conversion module comprises a first voltage conversion unit and a second voltage conversion unit; the input end of the first voltage conversion unit is used for receiving the first clock signal, the output end of the first voltage conversion unit is connected with the first input end of the control module, and the first voltage conversion unit is used for converting the voltage of the first clock signal into the processing voltage of the control module; the input end of the second voltage conversion unit is used for receiving the second clock signal, the output end of the second voltage conversion unit is connected with the second input end of the control module, and the second voltage conversion unit is used for converting the voltage of the second clock signal into the processing voltage of the control module.
8. The restart circuit of claim 7, wherein the first voltage converting unit comprises a first MOS transistor, a fourth high-level terminal, a fourth low-level terminal, and a fourth resistor; the control end of the first MOS transistor is configured to receive the first clock signal, the input end of the first MOS transistor is connected to the fourth high-level end, and the output end of the first MOS transistor is connected to the fourth low-level end through the fourth resistor; the output end of the first MOS tube is connected with the first input end of the control module; the second voltage conversion unit comprises a second MOS tube, a fifth high-level end, a fifth low-level end and a fifth resistor; the control end of the second MOS transistor is configured to receive the second clock signal, the input end of the second MOS transistor is connected to the fifth high-level end, and the output end of the second MOS transistor is connected to the fifth low-level end through the fifth resistor; and the output end of the second MOS tube is connected with the second input end of the control module.
9. The restart circuit of claim 1, further comprising a current limiting module; the input end of the current limiting module is connected with the output end of the timing module, and the output end of the current limiting module is connected with the output end of the resetting module; the current limiting module is used for controlling the input current flowing into the reset module.
10. An electronic device, characterized in that it comprises a restart circuit as claimed in any one of the preceding claims 1 to 9.
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| CN109637412B (en) * | 2018-12-25 | 2020-10-30 | 惠科股份有限公司 | Overcurrent protection method of display panel and display device |
| CN110009898B (en) * | 2019-04-29 | 2024-02-06 | 深圳市嘉昱机电有限公司 | Infrared receiving device and infrared receiving system |
| CN111063290B (en) * | 2019-12-25 | 2022-12-06 | Tcl华星光电技术有限公司 | Driving circuit, driving method and display panel |
| TWI717965B (en) * | 2020-01-08 | 2021-02-01 | 敦泰電子股份有限公司 | Display module, display driver integrated circuit and restarting method for display driver integrated circuit when abnormal voltage occurs |
| CN111200425A (en) * | 2020-01-23 | 2020-05-26 | 华为技术有限公司 | Reset circuit and related electronic equipment |
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