CN108234947B - Multi-picture image array display system - Google Patents
Multi-picture image array display system Download PDFInfo
- Publication number
- CN108234947B CN108234947B CN201810005869.3A CN201810005869A CN108234947B CN 108234947 B CN108234947 B CN 108234947B CN 201810005869 A CN201810005869 A CN 201810005869A CN 108234947 B CN108234947 B CN 108234947B
- Authority
- CN
- China
- Prior art keywords
- resistor
- capacitor
- diode
- transistor
- triode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
- H04N7/181—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast for receiving images from a plurality of remote sources
Abstract
The invention discloses a multi-picture image array display system, which comprises an integrated camera device, a plurality of data receiving modules, a storage module, a microprocessor, a display control module, a display interface module, a display and a power supply protection circuit, wherein the integrated camera device comprises a power supply circuit and a plurality of cameras which are all connected with the power supply circuit; the power supply circuit comprises a positive input end, a negative input end, a positive output end, a negative output end, a first diode, a first resistor, a second voltage stabilizing diode, a first triode, a third resistor, a first capacitor, a fourth resistor, a second triode, a third voltage stabilizing diode and a first MOS (metal oxide semiconductor) tube. The invention has the advantages of convenient and simple wiring, capability of displaying a plurality of pictures in an array mode, simpler circuit structure, lower cost and higher safety and reliability of the circuit.
Description
Technical Field
The invention relates to the field of image display, in particular to a multi-picture image array display system.
Background
At present, a Camera mainly transmits a collected image to a server (the server may be a Linux operating system or a Windows operating system) through a usb (universal Serial bus) Interface, an Ethernet Interface, or an mipicsi (Mobile Industry Processor Interface), a parallel Interface, an MIPI (Mobile Industry Processor Interface), or the like. In some application scenarios, for example, in the field of automatic driving, a large number (for example, 9 paths, or even more than ten paths) of cameras are often installed on a vehicle for collecting environmental image data, and installing too many cameras not only complicates wiring, but also causes waste of cost. In a traditional image acquisition and display system, only images acquired by cameras can be displayed independently, and images acquired by a plurality of cameras cannot be displayed in an array mode. In addition, the circuit structure of the power supply part in the traditional image acquisition display system is complex, and the hardware cost is high. And because the power supply part in the traditional image acquisition system lacks the corresponding circuit protection function, the safety and the reliability of the circuit are not high.
Disclosure of Invention
The present invention is directed to provide a multi-screen image array display system, which has the advantages of simple and convenient wiring, capability of displaying multiple screens in an array manner, simple circuit structure, low cost, and high circuit safety and reliability.
The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-picture image array display system is constructed and comprises an integrated camera device, a plurality of data receiving modules, a storage module, a microprocessor, a display control module, a display interface module, a display and a power supply protection circuit, wherein the integrated camera device comprises a power supply circuit and a plurality of cameras which are all connected with the power supply circuit, the storage module is connected with the microprocessor and used for storing preset image array values, each data receiving module acquires original images acquired by the cameras connected with the data receiving module and sends the original images to the microprocessor, the display interface module acquires parameters of the display and sends the parameters to the microprocessor, and the microprocessor sends the preset image array values and the parameters of the display to the display control module, the display control module calculates an image scaling coefficient, the microprocessor controls each original image to be scaled according to the image scaling coefficient to obtain a processed image, each processed image is sent to the display through the display interface module and is displayed on the display in an array arrangement mode, and the power supply protection circuit is connected with the microprocessor and used for protecting a power supply;
the power supply circuit comprises a positive input end, a negative input end, a positive output end, a negative output end, a first diode, a first resistor, a second voltage-stabilizing diode, a first triode, a third resistor, a first capacitor, a fourth resistor, a second triode, a third voltage-stabilizing diode and a first MOS (metal oxide semiconductor) tube, wherein the cathode of the first diode is connected with the positive input end, the anode of the first diode is connected with the negative input end, the cathode of the first diode is also respectively connected with one end of the first resistor and the cathode of the second voltage-stabilizing diode, the base of the first triode is respectively connected with the other end of the first resistor and one end of the second resistor, the other end of the second resistor is connected with the negative input end, and the emitter of the first triode is respectively connected with the anode of the second voltage-stabilizing diode and one end of the third resistor, the other end of the third resistor is connected with the negative electrode input end;
the collecting electrode of first triode passes through first electric capacity respectively with the one end of fourth resistance and the base of second triode are connected, the other end of fourth resistance and the projecting pole of second triode all with the negative pole input is connected, the collecting electrode of second triode respectively with the negative pole of third zener diode, the grid of first MOS pipe, the negative pole and the positive output of second zener diode are connected, the positive pole of third zener diode and the source electrode of first MOS pipe all with the negative pole input is connected, the drain electrode of first MOS pipe with the negative pole output is connected, the capacitance value of first electric capacity is 500 pF.
In the multi-picture image array display system of the present invention, the power supply circuit further includes a fourth diode, an anode of the fourth diode is connected to a cathode of the second zener diode, a cathode of the fourth diode is connected to the cathode output terminal, and the type of the fourth diode is S-562.
In the multivision image array display system of the present invention, the power supply circuit further includes a second capacitor, one end of the second capacitor is connected to a collector of the second triode, the other end of the second capacitor is connected to a gate of the first MOS transistor, and a capacitance of the second capacitor is 460 pF.
In the multi-picture image array display system of the present invention, the power supply circuit further includes a fifth resistor, one end of the fifth resistor is connected to the emitter of the second triode, the other end of the fifth resistor is connected to the negative input terminal, and the resistance of the fifth resistor is 33k Ω.
In the multi-picture image array display system of the present invention, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the first MOS transistor is an N-channel MOS transistor.
In the multivision image array display system of the present invention, the power protection circuit includes a dc power supply, a relay, a third transistor, a fourth transistor, a second MOS transistor, a sixth resistor, a seventh resistor, an eighth sliding resistor, a third capacitor, a fourth capacitor, a light emitting diode, and a voltage output terminal, a moving contact of the relay is connected to the dc power supply, a stationary contact of the relay is respectively connected to a collector of the third transistor and one end of the fourth capacitor, an emitter of the third transistor is connected to one end of a coil of the relay, the other end of the coil of the relay is grounded, a base of the third transistor is respectively connected to the other end of the fourth capacitor and one end of the sixth resistor, the other end of the sixth resistor is grounded, one fixed end of the eighth sliding resistor is respectively connected to one end of the fourth capacitor, The drain electrode of the second MOS tube, the collector electrode of the fourth triode and one end of the third capacitor are connected, another fixed end and the sliding end of the eighth sliding rheostat are respectively connected with one end of the seventh resistor and the base electrode of the fourth triode, the other end of the seventh resistor is grounded, the emitter electrode of the fourth triode is connected with the power output end, the grid electrode of the second MOS tube is respectively connected with one end of the third capacitor and the anode of the light-emitting diode, the cathode of the light-emitting diode is grounded, the source electrode of the second MOS tube is connected with the voltage output end, the capacitance value of the third capacitor is 300pF, and the capacitance value of the fourth capacitor is 450 pF.
In the multivision image array display system of the present invention, the power protection circuit further includes a fifth diode, an anode of the fifth diode is connected to a drain of the second MOS transistor, a cathode of the fifth diode is connected to a collector of the fourth transistor, and the fifth diode is of type e-501.
In the multivision image array display system of the present invention, the power protection circuit further includes a ninth resistor, one end of the ninth resistor is connected to the emitter of the fourth triode, the other end of the ninth resistor is connected to the voltage output terminal, and the resistance of the ninth resistor is 36k Ω.
In the multivision image array display system of the present invention, the power protection circuit further includes a fifth capacitor, one end of the fifth capacitor is connected to one end of the seventh resistor, the other end of the fifth capacitor is connected to a base of the fourth triode, and a capacitance of the fifth capacitor is 500 pF.
The multi-picture image array display system has the following beneficial effects: the power supply circuit comprises a positive electrode input end, a negative electrode input end, a positive electrode output end, a negative electrode output end, a first diode, a first resistor, a second voltage stabilizing diode, a first triode, a third resistor, a first capacitor, a fourth resistor, a second triode, a third voltage stabilizing diode and a first MOS (metal oxide semiconductor) tube The circuit structure is simpler, the cost is lower, and the security and the reliability of circuit are higher.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a multi-frame image array display system according to the present invention;
FIG. 2 is a schematic circuit diagram of the power supply circuit of the embodiment;
fig. 3 is a circuit schematic diagram of the power protection circuit in the embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In an embodiment of the present invention, a schematic structural diagram of the multiple-frame image array display system is shown in fig. 1. In fig. 1, the multi-screen image array display system includes an integrated camera device 1, a plurality of data receiving modules 2, a storage module 3, a microprocessor 4, a display control module 5, a display interface module 6, a display 7 and a power protection circuit 8, wherein the integrated camera device 1 includes a power supply circuit 11 and a plurality of cameras 12, the plurality of cameras 12 are all connected with the power supply circuit 11, the plurality of cameras 12 are made into the integrated camera device 1, so that not only can the cost be saved, but also the complexity of wiring can be reduced, and the wiring is convenient and simple. The storage module 3 is connected with the microprocessor 4 and is used for storing preset image array values. The memory module 3 may store the image data in a bit-mapped manner in a line scan order, sequentially store each pixel of the image in a byte matrix from left to right and from top to bottom, and store 8 pixels of data per byte for monochrome images.
The number of the data receiving modules 2 is equal to that of the cameras 12, each data receiving module 2 is connected with the corresponding camera 12, each data receiving module 2 acquires an original image acquired by the camera 12 connected with the data receiving module and sends the original image to the microprocessor 4, the display interface module 6 acquires parameters of the display 7 and sends the parameters of the display 7 to the microprocessor 4, the parameters of the display 7 comprise the highest resolution, the screen width and the height of the display 7, and the parameters of the display 7 are acquired through identification data of external display equipment.
The microprocessor 4 sends a preset image array value and parameters of the display 7 to the display control module 5, the display control module 5 calculates an image scaling coefficient, the microprocessor 4 obtains the image scaling coefficient from the display control module 5 and controls each original image to be scaled according to the image scaling coefficient to obtain a processed image, the microprocessor 4 sends each processed image to the display 7 through the display interface module 6 and displays the processed image on the display 7 in an array arrangement mode, the array arrangement mode is arranged according to the preset image array value, and the power supply protection circuit 8 is connected with the microprocessor 4 and used for protecting a power supply.
The invention scales the image according to the comprehensive parameters of the original image and the display 7, scales the image by the corresponding times in the horizontal direction and scales the image by the corresponding times in the vertical direction, thereby obtaining a new image which is a thumbnail of the original image and has the size which is just right enough to be displayed in the display 7. The invention calculates the image scaling factor through the parameters of the display 7 and the preset image array value, displays the image according to the image scaling factor, and ensures that the image can be reduced by a certain proportion according to the parameters of the display 7 and just displayed on the display 7 in an array arrangement mode. Therefore, the invention can display a plurality of pictures in an array mode.
Fig. 2 is a schematic circuit diagram of a power supply circuit in this embodiment, in fig. 2, the power supply circuit 11 includes a positive input terminal Vin +, a negative input terminal Vin-, a positive output terminal Vo +, a negative output terminal Vo-, a first diode D1, a first resistor R1, a second resistor R2, a second zener diode D2, a first transistor Q1, a third resistor R3, a first capacitor C1, a fourth resistor R4, a second transistor Q2, a third zener diode D3, and a first MOS transistor M1, wherein a cathode of the first diode D1 is connected to the positive input terminal Vin +, an anode of the first diode D1 is connected to the negative input terminal Vin-, a cathode of the first diode D1 is further connected to one end of the first resistor R1 and a cathode of the second zener diode D2, a base of the first transistor Q1 is connected to the other end of the first resistor R1 and one end of the second resistor R2, the other end of the second resistor R2 is connected with a negative input terminal Vin-, an emitter of the first triode Q1 is respectively connected with an anode of the second voltage-stabilizing diode D2 and one end of the third resistor R3, and the other end of the third resistor R3 is connected with the negative input terminal Vin-.
The collector of the first triode Q1 is connected with one end of a fourth resistor R4 and the base of the second triode Q2 through a first capacitor C1, the other end of the fourth resistor R4 and the emitter of the second triode Q2 are connected with a negative input terminal Vin-, the collector of the second triode Q2 is connected with the cathode of a third voltage-stabilizing diode D3, the grid of the first MOS transistor M1, the cathode of the second voltage-stabilizing diode D2 and a positive output terminal Vo +, the anode of the third voltage-stabilizing diode D3 and the source of the first MOS transistor M1 are connected with a negative input terminal Vin-, and the drain of the first MOS transistor M1 is connected with a negative output terminal Vo-.
Compared with the traditional power supply circuit, the power supply circuit 11 has the advantages that the number of used components is small, the circuit structure is simple, and therefore hardware cost can be reduced. The first capacitor C1 is a coupling capacitor for preventing interference between the first transistor Q1 and the second transistor Q2, so that the safety and reliability of the circuit are high. It should be noted that in the present embodiment, the capacitance value of the first capacitor C1 is 500pF, and certainly, in practical applications, the capacitance value of the first capacitor C1 may also be adjusted accordingly according to specific situations.
The first diode D1 is connected in parallel with the DC input power supply, when the DC input power supply is connected reversely, namely the positive input end Vin + is connected with the DC input power supply cathode, the negative input end Vin-is connected with the DC input power supply anode, at this moment, the first diode D1 is conducted to generate a large short-circuit current to prompt the DC input power supply to carry out overcurrent protection or blow a fuse in the circuit to remind a user, the first diode D1 is cut off reversely when in normal work, the system efficiency loss is zero, no voltage drop is generated because no series circuit is connected, no loss is generated, and the input back voltage can not damage the subsequent switch power supply.
The second zener diode D2 obtains the working current through the third resistor R3 and is still in a regulated state, and the terminal voltage of the first resistor R1 is obtained by dividing the voltage of the first resistor R1 and the second resistor R2, which is not enough to turn on the base to the emitter of the first transistor Q1, and the first transistor Q1 is turned off, then,due to the existence of the fourth resistor R4, the pull-down effect is achieved, the collector of the first triode Q1 outputs low level, the second triode Q2 is in a cut-off state at the moment, and the voltage stabilizing voltage of the third voltage stabilizing diode D3 is larger than the turn-on voltage V of the first MOS transistor M1GSAnd the first MOS transistor M1 is in a saturated conduction state, so that the voltage of the direct current input power supply is completely added to the positive output end Vo + and the negative output end Vo-, and the subsequent switching power supply circuit is electrified to work normally. According to the above working state, the first MOS transistor M1 is connected in series in the loop from the positive input terminal Vin + to the negative output terminal Vo —, that is, in the so-called ground loop, the first MOS transistor M1 can be directly driven by the dc input power through the third zener diode D3, the on-resistance (rds (on)) after the first MOS transistor M1 is turned on is very low, the insertion loss is low, and the static power consumption is very low in normal times; since no booster circuit is used, the static power consumption is further reduced.
When the direct current input power supply is over-voltage, the second voltage-stabilizing diode D2 obtains the working current through the third resistor R3, and is still in a voltage-stabilizing state, and the terminal voltage of the first resistor R1 is obtained by dividing the voltage of the first resistor R1 and the second resistor R2, but is enough to make the base electrode of the first triode Q1 conduct to the emitter electrode, the first triode Q1 conduct, the collector electrode of the first triode Q1 outputs high level, at this time, the second triode Q2 is in an amplifying state, the second triode Q2 is actually in a saturated conduction state, the voltage-stabilizing voltage of the third voltage-stabilizing diode D3 is equal to the saturated conduction voltage drop of the second triode Q2, generally less than 0.3V, and far less than the turn-on voltage V of the first MOS transistor M1 due to the saturated conduction of the second triode Q2GSWhen the first MOS transistor M1 is in the off state, the voltage of the dc input power cannot be applied to the positive output terminal Vo + and the negative output terminal Vo-, and the subsequent switching power supply circuit stops operating because there is no input voltage. In the event of an overvoltage, the first MOS transistor M1, which is protected against overvoltage, is not easily damaged by being turned off, i.e., turned off.
It should be noted that in this embodiment, the first transistor Q1 is a PNP transistor, the second transistor Q2 is an NPN transistor, and the first MOS transistor M1 is an N-channel MOS transistor. Certainly, in practical applications, the first transistor Q1 may also be an NPN transistor, the second transistor Q2 may also be a PNP transistor, and the first MOS transistor M1 may also be a P-channel MOS transistor, but the structure of the circuit is also changed accordingly.
In this embodiment, the power supply circuit 11 further includes a fourth diode D4, an anode of the fourth diode D4 is connected to a cathode of the second zener diode D2, and a cathode of the fourth diode D4 is connected to the negative output terminal Vo-. The fourth diode D4 is a current-limiting diode, and is used for current-limiting protection of the branch between the first transistor Q1 and the second transistor Q2, so as to further enhance the safety and reliability of the circuit. It should be noted that in the present embodiment, the model of the fourth diode D4 is S-562, and in practical applications, other models of diodes with similar functions may be selected as the fourth diode D4.
In this embodiment, the power supply circuit 11 further includes a second capacitor C2, one end of the second capacitor C2 is connected to the collector of the second transistor Q2, and the other end of the second capacitor C2 is connected to the gate of the first MOS transistor M1. The second capacitor C2 is a coupling capacitor for preventing interference between the second transistor Q2 and the first MOS transistor M1, so as to further enhance the safety and reliability of the circuit. It should be noted that in the present embodiment, the capacitance of the second capacitor C2 is 460pF, and certainly, in practical applications, the capacitance of the second capacitor C2 may be adjusted accordingly according to specific situations.
In this embodiment, the power supply circuit 11 further includes a fifth resistor R5, one end of the fifth resistor R5 is connected to the emitter of the second transistor Q2, and the other end of the fifth resistor R5 is connected to the negative input terminal Vin-. The fifth resistor R5 is a current limiting resistor, and is used for performing current limiting protection on the emitter current of the second transistor Q2, so as to further enhance the current limiting effect. It should be noted that, in the embodiment, the resistance of the fifth resistor R5 is 33k Ω, and certainly, in practical applications, the resistance of the fifth resistor R5 may be adjusted accordingly according to specific situations.
Fig. 3 is a schematic circuit diagram of a power protection circuit in this embodiment, in fig. 3, the power protection circuit 6 includes a dc power source VCC, a relay, a third transistor Q3, a fourth transistor Q4, a second MOS transistor M2, a sixth resistor R6, a seventh resistor R7, an eighth sliding resistor R8, a third capacitor C3, a fourth capacitor C4, a light emitting diode LED, and a voltage output terminal OUT, wherein a moving contact K-1 of the relay is connected to the dc power source VCC, the dc power source VCC is connected to the microprocessor 5, a stationary contact K-2 of the relay is connected to a collector of the third transistor Q3 and one end of the fourth capacitor C4, an emitter of the third transistor Q3 is connected to one end of a coil K of the relay, the other end of the coil K of the relay is grounded, a base of the third transistor Q3 is connected to the other end of the fourth capacitor C4 and one end of the sixth resistor R6, the other end of the sixth resistor R6 is grounded, one fixed end of the eighth sliding varistor R8 is connected to one end of the fourth capacitor C4, the drain of the second MOS transistor M2, the collector of the fourth triode Q4 and one end of the third capacitor C3, the other fixed end and the sliding end of the eighth sliding varistor R8 are connected to one end of the seventh resistor R7 and the base of the fourth triode Q4, the other end of the seventh resistor R7 is grounded, the emitter of the fourth triode Q4 is connected to the power output terminal OUT, the gate of the second MOS transistor M2 is connected to one end of the third capacitor C3 and the anode of the light emitting diode LED, the cathode of the light emitting diode LED is grounded, and the source of the second MOS transistor M2 is connected to the voltage output terminal OUT.
Compared with the traditional power supply circuit, the power supply protection circuit 6 has the advantages that the number of used components is small, the circuit structure is simple, and therefore hardware cost can be reduced. The third capacitor C3 is a coupling capacitor for preventing interference between the fourth transistor Q4 and the second MOS transistor M2; the fourth capacitor C4 is a coupling capacitor for preventing interference between the third transistor Q3 and the second MOS transistor M2, so that the circuit has high safety and reliability. It should be noted that, in the embodiment, the capacitance of the third capacitor C3 is 300pF, and the capacitance of the fourth capacitor C4 is 450pF, and certainly, in practical applications, the capacitance of the third capacitor C3 and the capacitance of the fourth capacitor C4 may be adjusted accordingly according to specific situations.
In this embodiment, the power protection circuit 6 further includes a fifth diode D5, an anode of the fifth diode D5 is connected to the drain of the second MOS transistor M2, and a cathode of the fifth diode D5 is connected to the collector of the fourth transistor Q4. The fifth diode D5 is a current limiting diode for current limiting protection of the collector current of the fourth transistor Q4, so as to further enhance the safety and reliability of the circuit. It should be noted that in the present embodiment, the model of the fifth diode D5 is e-501, and certainly, in practical applications, other models of diodes with similar functions may be selected as the fifth diode D5.
In this embodiment, the power protection circuit 6 further includes a ninth resistor R9, one end of the ninth resistor R9 is connected to the emitter of the fourth transistor Q4, and the other end of the ninth resistor R9 is connected to the voltage output terminal OUT. The ninth resistor R9 is a current limiting resistor, and is used for current limiting protection of the emitter current of the fourth transistor Q4, so as to further enhance the safety and reliability of the circuit. It should be noted that in the present embodiment, the resistance of the ninth resistor R9 is 36k Ω, and certainly, in practical applications, the resistance of the ninth resistor R9 may be adjusted accordingly according to specific situations.
In this embodiment, the power protection circuit 6 further includes a fifth capacitor C5, one end of the fifth capacitor C5 is connected to one end of a seventh resistor R7, and the other end of the fifth capacitor C5 is connected to the base of the fourth transistor Q4. The fifth capacitor C5 is a coupling capacitor for preventing interference between the second MOS transistor M2 and the fourth transistor Q4, so as to further enhance the safety and reliability of the circuit. It should be noted that the capacitance of the fifth capacitor C5 is 500pF, and of course, in practical applications, the capacitance of the fifth capacitor C5 may be adjusted accordingly according to specific situations.
In short, in this embodiment, the plurality of cameras 12 are integrated into the imaging apparatus 1, which not only saves cost, but also reduces complexity of wiring, and facilitates and simplifies wiring. The display 7 can display a plurality of images in an array arrangement mode, and compared with the traditional power supply circuit, the power supply circuit 11 has fewer used components and simpler circuit structure, so that the hardware cost can be reduced. In addition, since the power supply circuit 11 is provided with a coupling capacitor, the safety and reliability of the circuit are high.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A multi-picture image array display system is characterized by comprising an integrated camera device, a plurality of data receiving modules, a storage module, a microprocessor, a display control module, a display interface module, a display and a power supply protection circuit, wherein the integrated camera device comprises a power supply circuit and a plurality of cameras, the cameras are all connected with the power supply circuit, the storage module is connected with the microprocessor and used for storing preset image array values, each data receiving module acquires original images acquired by the cameras connected with the data receiving module and sends the original images to the microprocessor, the display interface module acquires parameters of the display and sends the parameters to the microprocessor, the microprocessor sends the preset image array values and the parameters of the display to the display control module, the display control module calculates an image scaling coefficient, the microprocessor controls each original image to be scaled according to the image scaling coefficient to obtain a processed image, each processed image is sent to the display through the display interface module and is displayed on the display in an array arrangement mode, and the power supply protection circuit is connected with the microprocessor and used for protecting a power supply;
the power supply circuit comprises a positive input end, a negative input end, a positive output end, a negative output end, a first diode, a first resistor, a second voltage-stabilizing diode, a first triode, a third resistor, a first capacitor, a fourth resistor, a second triode, a third voltage-stabilizing diode and a first MOS (metal oxide semiconductor) tube, wherein the cathode of the first diode is connected with the positive input end, the anode of the first diode is connected with the negative input end, the cathode of the first diode is also respectively connected with one end of the first resistor and the cathode of the second voltage-stabilizing diode, the base of the first triode is respectively connected with the other end of the first resistor and one end of the second resistor, the other end of the second resistor is connected with the negative input end, and the emitter of the first triode is respectively connected with the anode of the second voltage-stabilizing diode and one end of the third resistor, the other end of the third resistor is connected with the negative electrode input end;
a collector of the first triode is respectively connected with one end of a fourth resistor and a base of a second triode through the first capacitor, the other end of the fourth resistor and an emitter of the second triode are respectively connected with the negative input end, a collector of the second triode is respectively connected with a cathode of a third voltage stabilizing diode, a grid of a first MOS (metal oxide semiconductor) tube, a cathode of a second voltage stabilizing diode and an anode output end, an anode of the third voltage stabilizing diode and a source of the first MOS tube are respectively connected with the negative input end, a drain of the first MOS tube is connected with the negative output end, and a capacitance value of the first capacitor is 500 pF;
the power supply circuit of the power supply also comprises a fourth diode, the anode of the fourth diode is connected with the cathode of the second voltage stabilizing diode, the cathode of the fourth diode is connected with the cathode output end, and the model of the fourth diode is S-562;
the power supply circuit further comprises a second capacitor, one end of the second capacitor is connected with a collector electrode of the second triode, the other end of the second capacitor is connected with a grid electrode of the first MOS tube, and the capacitance value of the second capacitor is 460 pF.
2. The system of claim 1, wherein the power supply circuit further comprises a fifth resistor, one end of the fifth resistor is connected to the emitter of the second transistor, the other end of the fifth resistor is connected to the negative input terminal, and the resistance of the fifth resistor is 33k Ω.
3. The system of claim 1 or 2, wherein the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the first MOS transistor is an N-channel MOS transistor.
4. The multivision display system of claim 1 or 2, wherein the power protection circuit comprises a dc power source, a relay, a third transistor, a fourth transistor, a second MOS transistor, a sixth resistor, a seventh resistor, an eighth sliding rheostat, a third capacitor, a fourth capacitor, a light emitting diode and a voltage output terminal, a moving contact of the relay is connected to the dc power source, a fixed contact of the relay is connected to a collector of the third transistor and one end of the fourth capacitor, respectively, an emitter of the third transistor is connected to one end of a coil of the relay, the other end of the coil of the relay is grounded, a base of the third transistor is connected to the other end of the fourth capacitor and one end of the sixth resistor, respectively, the other end of the sixth resistor is grounded, and a fixed end of the eighth sliding rheostat is connected to one end of the fourth capacitor, respectively, The drain electrode of the second MOS tube, the collector electrode of the fourth triode and one end of the third capacitor are connected, another fixed end and the sliding end of the eighth sliding rheostat are respectively connected with one end of the seventh resistor and the base electrode of the fourth triode, the other end of the seventh resistor is grounded, the emitter electrode of the fourth triode is connected with the power output end, the grid electrode of the second MOS tube is respectively connected with one end of the third capacitor and the anode of the light-emitting diode, the cathode of the light-emitting diode is grounded, the source electrode of the second MOS tube is connected with the voltage output end, the capacitance value of the third capacitor is 300pF, and the capacitance value of the fourth capacitor is 450 pF.
5. The multivision image array display system of claim 4, wherein the power protection circuit further comprises a fifth diode, an anode of the fifth diode is connected to the drain of the second MOS transistor, a cathode of the fifth diode is connected to the collector of the fourth transistor, and the fifth diode is of type e-501.
6. The system of claim 5, wherein the power protection circuit further comprises a ninth resistor, one end of the ninth resistor is connected to the emitter of the fourth transistor, the other end of the ninth resistor is connected to the voltage output terminal, and the ninth resistor has a resistance of 36k Ω.
7. The multivision display system of claim 6, wherein the power protection circuit further comprises a fifth capacitor, one end of the fifth capacitor is connected to one end of the seventh resistor, the other end of the fifth capacitor is connected to the base of the fourth transistor, and the capacitance of the fifth capacitor is 500 pF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810005869.3A CN108234947B (en) | 2018-01-03 | 2018-01-03 | Multi-picture image array display system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810005869.3A CN108234947B (en) | 2018-01-03 | 2018-01-03 | Multi-picture image array display system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108234947A CN108234947A (en) | 2018-06-29 |
| CN108234947B true CN108234947B (en) | 2020-09-15 |
Family
ID=62645165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810005869.3A Active CN108234947B (en) | 2018-01-03 | 2018-01-03 | Multi-picture image array display system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108234947B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006304154A (en) * | 2005-04-25 | 2006-11-02 | Nisco Kk | Television camera apparatus for inspecting reactor internals |
| CN1878260A (en) * | 2006-07-14 | 2006-12-13 | 杭州国芯科技有限公司 | Multi-menu co-screen playing method |
| CN101286314A (en) * | 2008-05-26 | 2008-10-15 | 杭州华三通信技术有限公司 | Multi-picture splicing method and device |
| CN201440702U (en) * | 2009-05-06 | 2010-04-21 | 上海十加信息技术有限公司 | Actual space high-definition 360-degree interactive panoramic image data acquisition system |
| CN104242249A (en) * | 2014-09-17 | 2014-12-24 | 广州金升阳科技有限公司 | Protective circuit of switching power supply |
| CN104684144A (en) * | 2013-11-29 | 2015-06-03 | 成都市幻多奇软件有限公司 | Power control circuit used for multimedia projector |
-
2018
- 2018-01-03 CN CN201810005869.3A patent/CN108234947B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006304154A (en) * | 2005-04-25 | 2006-11-02 | Nisco Kk | Television camera apparatus for inspecting reactor internals |
| CN1878260A (en) * | 2006-07-14 | 2006-12-13 | 杭州国芯科技有限公司 | Multi-menu co-screen playing method |
| CN101286314A (en) * | 2008-05-26 | 2008-10-15 | 杭州华三通信技术有限公司 | Multi-picture splicing method and device |
| CN201440702U (en) * | 2009-05-06 | 2010-04-21 | 上海十加信息技术有限公司 | Actual space high-definition 360-degree interactive panoramic image data acquisition system |
| CN104684144A (en) * | 2013-11-29 | 2015-06-03 | 成都市幻多奇软件有限公司 | Power control circuit used for multimedia projector |
| CN104242249A (en) * | 2014-09-17 | 2014-12-24 | 广州金升阳科技有限公司 | Protective circuit of switching power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108234947A (en) | 2018-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104577993B (en) | Switching Power Supply input voltage protection circuit | |
| US9935490B2 (en) | Terminal and battery charging control device and method thereof for realizing overcurrent and/or overvoltage protection | |
| US20120098461A1 (en) | Power supply detecting circuit | |
| CN108173537B (en) | Restart circuit and electronic equipment | |
| CN108259826B (en) | Image acquisition and transmission system for displaying multiple images on same picture | |
| CN210724722U (en) | Hot plug control circuit | |
| CN108234947B (en) | Multi-picture image array display system | |
| CN104298331A (en) | Power supply circuit for power supply control chip | |
| CN115294923B (en) | Voltage stabilizing circuit and display panel | |
| CN218829101U (en) | Clamping protection circuit | |
| CN111934275A (en) | Overcurrent protection circuit, control circuit, chip and control method | |
| CN203553906U (en) | Protection circuit for input voltage of switch power supply | |
| CN211579897U (en) | Drive circuit and pump device using same | |
| CN105807878A (en) | An electronic apparatus power supply protection system | |
| CN204928080U (en) | Overvoltage protection circuit | |
| CN111398852A (en) | Power output short circuit detection circuit and electronic equipment | |
| CN211127140U (en) | Circuit protection device and system | |
| CN214900157U (en) | Load short-circuit protection circuit | |
| CN213185869U (en) | Power failure accelerating circuit, power supply circuit, driving board card and electronic equipment | |
| CN107230969A (en) | A kind of power supply overvoltage protection circuit | |
| CN211151823U (en) | Display device, switching power supply output circuit and overvoltage protection circuit | |
| CN212970189U (en) | LED backlight short-circuit protection circuit and electronic equipment | |
| CN214380096U (en) | Touch screen safety power supply circuit, touch screen and electrical equipment | |
| CN213341629U (en) | DC power supply electrostatic surge protection circuit and power supply system | |
| CN220209948U (en) | Multi-power-supply circuit with overvoltage and undervoltage protection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200727 Address after: Room 507, No.268, Baogang Avenue, Haizhu District, Guangzhou City, Guangdong Province 510000 Applicant after: Guangzhou luboyi Information Technology Co., Ltd Address before: 510000 Haizhuqu District South Road, Guangzhou, Guangzhou, Guangdong, No. 19, No. 106-2, No. 106-2 Applicant before: GUANGZHOU AIYIXUE INTELLIGENT INFORMATION TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |