CN105679226B - Power good signal output method and device - Google Patents
Power good signal output method and device Download PDFInfo
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- CN105679226B CN105679226B CN201511006305.4A CN201511006305A CN105679226B CN 105679226 B CN105679226 B CN 105679226B CN 201511006305 A CN201511006305 A CN 201511006305A CN 105679226 B CN105679226 B CN 105679226B
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Abstract
The invention provides a power good signal output method and a device, wherein the device comprises the following steps: the voltage division module is provided with an enabling switch and is used for converting the input power supply voltage into detection divided voltage for judgment, and the enabling switch responds to an enabling signal; the forward judgment module or the reverse judgment module judges the detection partial pressure through the forward judgment module when the enable switch is connected to the partial pressure module and is close to the high potential end, and judges the detection partial pressure through the reverse judgment module and outputs a mark signal when the enable switch is connected to the partial pressure module and is close to the low potential end; and the logic AND gate is used for processing the enable signal and the mark signal and outputting a power good signal. The invention can realize zero-power consumption quiescent current under a deep sleep or shutdown mode, solve the problems of competition and risk caused by different delays of the enabling switch and the judging module, eliminate the burr phenomenon in actual response output and improve the judgment accuracy of the good state of the power supply.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a power good signal output method and device.
Background
With the increasing popularization of smart phones, people also put higher and higher requirements on the display effect of mobile intelligent terminals, and the wide-screen high-resolution high-performance display effect becomes the mainstream. Therefore, the display driver chip functionality and performance of the handheld device also pose increasing challenges.
The charge pump in the important multi-output power management unit in the display driving chip provides positive and negative bias voltage for the liquid crystal, and the charge pump module can reach a stable state only by charging and discharging in a plurality of clock cycles in the process of power-on starting or power-off power failure, so that the state of multi-path positive and negative output voltage of the charge pump module is detected, and the orderly starting of the load circuit is particularly important.
On the other hand, with the improvement of the screen resolution of the handheld device, for wide-screen high-resolution displays such as WVGA and HD, under the condition of a certain frame frequency, the voltage driving output for GAMMA curve correction required for display needs to reach a 95% steady-state value within 1/3 line time, and thus, as the pixel dot matrix increases, the current also increases proportionally, and therefore, under the condition of a large current, it is important to detect the abnormality of the output voltage/current so as to start a protection circuit or prevent other responses such as latch-up (latch effect), and thus, a higher challenge is provided for the stability and the quick response capability of the power supply good output unit for detecting and feeding back the states of the output voltage and the current.
The power detection circuit structure of the display driver chip is generally shown in fig. 1, the multi-output power management unit 10 outputs a plurality of power voltages VDD1 to VDDN, each subunit 20 of the power good output unit respectively detects the power voltages VDD1 to VDDN, if the good output state is satisfied, the power good signals VDD1_ powered good to VDDN _ powered good are respectively output, and then all the power good signals are logically anded to determine the good output state of all the power outputs, so as to start the load or the protection circuit unit 30.
Fig. 2 shows a block diagram of a conventional power supply good output subunit, and fig. 3 and 4 show circuit diagrams of two exemplary embodiments of the conventional power supply good output subunit. The conventional power good output subunit 20 includes a voltage dividing module 21, a judging module 22 and a logic and gate 23. The voltage dividing module 21 converts the power voltage VDDN input by the multi-output power management unit 10 into a detectable divided voltage VDDN' through resistive voltage division. In order to reduce the overall power consumption of the display driving chip, an enable switch 24 is disposed in the voltage dividing module 21, and the enable switch 24 responds to an enable signal, and through the control of an enable signal EN, the static power consumption of the voltage dividing resistor string is zero in the deep sleep or shutdown mode. The judging module 22 is used for judging the detected divided voltage VDDN' and outputting a FLAG signal FLAG. The judging module 22 can comprise a single or a plurality of series-connected schmitt inverters 25, and the implementation of the schmitt inverters is completely based on digital CMOS complementary logic circuits, so that the influence of static power consumption does not exist; the comparison accuracy is determined by the size proportion of the complementary PMOS and NMOS transistors realized by a specific circuit and the power supply voltage DVDD generated by the LDO (low dropout regulator) in the chip, an additional reference voltage generating circuit is not needed, and the influence of offset voltage is avoided. The logic and gate 23 is used to and the enable signal EN and the FLAG signal FLAG, and output the power good signal VDDN _ power.
Taking the power supply voltage VDDN input by the multi-output power management unit 10 as a positive value (e.g., 3.0V), assuming that the positive threshold voltage of the determining module 22 is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the conventional power supply good output subunit shown in fig. 3 is as shown in fig. 5, and specifically includes the following stages:
stage 0-t 1: the enable signal EN is at a low level, that is, the enable switch 24 of the voltage divider module 21 is turned off at this time, that is, one end of the resistor string for detection is turned off from the positive power voltage end, while the other end is always coupled to the ground terminal, the detected divided voltage VDDN' is equal to the ground voltage (0V), the FLAG signal FLAG output after being determined by the schmitt inverter 25 of the determination module 22 is at a high level, and the logic and gate 23 outputs the power good signal VDDN _ power low after the enable signal EN is anded with the FLAG signal FLAG.
Stage t1-t 3: the enable signal EN is at a high level, that is, the enable switch 24 of the voltage dividing module 21 is closed, the input power voltage VDDN is at a start-up rising stage, but has not yet reached an ideal voltage state, so the detected divided voltage VDDN' converted by the voltage dividing module 21 has not yet reached a preset threshold range of the schmitt inverter 25, and ideally, the FLAG signal FLAG output after being judged by the schmitt inverter 25 should be at a low level, but due to a non-ideal characteristic of comparison by the schmitt inverter 25, there is a certain comparison delay time td, that is, the high-level FLAG signal output at time t1 will form a certain delay in the time period td, and the FLAG signal will not turn to a low level until time t2= t1+ td. Therefore, the FLAG signal output in the stage t1-t2 is at a high level, and after the enable signal EN is anded with the FLAG signal FLAG by the logic and gate 23, the output power good signal VDDN _ power good is at a high level, but at this time, the power does not really meet the good output state, so that the subsequent protection circuit is subjected to misoperation, and adverse effects are brought; the FLAG signal output during the period t2-t3 is low, and the logic and gate 23 outputs the power good signal VDDN _ power low after the enable signal EN is anded with the FLAG signal FLAG.
Stage t3-t 4: the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN' converted by the voltage dividing module 21 reaches and maintains a preset threshold range of the determining module 22, the FLAG signal FLAG output by the determining module 22 is a high level, the logic and gate 23 and the enable signal EN and the FLAG signal FLAG are anded, and then the output power supply good signal VDDN _ power is a high level, at this time, the power supply voltage really meets a good output state.
Based on the same principle, the signal response output process of the conventional power good output subunit shown in fig. 4 is also similar to that of the above embodiment, and is not described herein again.
Therefore, due to the problems of competition and risk caused by different delays of the enable switch and the judgment module, a burr phenomenon (at the stage t1-t 2) occurs in actual response output, the judgment accuracy of a good state of a power supply is influenced, the subsequent protection circuit is subjected to misoperation, and the overall performance of the display driving chip is further influenced.
Disclosure of Invention
The invention aims to provide a power good signal output method and a power good signal output device, which can improve the judgment accuracy of a power good state and improve the overall performance of a display driving chip.
In view of the above, one aspect of the present invention provides a power good signal output method, including the steps of:
converting input power supply voltage into detection divided voltage for judgment through a voltage dividing module with an enabling switch, wherein the enabling switch responds to an enabling signal, the power supply voltage is a positive value or a negative value, and the enabling switch is connected to the high potential end in the voltage dividing module;
judging the detected partial pressure through a forward judgment module, and outputting a mark signal;
and processing the enabling signal and the marking signal through a logic AND gate, and outputting a power good signal.
Preferably, when the power supply voltage is a positive value, the enable switch is connected to a power supply voltage end in the voltage dividing module, wherein the signal response output process includes the following stages:
stage 0-T1: enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at the low level, and marking the signal to be at the low level;
stages T1-T2: enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;
stages T2-T3: enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;
stages T3-T4: enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at a high level, and marking the signal to be at a low level;
post-stage T4: the enable signal is at low level, the detection divided voltage is equal to the ground voltage, the flag signal is at low level, and the power good signal is at low level.
Preferably, the forward judgment module comprises a hysteresis comparator or an even number of inverters connected in series, and the inverters comprise at least one schmitt inverter connected close to the output end of the voltage division module.
Preferably, the schmitt inverter is powered by a built-in power supply.
Another aspect of the present invention provides a power good signal output method, including the following steps:
converting input power supply voltage into detection divided voltage for judgment through a voltage dividing module with an enabling switch, wherein the enabling switch responds to an enabling signal, the power supply voltage is a positive value or a negative value, and the enabling switch is connected to the end, close to a low potential, in the voltage dividing module;
judging the detected partial pressure through a reverse judgment module, and outputting a mark signal;
and processing the enabling signal and the marking signal through a logic AND gate, and outputting a power good signal.
Preferably, when the power voltage is a positive value, the enable switch is connected to a ground terminal in the voltage dividing module, wherein the signal response output process includes the following steps:
stage 0-T1': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at low level, and marking the signal to be at low level;
stage T1 '-T2': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;
stage T2 '-T3': enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;
stage T3 '-T4': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at high level, and marking the signal to be at low level;
post stage T4': the enable signal is at low level, the detected divided voltage is equal to the power supply voltage, the flag signal is at low level, and the power good signal is at low level.
Preferably, the reverse judgment module comprises a hysteresis comparator or a single schmitt inverter or an odd number of inverters connected in series, and the inverters comprise at least one schmitt inverter connected close to the output end of the voltage division module.
Preferably, the schmitt inverter is powered by a built-in power supply.
Still another aspect of the present invention provides a power good signal output apparatus, including:
the voltage division module is provided with an enabling switch and is used for converting input power voltage into detection divided voltage for judgment, the enabling switch responds to an enabling signal, the power voltage is a positive value or a negative value, and the enabling switch is connected to the high potential end in the voltage division module;
the forward judgment module is used for judging the detection partial pressure and outputting a mark signal;
and the logic AND gate is used for processing the enable signal and the mark signal and outputting a power good signal.
Preferably, the forward judgment module comprises a hysteresis comparator or an even number of inverters connected in series, and the inverters comprise at least one schmitt inverter connected close to the output end of the voltage division module.
Preferably, the schmitt inverter is powered by a built-in power supply.
Still another aspect of the present invention provides a power good signal output apparatus, including:
the voltage division module is provided with an enabling switch and is used for converting input power voltage into detection divided voltage for judgment, the enabling switch responds to an enabling signal, the power voltage is a positive value or a negative value, and the enabling switch is connected to the end, close to a low potential, in the voltage division module;
the reverse judgment module is used for judging the detection partial pressure and outputting a mark signal;
and the logic AND gate is used for processing the enable signal and the mark signal and outputting a power good signal.
Preferably, the reverse judgment module comprises a hysteresis comparator or a single schmitt inverter or an odd number of inverters connected in series, and the inverters comprise at least one schmitt inverter connected close to the output end of the voltage division module.
Preferably, the schmitt inverter is powered by a built-in power supply.
According to the power good signal output method and device, the connection mode of the enable switch and the judgment mode of the judgment module are reasonably configured, so that zero-power-consumption quiescent current can be realized in a deep sleep or shutdown mode, the problems of competition and risk caused by different time delays of the enable switch and the judgment module can be solved, the burr phenomenon in actual response output is eliminated, the judgment accuracy of the good state of the power is improved, and the overall performance of the display driving chip is improved.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.
FIG. 1 is a diagram of a power detection circuit of a conventional display driver chip;
FIG. 2 is a block diagram of a conventional power supply and output subunit;
fig. 3 and 4 are circuit diagrams of a conventional power supply good output subunit;
FIG. 5 is a diagram illustrating the effect of a conventional power supply with a good output subunit;
FIG. 6(A) is a circuit diagram of a power supply sub-unit according to a first embodiment of the present invention;
FIG. 6(B) is a diagram illustrating the effect of the power supply sub-unit according to the first embodiment of the present invention;
FIG. 7(A) is a circuit diagram of a power supply sub-unit according to a second embodiment of the present invention;
fig. 7(B) is an effect diagram of the power supply good output subunit according to the second embodiment of the invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
In order to solve the problems in the prior art, the invention provides a power good signal output method and a power good signal output device, which can realize zero-power consumption quiescent current in a deep sleep or shutdown mode and solve the problems of competition and risk caused by different delays of an enable switch and a judgment module by reasonably configuring the connection mode of the enable switch and the judgment mode of the judgment module, eliminate the burr phenomenon in actual response output, improve the judgment accuracy of a power good state and improve the overall performance of a display driving chip.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Example one
Fig. 6(a) shows a circuit diagram of the power good signal output subunit according to the first embodiment of the present invention, and fig. 6(B) shows an effect diagram of the power good signal output subunit according to the first embodiment of the present invention.
As shown in fig. 6(a), the power good signal output subunit of the present invention includes a voltage dividing module 121 with an enable switch 124, a positive determination module 122 and a logic and gate 123, wherein the input power voltage VDDN is a positive value, and the enable switch 124 is close to a high potential terminal, i.e., a power voltage terminal (VDDN terminal).
The voltage dividing module 121 converts the input power voltage VDDN into a detection divided voltage VDDN' for determination through resistance voltage division. Because the voltage dividing module 121 is provided with the enable switch 124 responding to the enable signal EN, the static power consumption of the voltage dividing resistor string can be zero in the deep sleep or shutdown mode through the control of the enable signal EN.
The forward determination module 122 is configured to determine the detected divided voltage VDDN' and output a FLAG signal FLAG. Instead of two schmitt inverters 125 connected in series as shown in the present embodiment, an even number of schmitt inverters 125 connected in series may be used, and the number of the inverters includes at least one schmitt inverter 125 connected near the output end of the voltage dividing module 121 to increase the driving capability, or a hysteresis comparator may be directly used.
The logic and gate 123 is used to and the enable signal EN and the FLAG signal FLAG, and output the power good signal VDDN _ power.
Taking the example that VDDN of the power supply voltage inputted by the multi-output power management unit is 3.0V, assuming that the positive threshold voltage of the determination module is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the power supply good output subunit of this embodiment is as shown in fig. 6(B), and specifically includes the following stages:
stage 0-T1: the enable signal EN is at a low level, that is, the enable switch 124 of the voltage divider module 121 is turned off at this time, that is, one end level of the resistor string for detection is disconnected from the positive power voltage end, while the other end is always coupled to the ground terminal, the detected divided voltage VDDN' is equal to the ground voltage (0V), the FLAG signal FLAG output after being determined by the forward determination module 122 is at a low level, and the logic and gate 123 takes the enable signal EN and the FLAG signal FLAG and outputs the power good signal VDDN _ power at a low level;
stages T1-T2: the enable signal EN is high, i.e. the enable switch 124 of the voltage divider 121 is closed, the input power voltage VDDN is in the startup rising phase, however, the ideal voltage state is not reached yet, so the detected divided voltage VDDN' converted by the voltage dividing module 121 does not reach the preset threshold range of the forward judging module 122 yet, and the FLAG signal FLAG output after being judged by the forward judging module 122 should be a low level in an ideal case, although there is a certain comparison delay time td due to the non-ideal characteristic compared by the forward judging module 122, however, the logic state of the FLAG signal output at the time T1 is also low, so that the FLAG signal output at the stage T1-T2 is not affected, the FLAG signals output at the whole stage T1-T2 are all low, and the logic and gate 123 outputs the power good signal VDDN _ power low after the enable signal EN is anded with the FLAG signal FLAG;
stages T2-T3: the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN' converted by the voltage dividing module 121 reaches and maintains a preset threshold range of the forward determination module 122, the FLAG signal FLAG output by the forward determination module 122 is a high level, and the logic and gate 123 takes the enable signal EN and the FLAG signal FLAG and outputs the power supply good signal VDDN _ power as a high level;
post-stage T3: the enable signal EN is at a low level, that is, the enable switch 124 of the voltage divider module 121 is turned off, and it detects that the divided voltage VDDN' is equal to the ground voltage (0V) again, ideally, the FLAG signal FLAG output after being judged by the forward judgment module 122 should be at a low level, but due to the non-ideal characteristic compared by the forward judgment module 122, there is a certain comparison delay time td, that is, the high level FLAG signal output at time T3 will form a certain delay in a time period td, and the output power good signal VDDN _ power is at a low level until time T4= T3+ td, but in the stage after the whole T3, the logic and gate 123 takes the enable signal EN and the FLAG signal FLAG phase and then outputs the power good signal VDDN _ power at a low level, which indicates that the power voltage n is no longer in a good output state, that is, the power off state.
Example two
Fig. 7(a) shows a circuit diagram of the power good signal output subunit according to the second embodiment of the present invention, and fig. 7(B) shows an effect diagram of the power good signal output subunit according to the second embodiment of the present invention.
As shown in fig. 7(a), the power good signal output subunit of the present invention includes a voltage division module 221 with an enable switch 224, a reverse determination module 222 and a logic and gate 223, wherein the input power voltage VDDN is a positive value, and the enable switch 224 is close to a low potential terminal, i.e., a ground terminal (GND terminal).
The voltage divider 221 converts the input power voltage VDDN into a detection divided voltage VDDN' for determination through resistive voltage division. Because the voltage dividing module 221 is provided with the enable switch 224 responding to the enable signal EN, the static power consumption of the voltage dividing resistor string can be zero in the deep sleep or shutdown mode through the control of the enable signal EN.
The reverse determination module 222 is configured to determine the detected divided voltage VDDN' and output a FLAG signal FLAG. Instead of the single schmitt inverter 225 shown in this embodiment, an odd number of inverters connected in series may be used, and the inverters include at least one schmitt inverter 225 connected near the output end of the voltage dividing module 221 to increase the driving capability, or a hysteresis comparator may be directly used.
The logic and gate 223 is used to and the enable signal EN and the FLAG signal FLAG, outputting the power good signal VDDN _ power.
Taking the example that VDDN of the power supply voltage inputted by the multi-output power management unit is 3.0V, assuming that the positive threshold voltage of the determination module is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the power supply good output subunit of this embodiment is as shown in fig. 7(B), and specifically includes the following stages:
stage 0-T1': the enable signal EN is at a low level, that is, the enable switch 224 of the voltage divider module 221 is turned off at this time, that is, one end of the resistor string for detection is turned off from ground, while the other end is always coupled to the positive power voltage, the detected divided voltage VDDN' is equal to the power voltage VDDN (3V), the FLAG signal FLAG output after the determination by the reverse determination module 222 is at a low level, and the logic and gate 223 takes the enable signal EN and the FLAG signal FLAG and then outputs the power good signal VDDN _ power at a low level;
stage T1 '-T2': the enable signal EN is high, i.e. the enable switch 224 of the voltage divider module 221 is closed, the input power voltage VDDN is in the startup rising phase, however, the ideal voltage state is not reached yet, and therefore, the detected divided voltage VDDN' converted by the voltage dividing module 221 does not reach the preset threshold range of the reverse direction determining module 222 yet, the FLAG signal FLAG output after being determined by the reverse direction determining module 222 should be at a low level in an ideal situation, although there is a certain comparison delay time td due to the non-ideal characteristic compared by the reverse direction determining module 222, however, the logic state of the FLAG signal output at the time T1 ' is also low, so that the FLAG signal output at the stage T1 ' -T2 ' is not affected, the FLAG signals output at the whole stage T1 ' -T2 ' are all low, and after the enable signal EN is anded with the FLAG signal FLAG, the power good signal VDDN _ power good signal output is low by the logic and gate 223;
stage T2 '-T3': the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN' converted by the voltage dividing module 221 reaches and maintains a preset threshold range of the reverse determination module 222, the FLAG signal FLAG output by the reverse determination module 222 is a high level, and after the enable signal EN is anded with the FLAG signal FLAG by the logic and gate 223, the output power supply good signal VDDN _ power is a high level;
post stage T3': the enable signal EN is at a low level, that is, the enable switch 224 of the voltage dividing module 221 is turned off, and it is detected that the divided voltage VDDN ' is equal to the power supply voltage VDDN (3V) again, in an ideal case, the FLAG signal FLAG output after being determined by the inversion determining module 222 should be at a low level, but due to the non-ideal characteristic compared by the inversion determining module 222, there is a certain comparison delay time td, that is, the high level FLAG signal output at the time T3 ' will form a certain delay in a time period td, until the FLAG signal flips to a low level at the time T4 ' = T3 ' + td, but in the whole stage after T3 ', the logic and gate 223 takes the enable signal EN and the FLAG signal FLAG to be at a low level, which indicates that the power supply voltage VDDN is no longer at a good output state, that is the shutdown state.
It will be understood by those skilled in the art that the power supply good signal output method and apparatus of the present invention are also applicable to the case where the input power supply voltage VDDN is negative. When the supply voltage VDDN is negative, the high potential terminal of the voltage divider module should be the fixed voltage terminal (VDD terminal), and the low potential terminal should be the supply voltage terminal (VDDN terminal). Similarly, if the enabling switch is close to the high potential end and the detecting divided voltage VDDN 'is determined by the forward determining module, and the enabling switch is close to the low potential end and the detecting divided voltage VDDN' is determined by the reverse determining module, similar effects to those of the above embodiment can be achieved, and further description thereof is omitted.
According to the power good signal output method and device, the connection mode of the enable switch and the judgment mode of the judgment module are reasonably configured, so that zero-power-consumption quiescent current can be realized in a deep sleep or shutdown mode, the problems of competition and risk caused by different time delays of the enable switch and the judgment module can be solved, the burr phenomenon in actual response output is eliminated, the judgment accuracy of the good state of the power is improved, and the overall performance of the display driving chip is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (12)
1. A power good signal output method is characterized by comprising the following steps:
converting input power supply voltage into detection divided voltage for judgment through a voltage dividing module with an enabling switch, wherein the enabling switch responds to an enabling signal, the power supply voltage is a positive value or a negative value, and the enabling switch is connected to the high potential end in the voltage dividing module;
judging the detected partial pressure through a forward judgment module, and outputting a mark signal;
processing the enabling signal and the marking signal through a logic AND gate, and outputting a power good signal;
when the power supply voltage is a positive value, the enabling switch is connected to a power supply voltage end close to the voltage dividing module, wherein the signal response output process comprises the following stages:
stage 0-T1: enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at the low level, and marking the signal to be at the low level;
stages T1-T2: enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;
stages T2-T3: enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;
stages T3-T4: enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at a high level, and marking the signal to be at a low level;
post-stage T4: the enable signal is at low level, the detection divided voltage is equal to the ground voltage, the flag signal is at low level, and the power good signal is at low level.
2. The method of claim 1, wherein the forward decision module comprises a hysteresis comparator or an even number of inverters connected in series, the inverters comprising at least one schmitt inverter connected near an output of the voltage divider module.
3. The method of claim 2, wherein the schmitt inverter is powered by an internal power source.
4. A power good signal output method is characterized by comprising the following steps:
converting input power supply voltage into detection divided voltage for judgment through a voltage dividing module with an enabling switch, wherein the enabling switch responds to an enabling signal, the power supply voltage is a positive value or a negative value, and the enabling switch is connected to the end, close to a low potential, in the voltage dividing module;
judging the detected partial pressure through a reverse judgment module, and outputting a mark signal;
processing the enabling signal and the marking signal through a logic AND gate, and outputting a power good signal;
when the power supply voltage is a positive value, the enabling switch is connected to a ground wire end close to the voltage dividing module, wherein the signal response output process comprises the following stages:
stage 0-T1': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at low level, and marking the signal to be at low level;
stage T1 '-T2': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;
stage T2 '-T3': enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;
stage T3 '-T4': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at high level, and marking the signal to be at low level;
post stage T4': the enable signal is at low level, the detected divided voltage is equal to the power supply voltage, the flag signal is at low level, and the power good signal is at low level.
5. The method as claimed in claim 4, wherein the reverse direction decision module comprises a hysteresis comparator or a single schmitt inverter or an odd number of inverters connected in series, and the inverter comprises at least one schmitt inverter connected near the output terminal of the voltage division module.
6. The method of claim 5, wherein the Schmitt inverter is powered by an internal power source.
7. A power good signal output apparatus, comprising:
the voltage division module is provided with an enabling switch and is used for converting input power voltage into detection divided voltage for judgment, the enabling switch responds to an enabling signal, the power voltage is a positive value or a negative value, and the enabling switch is connected to the high potential end in the voltage division module;
the forward judgment module is used for judging the detection partial pressure and outputting a mark signal;
the logic AND gate is used for processing the enabling signal and the marking signal and outputting a power good signal;
when the power supply voltage is a positive value, the enabling switch is connected to a power supply voltage end close to the voltage dividing module, wherein the signal response output process comprises the following stages:
stage 0-T1: enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at the low level, and marking the signal to be at the low level;
stages T1-T2: enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;
stages T2-T3: enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;
stages T3-T4: enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at a high level, and marking the signal to be at a low level;
post-stage T4: the enable signal is at low level, the detection divided voltage is equal to the ground voltage, the flag signal is at low level, and the power good signal is at low level.
8. The device as claimed in claim 7, wherein the positive direction decision module comprises a hysteresis comparator or an even number of inverters connected in series, the inverters comprising at least one schmitt inverter connected near the output terminal of the voltage division module.
9. The powered good signal output device of claim 8, wherein the schmitt inverter is powered by an internal power source.
10. A power good signal output apparatus, comprising:
the voltage division module is provided with an enabling switch and is used for converting input power voltage into detection divided voltage for judgment, the enabling switch responds to an enabling signal, the power voltage is a positive value or a negative value, and the enabling switch is connected to the end, close to a low potential, in the voltage division module;
the reverse judgment module is used for judging the detection partial pressure and outputting a mark signal;
the logic AND gate is used for processing the enabling signal and the marking signal and outputting a power good signal;
when the power supply voltage is a positive value, the enabling switch is connected to a ground wire end close to the voltage dividing module, wherein the signal response output process comprises the following stages:
stage 0-T1': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at low level, and marking the signal to be at low level;
stage T1 '-T2': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;
stage T2 '-T3': enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;
stage T3 '-T4': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at high level, and marking the signal to be at low level;
post stage T4': the enable signal is at low level, the detected divided voltage is equal to the power supply voltage, the flag signal is at low level, and the power good signal is at low level.
11. The apparatus of claim 10, wherein the inversion decision module comprises a hysteresis comparator or a single schmitt inverter or an odd number of serially connected inverters, and the inverter comprises at least one schmitt inverter connected near the output of the voltage divider module.
12. The powered good signal output device of claim 11, wherein the schmitt inverter is powered by an internal power source.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511006305.4A CN105679226B (en) | 2015-12-29 | 2015-12-29 | Power good signal output method and device |
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| CN201511006305.4A CN105679226B (en) | 2015-12-29 | 2015-12-29 | Power good signal output method and device |
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| CN105679226A CN105679226A (en) | 2016-06-15 |
| CN105679226B true CN105679226B (en) | 2020-09-25 |
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| JPS59165520A (en) * | 1983-03-09 | 1984-09-18 | Fujitsu Ltd | Automatic initializing circuit |
| CN101394171B (en) * | 2008-10-24 | 2010-08-11 | 华中科技大学 | Static zero-consumption power-on resetting circuit |
| CN101588167B (en) * | 2009-06-18 | 2011-06-15 | 广州润芯信息技术有限公司 | Electrifying reset and undervoltage turnoff circuit |
| CN101762737A (en) * | 2009-11-09 | 2010-06-30 | 天津南大强芯半导体芯片设计有限公司 | Null voltage detection circuit and detection method thereof |
| CN102710241B (en) * | 2012-05-08 | 2015-06-03 | 卓捷创芯科技（深圳）有限公司 | Passive radio-frequency recognition power-on-reset circuit and passive radio-frequency recognition tag |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
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