CN105654885B

CN105654885B - Power good signal output method and device

Info

Publication number: CN105654885B
Application number: CN201511006301.6A
Authority: CN
Inventors: 张科; 王富中; 丁启源
Original assignee: Geke Microelectronics Shanghai Co Ltd
Current assignee: Geke Microelectronics Shanghai Co Ltd
Priority date: 2015-12-29
Filing date: 2015-12-29
Publication date: 2021-02-26
Anticipated expiration: 2035-12-29
Also published as: CN105654885A

Abstract

The invention provides a power good signal output method and a device, wherein the device comprises the following steps: the voltage division module is provided with an enabling switch and is used for converting input power supply voltage into detection divided voltage for judgment, the enabling switch responds to an enabling signal, and the power supply voltage is a positive value or a negative value; the forward judgment module or the reverse judgment module is used for judging the detection partial pressure and outputting a mark signal; and the trigger is used for processing the enabling signal and the marking signal and outputting a power good signal. The invention processes the enable signal and the mark signal by adopting the trigger to output the good signal of the power supply, not only can realize zero-power consumption quiescent current under a deep sleep or shutdown mode, but also can solve the problems of competition and risk caused by different delays of the enable switch and the judgment module, eliminate the burr phenomenon in actual response output, improve the judgment accuracy of the good state of the power supply and improve the overall performance of the display driving chip.

Description

Power good signal output method and device

Technical Field

The invention relates to the field of integrated circuits, in particular to a power good signal output method and device.

Background

With the increasing popularization of smart phones, people also put higher and higher requirements on the display effect of mobile intelligent terminals, and the wide-screen high-resolution high-performance display effect becomes the mainstream. Therefore, the display driver chip functionality and performance of the handheld device also pose increasing challenges.

The charge pump in the important multi-output power management unit in the display driving chip provides positive and negative bias voltage for the liquid crystal, and the charge pump module can reach a stable state only by charging and discharging in a plurality of clock cycles in the process of power-on starting or power-off power failure, so that the state of multi-path positive and negative output voltage of the charge pump module is detected, and the orderly starting of the load circuit is particularly important.

On the other hand, with the improvement of the screen resolution of the handheld device, for wide-screen high-resolution displays such as WVGA and HD, under the condition of a certain frame frequency, the voltage driving output for GAMMA curve correction required for display needs to reach a 95% steady-state value within 1/3 line time, and thus, as the pixel dot matrix increases, the current also increases proportionally, and therefore, under the condition of a large current, it is important to detect the abnormality of the output voltage/current so as to start a protection circuit or prevent other responses such as latch-up (latch effect), and thus, a higher challenge is provided for the stability and the quick response capability of the power supply good output unit for detecting and feeding back the states of the output voltage and the current.

The power detection circuit structure of the display driver chip is generally shown in fig. 1, the multi-output power management unit 10 outputs a plurality of power voltages VDD1 to VDDN, each subunit 20 of the power good output unit respectively detects the power voltages VDD1 to VDDN, if the good output state is satisfied, the power good signals VDD1_ powered good to VDDN _ powered good are respectively output, and then all the power good signals are logically anded to determine the good output state of all the power outputs, so as to start the load or the protection circuit unit 30.

Fig. 2 shows a block diagram of a conventional power supply good output subunit, and fig. 3 and 4 show circuit diagrams of two exemplary embodiments of the conventional power supply good output subunit. The conventional power good output subunit 20 includes a voltage dividing module 21, a judging module 22 and a logic and gate 23. The voltage dividing module 21 converts the power voltage VDDN input by the multi-output power management unit 10 into a detectable divided voltage VDDN' through resistive voltage division. In order to reduce the overall power consumption of the display driving chip, an enable switch 24 is disposed in the voltage dividing module 21, and the enable switch 24 responds to an enable signal, and through the control of an enable signal EN, the static power consumption of the voltage dividing resistor string is zero in the deep sleep or shutdown mode. The judging module 22 is used for judging the detected divided voltage VDDN' and outputting a FLAG signal FLAG. The judging module 22 can comprise a single or a plurality of series-connected schmitt inverters 25, and the implementation of the schmitt inverters is completely based on digital CMOS complementary logic circuits, so that the influence of static power consumption does not exist; the comparison accuracy is determined by the size proportion of the complementary PMOS and NMOS transistors realized by a specific circuit and the power supply voltage DVDD generated by the LDO (low dropout regulator) in the chip, an additional reference voltage generating circuit is not needed, and the influence of offset voltage is avoided. The logic and gate 23 is used to and the enable signal EN and the FLAG signal FLAG, and output the power good signal VDDN _ power.

Taking the power supply voltage VDDN input by the multi-output power management unit 10 as a positive value (e.g., 3.0V), assuming that the positive threshold voltage of the determining module 22 is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the conventional power supply good output subunit shown in fig. 3 is as shown in fig. 5, and specifically includes the following stages:

stage 0-t 1: the enable signal EN is at a low level, that is, the enable switch 24 of the voltage divider module 21 is turned off at this time, that is, one end of the resistor string for detection is turned off from the positive power voltage end, while the other end is always coupled to the ground terminal, the detected divided voltage VDDN' is equal to the ground voltage (0V), the FLAG signal FLAG output after being determined by the schmitt inverter 25 of the determination module 22 is at a high level, and the logic and gate 23 outputs the power good signal VDDN _ power low after the enable signal EN is anded with the FLAG signal FLAG.

Stage t1-t 3: the enable signal EN is at a high level, that is, the enable switch 24 of the voltage dividing module 21 is closed, the input power voltage VDDN is at a start-up rising stage, but has not yet reached an ideal voltage state, so the detected divided voltage VDDN' converted by the voltage dividing module 21 has not yet reached a preset threshold range of the schmitt inverter 25, and ideally, the FLAG signal FLAG output after being judged by the schmitt inverter 25 should be at a low level, but due to a non-ideal characteristic of comparison by the schmitt inverter 25, there is a certain comparison delay time td, that is, the high-level FLAG signal output at time t1 will form a certain delay in the time period td, and the FLAG signal will not turn to a low level until time t2= t1+ td. Therefore, the FLAG signal output in the stage t1-t2 is at a high level, and after the enable signal EN is anded with the FLAG signal FLAG by the logic and gate 23, the output power good signal VDDN _ power good is at a high level, but at this time, the power does not really meet the good output state, so that the subsequent protection circuit is subjected to misoperation, and adverse effects are brought; the FLAG signal output during the period t2-t3 is low, and the logic and gate 23 outputs the power good signal VDDN _ power low after the enable signal EN is anded with the FLAG signal FLAG.

Stage t3-t 4: the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN' converted by the voltage dividing module 21 reaches and maintains a preset threshold range of the determining module 22, the FLAG signal FLAG output by the determining module 22 is a high level, the logic and gate 23 and the enable signal EN and the FLAG signal FLAG are anded, and then the output power supply good signal VDDN _ power is a high level, at this time, the power supply voltage really meets a good output state.

Based on the same principle, the signal response output process of the conventional power good output subunit shown in fig. 4 is also similar to that of the above embodiment, and is not described herein again.

Therefore, due to the problems of competition and risk caused by different delays of the enable switch and the judgment module, a burr phenomenon (at the stage t1-t 2) occurs in actual response output, the judgment accuracy of a good state of a power supply is influenced, the subsequent protection circuit is subjected to misoperation, and the overall performance of the display driving chip is further influenced.

Disclosure of Invention

The invention aims to provide a power good signal output method and a power good signal output device, which can improve the judgment accuracy of a power good state and improve the overall performance of a display driving chip.

Based on the above consideration, the invention provides a power good signal output method, which comprises the following steps:

converting input power supply voltage into detection divided voltage for judgment through a voltage dividing module with an enabling switch, wherein the enabling switch responds to an enabling signal, and the power supply voltage is a positive value or a negative value;

judging the detected partial pressure through a forward judgment module or a reverse judgment module, and outputting a mark signal;

and processing the enabling signal and the marking signal through a trigger, and outputting a power good signal.

Preferably, the forward judgment module comprises a hysteresis comparator or an even number of inverters connected in series, and the inverters comprise at least one schmitt inverter connected close to the output end of the voltage division module.

Preferably, the reverse judgment module comprises a hysteresis comparator or a single schmitt inverter or an odd number of inverters connected in series, and the inverters comprise at least one schmitt inverter connected close to the output end of the voltage division module.

Preferably, the schmitt inverter is powered by a built-in power supply.

According to an embodiment of the present invention, when the power voltage is a positive value, the enable switch is connected to a ground terminal in the voltage dividing module, and the positive determining module determines the detected divided voltage, wherein the signal response output process includes the following steps:

stage 0-T1: enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at high level, and marking the signal to be at low level;

stages T1-T2: enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at a low level;

stages T2-T3: enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;

stages T3-T4: enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;

post-stage T4: the enable signal is at low level, the detected divided voltage is equal to the power supply voltage, the flag signal is at high level, and the power good signal is at low level.

According to another specific embodiment of the present invention, when the power voltage is a positive value, the enable switch is connected to a power voltage end of the voltage dividing module, and the positive determination module determines the detected divided voltage, wherein the signal response output process includes the following steps:

wherein, the signal response output process comprises the following stages:

stage 0-T1': enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at the low level, and marking the signal to be at the low level;

stage T1 '-T2': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;

stage T2 '-T3': enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;

stage T3 '-T4': enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at a high level, and marking the signal to be at a low level;

post stage T4': the enable signal is at low level, the detection divided voltage is equal to the ground voltage, the flag signal is at low level, and the power good signal is at low level.

According to another specific embodiment of the present invention, when the power voltage is a positive value, the enable switch is connected to a power voltage end of the voltage dividing module, and the detected divided voltage is determined by the reverse determination module, wherein the signal response output process includes the following steps:

stage 0-T1': enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at a high level, and marking the signal to be at a low level;

stages T1 '' -T2 '': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at a low level;

stages T2 '' -T3 '': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;

stages T3 '' -T4 '': enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;

post-stage T4 ″: the enable signal is at low level, the detection divided voltage is equal to the ground voltage, the flag signal is at high level, and the power good signal is at low level.

According to another specific embodiment of the present invention, when the power voltage is a positive value, the enable switch is connected to a ground terminal in the voltage dividing module, and the detected divided voltage is determined by the reverse determination module, wherein the signal response output process includes the following steps:

stage 0-T1 ' ' ': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at low level, and marking the signal to be at low level;

stage T1 '' '-T2' '': enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;

stage T2 '' '-T3' '': enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;

stage T3 '' '-T4' '': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at high level, and marking the signal to be at low level;

t4 ' ' ' post stage: the enable signal is at low level, the detected divided voltage is equal to the power supply voltage, the flag signal is at low level, and the power good signal is at low level.

Another aspect of the present invention provides a power good signal output apparatus, including:

the voltage division module is provided with an enabling switch and is used for converting input power supply voltage into detection divided voltage for judgment, the enabling switch responds to an enabling signal, and the power supply voltage is a positive value or a negative value;

the forward judgment module or the reverse judgment module is used for judging the detection partial pressure and outputting a mark signal;

and the trigger is used for processing the enabling signal and the marking signal and outputting a power good signal.

Preferably, the schmitt inverter is powered by a built-in power supply.

Preferably, the enable switch is connected to a power supply voltage end of the voltage division module.

Preferably, the enable switch is connected to a ground terminal near the voltage dividing module.

According to the power good signal output method and device, the trigger is adopted to process the enable signal and the mark signal so as to output the power good signal, so that zero-power-consumption quiescent current can be realized in a deep sleep or shutdown mode, the problems of competition and risk caused by different delays of the enable switch and the judgment module can be solved, the burr phenomenon in actual response output is eliminated, the judgment accuracy of the power good state is improved, and the overall performance of the display driving chip is improved.

Drawings

Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.

FIG. 1 is a diagram of a power detection circuit of a conventional display driver chip;

FIG. 2 is a block diagram of a conventional power supply and output subunit;

fig. 3 and 4 are circuit diagrams of a conventional power supply good output subunit;

FIG. 5 is a diagram illustrating the effect of a conventional power supply with a good output subunit;

FIG. 6 is a block diagram of a power good output subunit of the present invention;

FIG. 7(A) is a circuit diagram of a power supply sub-unit according to a first embodiment of the present invention;

FIG. 7(B) is a diagram illustrating the effect of the power supply sub-unit according to the first embodiment of the present invention;

FIG. 8(A) is a circuit diagram of a power supply sub-unit according to a second embodiment of the present invention;

FIG. 8(B) is a diagram illustrating the effect of the power supply sub-unit according to the second embodiment of the present invention;

FIG. 9(A) is a circuit diagram of a power supply output sub-unit according to a third embodiment of the present invention;

FIG. 9(B) is a diagram illustrating the effect of the power supply sub-unit according to the third embodiment of the present invention;

FIG. 10(A) is a circuit diagram of a power supply sub-unit according to a fourth embodiment of the present invention;

fig. 10(B) is an effect diagram of the power supply good output subunit according to the fourth embodiment of the present invention.

In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.

Detailed Description

In order to solve the problems in the prior art, the invention provides a power good signal output method and a device, wherein the trigger is adopted to process the enable signal and the mark signal so as to output the power good signal, so that the zero-power quiescent current can be realized in a deep sleep or shutdown mode, the problems of competition and risk caused by different delays of the enable switch and the judgment module can be solved, the burr phenomenon in actual response output is eliminated, the judgment accuracy of the power good state is improved, and the overall performance of the display driving chip is improved.

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Fig. 6 shows a block diagram of a power good output subunit of the present invention. Fig. 7-10 show the circuit diagram and effect diagram of four preferred embodiments of the present invention, respectively. As shown in fig. 6, the power good signal output device 120 of the present invention includes a voltage dividing module 121 with an enable switch, a determining module 122 and a trigger 123.

The voltage divider 121 converts the power voltage VDDN input by the multi-output power management unit 110 into a detectable divided voltage VDDN' through resistive voltage division. Because the voltage division module 121 is provided with the enable switch responding to the enable signal EN, the static power consumption of the voltage division resistor string can be zero under the deep sleep or shutdown mode through the control of the enable signal EN. The enabling switch has two connections, one is close to the ground terminal (GND terminal), as shown in embodiment I (FIG. 7) and embodiment IV (FIG. 10); the other is close to the power supply voltage terminal (VDDN terminal), as shown in embodiment two (FIG. 8) and embodiment three (FIG. 9).

The determining module 122 is configured to determine to detect the divided voltage VDDN' and output a FLAG signal FLAG. The judging module has two types, one is a forward judging module, as shown in the first embodiment (fig. 7) and the second embodiment (fig. 8), in addition to the two schmitt inverters connected in series as shown in the above embodiments, an even number of inverters connected in series can be adopted, and the inverters include at least one schmitt inverter connected to the output end close to the voltage dividing module to increase the driving capability, or a hysteresis comparator is directly adopted; another is a reverse judging module, as shown in the third embodiment (fig. 9) and the fourth embodiment (fig. 10), in addition to the single schmitt inverter shown in the above embodiments, an odd number of inverters connected in series may be used, where the inverter includes at least one schmitt inverter connected near the output end of the voltage dividing module to increase the driving capability, or a hysteresis comparator is directly used.

The flip-flop (e.g., D flip-flop, DFF) 123 uses the enable signal EN as an input signal and a reset signal, uses the FLAG signal FLAG as a clock signal, and uses edge triggering to detect the input signal and assign it to the output signal when the clock signal is a rising edge, thereby obtaining the VDDN _ powered signal. Because the characteristic of the flip-flop is edge triggering, only when the FLAG signal FLAG is turned over at the rising edge, the response is output, and the influence of the delay of the FLAG signal caused by the non-ideal characteristic of the comparison of the judging module in the stage t1-t2 in the prior art is completely avoided, so that the problems of competition and risk caused by different delays of the enabling switch and the judging module can be solved, and the specific reference is made to the following embodiments.

Example one

Fig. 7(a) shows a circuit diagram of the power good signal output subunit according to the first embodiment of the present invention, and fig. 7(B) shows an effect diagram of the power good signal output subunit according to the first embodiment of the present invention.

As shown in fig. 7(a), the power good signal output subunit of the present invention includes a voltage division module 221 with an enable switch 224, a forward direction determination module 222, and a flip-flop 223, wherein the enable switch 224 is close to a ground terminal (GND terminal).

The voltage divider 221 converts the input power voltage VDDN into a detection divided voltage VDDN' for determination through resistive voltage division. Because the voltage dividing module 221 is provided with the enable switch 224 responding to the enable signal EN, the static power consumption of the voltage dividing resistor string can be zero in the deep sleep or shutdown mode through the control of the enable signal EN.

The forward determination module 222 is configured to determine the detected divided voltage VDDN' and output a FLAG signal FLAG. Instead of two schmitt inverters 225 connected in series as shown in this embodiment, an even number of schmitt inverters may be used, and the number of the inverters may include at least one schmitt inverter 225 connected near the output end of the voltage dividing module to increase the driving capability, or a hysteresis comparator may be directly used.

The flip-flop 223 uses the enable signal EN as an input signal and a reset signal, uses the FLAG signal FLAG as a clock signal, adopts edge triggering, detects the input signal and assigns it to an output signal when the clock signal is a rising edge, thereby obtaining a VDDN _ powered signal.

Taking the power voltage VDDN input by the multi-output power management unit as a positive value (e.g., 3.0V), assuming that the positive threshold voltage of the determination module is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the power good output subunit of the embodiment is as shown in fig. 7(B), and specifically includes the following stages:

stage 0-T1: the enable signal EN is at a low level, that is, the enable switch 224 of the voltage divider module 221 is turned off at this time, that is, one end of the resistor string for detection is turned off from the ground terminal, while the other end is always coupled to the positive power voltage output, the detected divided voltage VDDN' is equal to the power voltage VDDN (3V), the FLAG signal FLAG output after the determination by the forward determination module 222 is at a high level, the flip-flop 223 is not triggered, and the output power good signal VDDN _ power good is at a low level.

Stages T1-T3: the enable signal EN is at a high level, that is, the enable switch 224 of the voltage dividing module 221 is closed, the input power voltage VDDN is at a start-up stage, but has not yet reached an ideal voltage state, so the detected divided voltage VDDN' converted by the voltage dividing module 221 has not yet reached the preset threshold range of the forward determination module 222, and ideally, the FLAG signal FLAG output after being determined by the forward determination module 222 should be at a low level, but due to the non-ideal characteristic of comparison by the forward determination module 222, there is a certain comparison delay time td, that is, the high-level FLAG signal output at the time T1 will form a certain delay in the time period td, and the FLAG signal will not flip to a low level until the time T2= T1+ td. Therefore, the FLAG signal output in the stage T1-T2 is at a high level, the FLAG signal output in the stage T2-T3 is at a low level, and the trigger is characterized in edge triggering, and only when the FLAG signal FLAG flips at a rising edge, the trigger outputs a response, so that the trigger is completely free from the influence of the delay of the FLAG signal in the stage T1-T2 due to the non-ideal characteristic compared by the judgment module, and the power good signal VDDN _ powered good output in the whole stage T1-T3 is at a low level.

Stages T3-T4: the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN' converted by the voltage dividing module 221 reaches and maintains a preset threshold range of the forward determination module 222, the FLAG signal FLAG output by the forward determination module 222 is inverted to a high level at time T3, the flip-flop is triggered, the enable signal EN is assigned to the output power good signal VDDN _ power, and the output power good signal VDDN _ power is a high level.

Post-stage T4: the enable signal EN is at a low level, that is, the enable switch 224 of the voltage divider module 221 is turned off, and it is detected that the divided voltage VDDN' is equal to the power supply voltage VDDN (3V) again, in an ideal case, the FLAG signal FLAG output after being judged by the forward judgment module 222 should be at a high level, although a certain comparison delay time td exists due to the non-ideal characteristic compared by the forward judgment module 222, since the logic state of the FLAG signal output at time T4 is also at a high level, the FLAG signal output at the later stage of T4 is not affected, the FLAG signal output at the later stage of the whole T4 is at a high level, the flip-flop continues to assign the enable signal EN to the output power good signal VDDN _ power, and the output power good signal VDDN _ power is at a low level, which indicates that the power supply voltage VDDN is no longer in a good output state, that is the power-off state.

Example two

Fig. 8(a) shows a circuit diagram of the power good signal output subunit according to the second embodiment of the present invention, and fig. 8(B) shows an effect diagram of the power good signal output subunit according to the second embodiment of the present invention.

As shown in fig. 8(a), the power good signal output subunit of the present invention includes a voltage dividing module 321 with an enable switch 324, a forward direction determining module 322, and a flip-flop 323, wherein the enable switch 324 is close to the power voltage terminal (VDDN terminal).

The voltage dividing module 321 converts the input power voltage VDDN into a detection divided voltage VDDN' for determination through resistance voltage division. Because the voltage dividing module 321 is provided with the enable switch 324 responding to the enable signal EN, the static power consumption of the voltage dividing resistor string can be zero in the deep sleep or shutdown mode through the control of the enable signal EN.

The forward determination module 322 is used for determining the detected divided voltage VDDN' and outputting a FLAG signal FLAG. Instead of two schmitt inverters 325 connected in series as shown in this embodiment, an even number of schmitt inverters connected in series may be used, and the number of the inverters includes at least one schmitt inverter 325 connected near the output end of the voltage dividing module to increase the driving capability, or a hysteresis comparator may be directly used.

The flip-flop 323 uses the enable signal EN as an input signal and a reset signal, uses the FLAG signal FLAG as a clock signal, adopts edge triggering, detects the input signal and assigns it to an output signal when the clock signal is a rising edge, thereby obtaining a VDDN _ powered signal. .

Taking the power voltage VDDN input by the multi-output power management unit as a positive value (e.g., 3.0V), assuming that the positive threshold voltage of the determination module is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the power good output subunit of the embodiment is as shown in fig. 8(B), and specifically includes the following stages:

stage 0-T1': the enable signal EN is at a low level, that is, the enable switch 324 of the voltage divider module 321 is turned off at this time, that is, one end of the resistor string for detection is turned off from the positive power voltage end, while the other end is always coupled to the ground terminal, the detected divided voltage VDDN' is equal to the ground voltage (0V), the FLAG signal FLAG output after the determination by the forward determination module 322 is at a low level, the trigger 323 is not triggered, and the output power good signal VDDN _ power good is at a low level.

Stage T1 '-T2': the enable signal EN is at a high level, that is, the enable switch 324 of the voltage dividing module 321 is closed, the input power supply voltage VDDN is at a start-up stage, but has not yet reached an ideal voltage state, so the detected divided voltage VDDN 'converted by the voltage dividing module 321 has not yet reached the preset threshold range of the forward determination module 322, and in an ideal case, the FLAG signal FLAG output after being determined by the forward determination module 322 should be at a low level, although there is a certain comparison delay time td due to the non-ideal characteristic compared by the forward determination module 322, since the logic state of the FLAG signal output at the time T1' is also at a low level, the FLAG signal output at the stage T1 '-T2' is not affected, and the FLAG signal output at the whole stage T1 '-T2' is at a low level, the trigger 323 is not triggered, and the output power supply good signal VDDN _ poll is at a low level.

Stage T2 '-T3': the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN 'converted by the voltage dividing module 321 reaches and maintains a preset threshold range of the forward determination module 322, the FLAG signal FLAG output by the forward determination module 322 is inverted to a high level at time T2', the flip-flop is triggered, the enable signal EN is assigned to the output power good signal VDDN _ power, and the output power good signal VDDN _ power is a high level.

Post stage T3': the enable signal EN is at a low level, that is, the enable switch 324 of the voltage dividing module 321 is turned off, and the divided voltage VDDN 'is detected to be equal to the ground voltage (0V) again, in an ideal case, the FLAG signal FLAG output after being judged by the forward judging module 322 should be at a low level, but due to the non-ideal characteristic compared by the forward judging module 322, a certain comparison delay time td exists, that is, the high level FLAG signal output at the time T3' will form a certain delay in a time period td until the FLAG signal output at the time T4 '= T3+ td flips to be at a low level, in the whole stage after T3', the flip-flop 323 continues to assign the enable signal EN to the output power good signal VDDN _ power, and the output good signal VDDN is at a low level, which indicates that the power voltage VDDN is no longer in a good output state, that is the power-off state.

EXAMPLE III

Fig. 9(a) shows a circuit diagram of the power good signal output subunit according to the third embodiment of the present invention, and fig. 9(B) shows an effect diagram of the power good signal output subunit according to the third embodiment of the present invention.

As shown in fig. 9(a), the power good signal output subunit of the present invention includes a voltage dividing module 421 with an enable switch 424, a reverse direction determining module 422, and a flip-flop 423, wherein the enable switch 424 is close to the power voltage terminal (VDDN terminal).

The voltage dividing module 421 converts the input power voltage VDDN into a detection divided voltage VDDN' for determination through resistance voltage division. Because the voltage dividing module 421 is provided with the enable switch 424 responding to the enable signal EN, the static power consumption of the voltage dividing resistor string can be zero in the deep sleep or shutdown mode through the control of the enable signal EN.

The reverse determination module 422 is configured to determine the detected divided voltage VDDN' and output a FLAG signal FLAG. Instead of the single schmitt inverter 425 shown in this embodiment, an odd number of inverters connected in series may be used, including at least one schmitt inverter 425 connected near the output of the voltage divider block to increase the driving capability, or a hysteresis comparator may be used directly.

The flip-flop 423 uses the enable signal EN as an input signal and a reset signal, uses the FLAG signal FLAG as a clock signal, adopts edge triggering, detects the input signal and assigns it to the output signal when the clock signal is a rising edge, thereby obtaining a VDDN _ powered signal.

Taking the power voltage VDDN input by the multi-output power management unit as a positive value (e.g., 3.0V), assuming that the positive threshold voltage of the determination module is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the power good output subunit of this embodiment is as shown in fig. 9(B), and specifically includes the following stages:

stage 0-T1': the enable signal EN is at a low level, that is, the enable switch 424 of the voltage divider module 421 is turned off at this time, that is, one end of the resistor string for detection is turned off from the positive power voltage end, while the other end is always coupled to the ground terminal, the detected divided voltage VDDN' is equal to the ground voltage (0V), the FLAG signal FLAG output after the judgment of the reverse judgment module 422 is at a high level, the flip-flop 423 is not triggered, and the output power good signal VDDN _ power good is at a low level.

Stages T1 '' -T3 '': the enable signal EN is at a high level, that is, the enable switch 424 of the voltage dividing module 421 is closed, the input power voltage VDDN is at a start-up stage, but has not yet reached an ideal voltage state, so the detected divided voltage VDDN' converted by the voltage dividing module 421 has not yet reached the preset threshold range of the inversion determination module 422, and ideally, the FLAG signal FLAG output after the judgment by the inversion determination module 422 should be at a low level, but due to the non-ideal characteristic compared by the inversion determination module 422, there is a certain comparison delay time td, that is, the high-level FLAG signal output at the time T1 ″ will form a certain delay in the time period td, and the FLAG signal will not flip to a low level until the time T2= T1 ″ + td. Therefore, the FLAG signal output from the stages T1 "-T2" is high, the FLAG signal output from the stages T2 "-T3" is low, and since the flip-flop is characterized by edge triggering, the response is output only when the FLAG signal FLAG flips at the rising edge, which is completely unaffected by the delay of the FLAG signal caused by the non-ideal characteristics of the comparison of the determination modules in the stages T1 "-T2", and the good power signal VDDN _ power output from the entire stages T1 "-T3" is low.

Stages T3 '' -T4 '': the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN' converted by the voltage dividing module 421 reaches and maintains a preset threshold range of the inversion determination module 422, the FLAG signal FLAG output by the inversion determination module 422 is inverted to a high level at time T3 ″, the flip-flop is triggered, the enable signal EN is assigned to the output power good signal VDDN _ power good, and the output power good signal VDDN _ power good is a high level.

Post-stage T4 ″: the enable signal EN is at a low level, that is, the enable switch 424 of the voltage dividing module 421 is turned off, the detected divided voltage VDDN' is equal to the ground voltage (0V) again, and ideally, the FLAG signal FLAG output after being determined by the inversion determining module 422 should be at a high level, although a certain comparison delay time td exists due to the non-ideal characteristic compared by the inversion determining module 422, since the logic state of the FLAG signal output at the time T4 ″ is also at a high level, the FLAG signal output at the later stage of T4 ″ is not affected, the FLAG signal output at the later stage of T4 ″ is at a high level, the flip-flop continues to assign the enable signal EN to the output power good signal VDDN _ powered good, and the output power good signal VDDN _ powered good is at a low level, which indicates that the power voltage VDDN is no longer at a good output state, that is the shutdown state.

Example four

Fig. 10(a) shows a circuit diagram of the power good signal output subunit according to the fourth embodiment of the present invention, and fig. 10(B) shows an effect diagram of the power good signal output subunit according to the fourth embodiment of the present invention.

As shown in fig. 10(a), the power good signal output subunit of the present invention includes a voltage division module 521 with an enable switch 524, a reverse determination module 522, and a flip-flop 523, wherein the enable switch 524 is close to a ground terminal (GND terminal).

The voltage divider 521 converts the input power voltage VDDN into a detection divided voltage VDDN' for determination through resistance voltage division. Due to the fact that the enable switch 524 responding to the enable signal EN is arranged in the voltage dividing module 521, the static power consumption of the voltage dividing resistor string can be zero in the deep sleep or shutdown mode through control of the enable signal EN.

The reverse determination module 522 is configured to determine the detected divided voltage VDDN' and output a FLAG signal FLAG. Instead of the single schmitt inverter 525 shown in this embodiment, an odd number of inverters connected in series may be used, including at least one schmitt inverter 525 connected near the output of the voltage dividing module to increase the driving capability, or a hysteresis comparator may be directly used.

The flip-flop 523 uses the enable signal EN as an input signal and a reset signal, uses the FLAG signal FLAG as a clock signal, adopts edge triggering, detects the input signal and assigns it to an output signal when the clock signal is a rising edge, thereby obtaining a VDDN _ powered signal.

Taking the power voltage VDDN input by the multi-output power management unit as a positive value (e.g., 3.0V), assuming that the positive threshold voltage of the determination module is 1.6V and the negative threshold voltage is 0.8V, the signal response output process of the power good output subunit of the embodiment is as shown in fig. 10(B), and specifically includes the following stages:

stage 0-T1': the enable signal EN is at a low level, that is, the enable switch 524 of the voltage divider module 521 is turned off at this time, that is, the level of one end of the resistor string for detection is disconnected from the ground terminal, while the other end is always coupled to the positive power voltage output, the detected divided voltage VDDN' is equal to the power voltage VDDN (3V), the FLAG signal FLAG output after the determination by the reverse determination module 522 is at a low level, the flip-flop 523 is not triggered, and the power good signal VDDN _ power good is at a low level.

Stage T1 '' '-T2' '': the enable signal EN is high, i.e. the enable switch 524 of the voltage divider 521 is closed, the input power voltage VDDN is in the startup rising phase, however, the ideal voltage state is not reached yet, and therefore, the detected divided voltage VDDN' converted by the voltage dividing module 521 does not reach the preset threshold range of the reverse judging module 522, the FLAG signal FLAG output after being judged by the reverse judging module 522 should be at a low level in an ideal case, although there is a certain comparison delay time td due to the non-ideal characteristic compared by the reverse judging module 522, however, since the logic state of the FLAG signal output at time T1 ' ″ is also low, the FLAG signal output at the stage T1 ' ″ -T2 ' ″ is not affected, the FLAG signal output at the stage T1 ' ″ -T2 ' ″ is all low, the flip-flop 523 is not triggered, and the power good signal VDDN _ power good is output low.

Stage T2 '' '-T3' '': the enable signal EN continues to maintain a high level, and the power supply voltage VDDN reaches and maintains an ideal voltage state, so that the detected divided voltage VDDN 'converted by the voltage dividing module 521 reaches and maintains a preset threshold range of the inversion determination module 522, the FLAG signal FLAG output by the inversion determination module 522 is inverted to a high level at time T2' ″, the flip-flop is triggered, the enable signal EN is assigned to the output power good signal VDDN _ power good, and the output power good signal VDDN _ power good is a high level.

T3 ' ' ' post stage: the enable signal EN is at a low level, that is, the enable switch 524 of the voltage dividing module 521 is turned off, and it is detected that the divided voltage VDDN 'is equal to the power voltage (3V) again, in an ideal case, the FLAG signal FLAG output after being determined by the reverse determination module 522 should be at a low level, but due to the non-ideal characteristic compared by the reverse determination module 522, there is a certain comparison delay time td, that is, the high level FLAG signal output at time T3' ″ forms a certain delay in a time period td until the FLAG signal output at time T4 '= T3' + td turns to a low level, and in the whole period after T3 '″, the flip-flop' 523 continues to assign the enable signal EN to the output power good signal VDDN _ power, and outputs the power good signal n _ power vddvddn at a low level, which indicates that the power voltage VDDN is no longer in a good output state, that is the power-off state.

It can be understood by those skilled in the art that the method and apparatus for outputting a power supply signal of the present invention are also applicable to the case where the input power supply voltage VDDN is negative, and the signal response output process is similar to the above embodiments and will not be described herein again.

The invention processes the enable signal and the mark signal by adopting the trigger to output the good signal of the power supply, not only can realize zero-power consumption quiescent current under a deep sleep or shutdown mode, but also can solve the problems of competition and risk caused by different delays of the enable switch and the judgment module, eliminate the burr phenomenon in actual response output, improve the judgment accuracy of the good state of the power supply and improve the overall performance of the display driving chip.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims

1. A power good signal output method is characterized by comprising the following steps:

processing the enabling signal and the marking signal through a trigger, and outputting a power good signal;

when power supply voltage is a positive value, the enabling switch is connected to a ground wire end close to the voltage dividing module, the detection voltage division is judged through the forward judging module, and the signal response output process comprises the following stages:

2. The method of claim 1, wherein the forward decision module comprises a hysteresis comparator or an even number of inverters connected in series, the inverters comprising at least one schmitt inverter connected near an output of the voltage divider module.

3. The method of claim 1, wherein the reverse direction decision module comprises a hysteresis comparator or an odd number of inverters connected in series, the inverters comprising at least one schmitt inverter connected near an output of the voltage divider module.

4. The method of claim 2 or 3, wherein the Schmitt inverter is powered by an internal power source.

5. A power good signal output method is characterized by comprising the following steps:

when power supply voltage is a positive value, the enabling switch is connected to a power supply voltage end close to the voltage dividing module, the voltage division is detected through judgment of the forward judgment module, and the signal response output process comprises the following stages:

6. A power good signal output method is characterized by comprising the following steps:

processing the enabling signal and the marking signal through a trigger, and outputting a power good signal; when the power supply voltage is a positive value, the enabling switch is connected to a power supply voltage end close to the voltage dividing module, the voltage division is detected through judgment of the reverse judging module, and the signal response output process comprises the following stages:

stage 0-T1 ": enabling the signal to be at a low level, detecting that the divided voltage is equal to the ground wire voltage, marking the signal to be at a high level, and marking the signal to be at a low level;

stage T1 "-T2": enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at a low level;

stage T2 "-T3": enabling the signal to be at a high level, detecting that the partial voltage does not reach a preset threshold range, marking the signal to be at a low level, and marking the signal with a good power supply to be at a low level;

stage T3 "-T4": enabling the signal to be at a high level, detecting that the partial voltage reaches a preset threshold range, marking the signal to be at the high level, and marking the signal with a good power supply to be at the high level;

t4 "post stage: the enable signal is at low level, the detection divided voltage is equal to the ground voltage, the flag signal is at high level, and the power good signal is at low level.

7. A power good signal output method is characterized by comprising the following steps:

when the power supply voltage is a positive value, the enabling switch is connected to a ground wire end close to the voltage dividing module, the detection voltage division is judged through the reverse judging module, and the signal response output process comprises the following stages:

stage 0-T1' ″: enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at low level, and marking the signal to be at low level;

stage T3 '-T4': enabling the signal to be at low level, detecting that the divided voltage is equal to the power supply voltage, marking the signal to be at high level, and marking the signal to be at low level;

t4 "' post stage: the enable signal is at low level, the detected divided voltage is equal to the power supply voltage, the flag signal is at low level, and the power good signal is at low level.

8. A power good signal output apparatus, comprising:

the trigger is used for processing the enabling signal and the marking signal and outputting a power good signal;

9. The device as claimed in claim 8, wherein the positive direction decision module comprises a hysteresis comparator or an even number of inverters connected in series, the inverters comprising at least one schmitt inverter connected near the output terminal of the voltage division module.

10. The apparatus of claim 8, wherein the inversion decision module comprises a hysteresis comparator or an odd number of inverters connected in series, the inverters comprising at least one schmitt inverter connected near an output of the voltage divider module.

11. The powered good signal output device of claim 9 or 10, wherein the schmitt inverter is powered by an internal power source.

12. A power good signal output apparatus, comprising: