CN110992866A - Drive circuit of display panel and logic circuit of electronic device - Google Patents
Drive circuit of display panel and logic circuit of electronic device Download PDFInfo
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- CN110992866A CN110992866A CN201911261127.8A CN201911261127A CN110992866A CN 110992866 A CN110992866 A CN 110992866A CN 201911261127 A CN201911261127 A CN 201911261127A CN 110992866 A CN110992866 A CN 110992866A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention discloses a drive circuit of a display panel and a logic circuit of an electronic device, wherein the drive circuit comprises a power failure detection circuit and a power management chip connected with the power failure detection circuit, and the power failure detection circuit comprises: the energy storage device comprises a first triode, a second triode and an energy storage unit, wherein the first triode is a PNP type triode, and the second triode is an NPN type triode; the base of the first triode is used for being connected with the input voltage of the power management chip, the emitting electrode of the first triode is connected with the input voltage of the power management chip through the energy storage unit, the collecting electrode of the first triode is connected with the base of the second triode, the emitting electrode of the second triode is grounded, the collecting electrode of the second triode is used for being connected with the reference voltage of the power management chip, and the energy storage unit is used for discharging when the input voltage drops to 0V. By the power failure detection circuit, the error change of the register by interference voltage can be avoided, and the normal starting state of the power management chip next time is ensured.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a driving circuit of a display panel and a logic circuit of an electronic device.
Background
At present, a driving circuit of a display panel usually includes a power management chip, wherein a reference voltage exists inside the power management chip (PMIC) to provide a stable reference voltage for a circuit in the power management chip, so that the reference voltage requires high precision, good stability and small temperature drift to ensure normal startup of the power management chip. The reference voltage is generated by the input voltage of the power management chip, when the power is off and the power is off, the input voltage is also off, the power management chip detects that the reference voltage is off to a set value, for example, the register is reset after the reference voltage drops from 5V to 2V, so that the condition that the register is mistakenly changed by interference voltage when the power is off and the next power on state of the power management chip is influenced is avoided. On the contrary, when the input voltage is powered down, if the reference voltage of the power management chip cannot be powered down to the set value for some reasons, the power management chip cannot reset the register, and even the interference voltage may change the register by mistake, which finally causes the power management chip to be in an abnormal state when the power management chip is started up next time.
Disclosure of Invention
Based on the above, the invention provides a driving circuit and a logic circuit, which can enable the reference voltage to be powered down to a set value when the input voltage is powered down so as to reset the register of the power management chip, can avoid the interference voltage from changing the register by mistake, and can ensure the normal state of the power management chip when the power management chip is started next time.
The utility model provides a display panel's drive circuit, its characterized in that, drive circuit including power down detection circuitry, with the power management chip that power down detection circuitry is connected, power down detection circuitry includes: the energy storage device comprises a first triode, a second triode and an energy storage unit, wherein the first triode is a PNP type triode, and the second triode is an NPN type triode;
the base of the first triode is used for being connected with the input voltage of the power management chip, the emitting electrode of the first triode is connected with the input voltage of the power management chip through the energy storage unit, the collecting electrode of the first triode is connected with the base of the second triode, the emitting electrode of the second triode is grounded, the collecting electrode of the second triode is used for being connected with the reference voltage of the power management chip, and the energy storage unit is used for discharging when the input voltage is reduced to 0V so as to conduct the first triode.
According to the power failure detection circuit, when the input voltage of the power management chip is reduced to 0V, the energy storage unit discharges, the first triode is conducted, the second triode is conducted, the reference voltage of the power management chip is pulled to the ground by the conducted second triode, the reference voltage can be powered down to a set value, and therefore the power failure detection circuit can ensure that the reference voltage is powered down to the set value when the input voltage is powered down, the register of the power management chip is reset, the phenomenon that the register is mistakenly changed by interference voltage can be avoided, and the power management chip can be ensured to be in a normal state when the power management chip is started next time.
A logic circuit of an electronic device comprises a logic board, a clock line, a data line, a signal board for providing a clock signal and a data signal, two pull-up resistors and a power failure detection circuit, wherein the logic board comprises a power management chip and a time schedule controller, the signal board is connected with the power management chip through the clock line and the data line respectively, the power management chip is also connected with the time schedule controller, the signal board transmits the clock signal and the data signal to the power management chip from the clock line and the data line respectively, the clock signal and the data signal are relayed to the time schedule controller by the power management chip, one of the two pull-up resistors clamps the clock signal transmitted by the clock line to a high level, and the other pull-up resistor clamps the data signal transmitted by the data line to the high level; the power failure detection circuit comprises a first triode, a second triode and an energy storage unit, wherein the first triode is a PNP type triode, and the second triode is an NPN type triode; the base of the first triode is connected with the input voltage of the power management chip, the emitter of the first triode is connected with the input voltage of the power management chip through the energy storage unit, the collector of the first triode is connected with the base of the second triode, the emitter of the second triode is grounded, the collector of the second triode is connected with the reference voltage of the power management chip, and the energy storage unit is used for discharging when the input voltage is reduced to 0V so as to conduct the first triode.
In the logic circuit, if the power management chip is powered off, the signal board is not powered off due to the reason of entering a standby mode and the like, the clamped high level on the clock line and the signal line can be used as a pull-up voltage to be injected into the power management chip, so that the reference voltage of the power management chip cannot be powered off to a set value, the power management chip cannot reset the register, even interference voltage can be mistakenly changed into the register, and finally the risk of voltage abnormity exists when the power management chip is started next time, but the power failure detection circuit can detect the input voltage and the reference voltage of the power management chip, when the input voltage of the power management chip is reduced to 0V, the energy storage unit discharges to enable the first triode to be conducted, further enable the second triode to be conducted, and the reference voltage of the power management chip is pulled to the ground so that the reference voltage can be powered off to the set value, therefore, the power failure detection circuit can ensure that the reference voltage is also powered down to a set value when the condition occurs so as to reset the register of the power management chip, avoid the interference voltage from changing the register by mistake and ensure that the power management chip is in a normal state when being started next time.
Drawings
FIG. 1 is a schematic diagram of the connection between a system-on-chip and a logic board according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a normal reset of a register of a power management chip according to an embodiment of the invention;
FIG. 3 is a flow chart illustrating how a register of a power management chip cannot be reset according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a power down detection circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a power down detection circuit according to another embodiment of the present invention;
FIG. 6 is a schematic flow chart of a reset register of the power down detection circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a logic circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. The following embodiments and their technical features may be combined with each other without conflict. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As described in the background art, a reference voltage exists inside the power management chip to provide a stable reference voltage for the circuits in the power management chip, so that the reference voltage has high precision, good stability and small temperature drift to ensure the normal startup of the power management chip. The reference voltage is generated by the input voltage of the power management chip, when the power is off and the power is off, the input voltage is also off, the power management chip detects that the reference voltage is off to a set value, for example, the register is reset after the reference voltage drops from 5V to 2V, so that the condition that the register is mistakenly changed by interference voltage when the power is off and the next power on state of the power management chip is influenced is avoided. On the contrary, if the reference voltage of the power management chip cannot be powered down to the set value for some reasons, the power management chip cannot reset the register, and even the interference voltage may change the register by mistake, which finally causes the power management chip to be in an abnormal state when the power management chip is started up next time.
For example, as shown in fig. 1, a System On Chip (SOC) 21 provides a clock signal and a data signal, and transmits the clock signal and the data signal to a timing controller 12 (TCON) through a power management Chip 11, the power management Chip includes a voltage regulator, a capacitor, an I2C (Inter Integrated Circuit) interface, a digital-to-analog conversion register, a program controller, a dc controller and an amplifier, the System on Chip transmits the data signal and the clock signal to a logic board through an I2C serial bus, one of which is a serial data line (SDA) and the other is a Serial Clock Line (SCL), respectively, through an I2C interface of the power management Chip 11, and the I2C serial bus clamps the data signal to a high level through pull-up resistors R1 and R2, as shown in fig. 2, when the power management Chip 11 also has no input voltage (VIN in fig. 1), if it detects that the reference voltage (VL in fig. 1) is lower than a preset value, resetting a register; as shown in fig. 3, when the power management chip 11 has no input voltage (VIN in fig. 1), if the system-on chip 21 does not power down due to entering the standby mode, as shown in fig. 1, the pull-up voltage (i.e. the high level of the clamp) of the I2C serial bus still flows into the power management chip 11 through the I2C interface, so that the reference voltage (VIN in fig. 1) of the power management chip 11 cannot power down to a set value, for example, cannot power down to 2V, so that the power management chip 11 cannot reset the register, or even may erroneously change the register with an interference voltage, and finally the power management chip 11 may have a risk of voltage abnormality when it is turned on next time. Fig. 2 is a schematic flowchart of a normal reset of the register of the power management chip 11, and fig. 3 is a schematic flowchart of a non-reset of the register of the power management chip 11.
Based on this, the embodiment of the present invention provides a driving circuit for a display panel, which can enable a reference voltage to be powered down to a set value when an input voltage is powered down, so as to reset a register of a power management chip, avoid an interference voltage from falsely changing the register, and ensure that the power management chip is in a normal state when the power management chip is started next time.
Fig. 4 is a schematic structural diagram of a power down detection circuit 40 of a driving circuit according to an embodiment of the present invention, as shown in fig. 4, the power down detection circuit includes: a first transistor (i.e., the transistor Q1 in fig. 4), a transistor Q2 (i.e., the transistor Q2 in fig. 4), and an energy storage unit 41, wherein the transistor Q1 is a PNP transistor, and the transistor Q2 is an NPN transistor. In the power-down detection circuit 40, a base of the transistor Q1 is used for accessing an input voltage (see VIN in fig. 4) of the power management chip 11, an emitter of the transistor Q1 is accessed to the input voltage (see VIN in fig. 4) of the power management chip 11 through the energy storage unit 41, a collector of the transistor Q1 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is grounded, a collector of the transistor Q2 is connected to the power management chip 11, and the energy storage unit 41 is used for discharging when the input voltage is reduced to 0V specifically when the input voltage is powered down, so as to turn on the transistor Q1.
In one embodiment, as shown in fig. 5, the energy storage unit 41 may be a charging and discharging circuit, which discharges when the input voltage drops to 0V to turn on the transistor Q1, and charges through the input voltage when the input voltage of the power management chip 11 is normal. Specifically, the energy storage unit 41 includes a first resistor R1, a second resistor 2, and a charge-discharge capacitor C1, wherein the resistance of the first resistor R1 is greater than the resistance of the second resistor R2, for example, as shown in fig. 5, the resistance of the first resistor R1 is 8000 ohms, and the resistance of the second resistor R2 is 4000 ohms; the emitter of the triode Q1 is grounded through the first resistor R1 and a charge-discharge capacitor C1 respectively, and the first resistor R1 is connected in parallel with the charge-discharge capacitor C1; a first end of the second resistor R2 is used for accessing an input voltage of the power management chip 11, a second end of the second resistor R2 is grounded through the first resistor R1 and the charge-discharge capacitor C1, the second resistor R2 is used as a charge resistor to charge the charge-discharge capacitor C1, and a second end of the second resistor R2 is further connected to an emitter of the triode Q1; the charge/discharge capacitor C1 is discharged when the input voltage drops to 0V, and the first resistor R1 serves as a discharge resistor to discharge the charge/discharge capacitor C1.
In this embodiment, the first resistor R1 with a larger resistance as the discharge resistor can increase the discharge time of the charge-discharge capacitor C1, so that the charge-discharge capacitor C1 discharges slowly to ground through the resistor R1. The charging time of the charging/discharging capacitor C1 can be shortened by using the first resistor R1 as a charging resistor with a small resistance. Therefore, the resistance of the first resistor R1 is greater than the resistance of the second resistor R2, so as to ensure that the charging time is shorter than the discharging time, and further ensure the on-time of the transistor Q1 and the transistor Q2, that is, when the input voltage of the power management chip 11 is powered down, further, the reference voltage will have sufficient time to be powered down to the set value.
When the input voltage of the power management chip 11 is normal, the charging and discharging capacitor C1 is charged, when the input voltage drops to 0V, the charging and discharging capacitor C1 is discharged, the discharging time of the charging and discharging capacitor C1 can be adjusted by changing a time constant, the charging and discharging capacitor C1 and the first resistor R1 are in positive correlation, the time constant is the product of the capacitance of the charging and discharging capacitor C1 and the resistance of the first resistor R1, and the discharging time meets the following conditions:
wherein t is the discharge time; RC is the time constant; v0 is the initial voltage value across the charge and discharge capacitor; vt is a voltage across the charge/discharge capacitor C1 at any time when it is discharged; v1 is the voltage across the charge-discharge capacitor C1 when charged to its maximum value.
Further, as shown in fig. 5, the power down detection circuit 40 of the driving circuit may further include: a third resistor R3 and a fourth resistor R4, wherein the resistances of the third resistor R3 and the fourth resistor R4 are lower than 100 ohms, for example, as shown in fig. 5, the resistances of the third resistor R3 and the fourth resistor R4 are both 100 ohms. Specifically, the second end of the second resistor R2 is connected to the emitter of the transistor Q1 through the third resistor R3; the emitter of the triode Q1 is grounded through the third resistor R3 and the first resistor R1 and the charging and discharging capacitor C1, respectively; the base of the triode Q1 is connected to the input voltage of the power management chip 11 through the fourth resistor R4.
By adding the third resistor R3 and the fourth resistor R4 to the power failure detection circuit 40, the function of limiting current can be achieved, thereby improving the safety of the power failure detection circuit 40.
As an alternative embodiment, as shown in fig. 5, the power down detection circuit 40 of the driving circuit may further include a diode D1. Specifically, the collector of the transistor Q2 is connected to the reference voltage of the power management chip 11 through the diode D1, wherein the cathode of the diode D1 is connected to the collector of the transistor Q2, and the anode of the diode D1 is connected to the power management chip 11.
Because the diode has a unidirectional conduction characteristic, i.e. current flows in from the anode and flows out from the cathode of the diode, the diode D1 in this embodiment only allows the reference voltage of the power management chip 11 to flow to the transistor Q2, but does not allow the voltage of the transistor Q2 to flow to the power management chip 11 to affect the reference voltage of the power management chip 11, so the diode D1 can prevent the reference voltage of the power management chip 11 from being affected when the power down detection circuit 40 is abnormal.
In the power down detection circuit 40 of the driving circuit according to the embodiment of the present invention, when the electronic device is powered down, the input voltage of the power down detection circuit 40 is rapidly reduced to 0V, the voltage at the base of the transistor Q1 is also 0V, at this time, the energy storage unit 41 discharges, so that the voltage at the emitter of the transistor Q1 (i.e., point ① in fig. 4 or fig. 5) is greater than the voltage at the base of the transistor Q1, i.e., point ② in fig. 4 or fig. 5), the voltage at the base of the transistor Q2 (i.e., point ③ in fig. 4 or fig. 5) is greater than the voltage at the collector of the transistor Q2 when the transistor Q Q1. is turned on, the transistor Q2 is turned on, the reference voltage of the power management chip 11 connected to the collector of the transistor Q2 is pulled down to ground through the transistor Q2, the reference voltage can be reduced to a set value, so that the register of the power management chip Q11 is reset, thereby ensuring that the voltage at the next power up of the electronic device is normal, and improving the reliability of the electronic device when the power down detection circuit is further, the power down detection circuit further includes a power down detection circuit that the power down detection circuit detects that the power down time when the power down detection circuit detects the power down, the power down detection circuit detects that the power down detection circuit fails to include the power down, the power down detection circuit, the power management circuit may further includes the power down detection circuit, the power management circuit detects that the power management circuit 40, the power management circuit detects that the power down detection circuit 40, the power down time when the power down detection circuit detects an abnormal power down time when the power down detection circuit 40, the power down detection circuit detects the power down detection circuit 40, the power down time when the power down detection circuit detects the power down time when the power down detection circuit includes the power down time when the power management circuit 40, the power management circuit 40.
The embodiment of the present invention further provides a logic circuit, which includes the power failure detection circuit 40, and the logic circuit can be applied to a display screen to enable the display screen to work normally, and the logic circuit can be disposed in any electronic device including the display screen, such as a mobile terminal. Fig. 7 is a logic circuit according to an embodiment of the present invention, please refer to fig. 7, the logic circuit includes a logic board 10, a clock line 71, a data line 72, a signal board 20 for providing a clock signal and a data signal, and two pull-up resistors (R5, R6), and further includes a power-down detection circuit 40, the logic board includes a power management chip 11 and a timing controller 12, as shown in fig. 4, the power-down detection circuit 40 includes a first transistor (a transistor Q1 in fig. 4), a second transistor (a transistor Q2 in fig. 4), and an energy storage unit 41, the transistor Q1 is a PNP transistor, and the transistor Q2 is an NPN transistor; the base of the triode Q1 is connected to the input voltage of the power management chip 11, the emitter of the triode Q1 is connected to the input voltage of the power management chip 11 through the energy storage unit 41, the collector of the triode Q1 is connected to the base of the triode Q2, the emitter of the triode Q2 is grounded, the collector of the triode Q2 is connected to the reference voltage of the power management chip 11, and the energy storage unit 41 is used for discharging when the input voltage drops to 0V to turn on the triode Q1; the signal board 20 is connected to the power management chip 11 through a clock line 71 and a data line 72, the power management chip 11 is further connected to the timing controller 12, the signal board 20 transmits a clock signal and a data signal from the clock line 71 and the data line 72 to the power management chip 11, and the power management chip 11 forwards the clock signal and the data signal to the timing controller 12, one of the two pull-up resistors R5 clamps the clock signal transmitted by the clock line 71 to a high level, and the other pull-up resistor R6 clamps the data signal transmitted by the data line 72 to a high level.
For specific limitations of the embodiment of the present invention on the power-down detection circuit 40 of the driving circuit, reference may be made to the foregoing embodiments, and the limitations are not repeated here.
Specifically, referring to fig. 7, the signal board 20 includes a system-on-chip 21 and a first printed circuit board 22, the system-on-chip 21 is configured to provide the clock signal and the data signal, the system-on-chip 21 is disposed on the first printed circuit board 13, and the clock line 71 and the data line 72 are both signal lines of an I2C serial bus; the power management chip 11 includes an I2C interface 111, and the soc 21 is connected to the I2C interface 111 through the clock line 71 and the data line 72, and then connected to the timing controller 12 through the I2C interface 111. The pull-up voltage of the I2C serial bus will sink into the power management chip 11 when the input voltage of the power management chip 11 is powered down and the system-on-chip 21 is not powered down.
Further, referring to fig. 7, the power management chip 11 further includes a voltage regulator 112, a capacitor C2, a digital-to-analog conversion register 113, a program controller 114, a dc controller 115, and an amplifier 116; the I2C interface 111, the digital-to-analog conversion register 113, the program controller 114, the dc controller 115, and the amplifier 116 are connected in series, the regulator 112 is configured to access an input voltage and generate a reference voltage, the reference voltage is used to provide a stable reference voltage for the I2C interface 111 and the dc controller 115, etc., the base of the transistor Q1 and the energy storage unit 41 in fig. 4 or fig. 5 are connected to the input terminal of the regulator 112 in fig. 7 to access the input voltage of the power management chip 11, the collector of the second transistor is connected to the output terminal of the regulator 112 to access the reference voltage of the power management chip 11, and the regulator 112 is further connected to ground through the capacitor C2.
Specifically, as shown in fig. 5, when the energy storage unit 41 includes a resistor R1, a resistor R2, and a charging/discharging capacitor C1, the resistor R2 is connected to the voltage regulator 112 shown in fig. 7, so as to access the input voltage of the power management chip 11.
Specifically, referring to fig. 7, the logic board further includes a second printed circuit board 13, the power management chip 11, the timing controller 12 and the power down detection circuit 40 are all disposed on the printed circuit board 13, and the power down detection circuit 40 may be regarded as one of the constituent structures of the logic board 10.
In the logic circuit, if the power management chip 11 is powered off, the signal board 20 is not powered off due to entering the standby mode, and the like, the high level clamped on the clock line 71 and the signal line 72 may be used as a pull-up voltage to be injected into the power management chip 11, so that the reference voltage of the power management chip 11 cannot be powered off to a set value, and the power management chip 11 cannot reset the register, and even may cause an interference voltage to falsely change the register, and finally the power management chip 11 may have a risk of voltage abnormality when being powered on next time, but the power-off detection circuit 40 may detect the input voltage and the reference voltage of the power management chip 11, when the input voltage of the power management chip 11 is reduced to 0V, the energy storage unit 41 discharges to turn on the transistor Q1, so that the transistor Q2 is turned on, and the reference voltage of the power management chip 11 is pulled to the ground by the turned on transistor Q, the reference voltage can be powered down to a set value, so the power failure detection circuit 40 can ensure that the reference voltage is powered down to the set value when the above condition occurs, thereby resetting the register of the power management chip 11, avoiding the interference voltage from changing the register by mistake, and ensuring that the power management chip 11 is in a normal state when being started next time.
Although the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present invention includes all such modifications and variations, and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification. In addition, while a particular feature of the specification may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising. Further, it is understood that reference to "a plurality" herein means two or more. For the steps mentioned in the text, the numerical suffixes are only used for clearly expressing the embodiments and are convenient for understanding, the execution sequence of the steps is not completely represented, and the logical relationship should be set as the consideration
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as the mutual combination of technical features between various embodiments, or the direct or indirect application to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. The utility model provides a display panel's drive circuit, its characterized in that, drive circuit including power down detection circuitry, with the power management chip that power down detection circuitry is connected, power down detection circuitry includes: the energy storage device comprises a first triode, a second triode and an energy storage unit, wherein the first triode is a PNP type triode, and the second triode is an NPN type triode;
the base of the first triode is used for being connected with the input voltage of the power management chip, the emitting electrode of the first triode is connected with the input voltage of the power management chip through the energy storage unit, the collecting electrode of the first triode is connected with the base of the second triode, the emitting electrode of the second triode is grounded, the collecting electrode of the second triode is used for being connected with the reference voltage of the power management chip, and the energy storage unit is used for discharging when the input voltage is reduced to 0V so as to conduct the first triode.
2. The circuit of claim 1, wherein the energy storage unit comprises: the circuit comprises a first resistor, a second resistor and a charge-discharge capacitor, wherein the resistance value of the first resistor is larger than that of the second resistor;
the emitter of the first triode is grounded through the first resistor and the charge-discharge capacitor respectively, and the first resistor is connected with the charge-discharge capacitor in parallel; the first end of the second resistor is used for being connected with the input voltage of the power management chip, the second end of the second resistor is grounded through the first resistor and the charge-discharge capacitor respectively and used for charging the charge-discharge capacitor, and the second end of the second resistor is also connected with the emitter of the first triode; the charge and discharge capacitor is discharged when the input voltage drops to 0V.
3. The circuit of claim 2, wherein the discharge time of the charge-discharge capacitor is positively correlated to a time constant, wherein the time constant is a product of a capacitance value of the charge-discharge capacitor and a resistance value of the first resistor.
4. The circuit of claim 3, wherein the discharge time satisfies the following condition:
wherein t is the discharge time; RC is the time constant; v0The initial voltage value of two ends of the charge-discharge capacitor is obtained; vtThe voltage at the two ends at any time when the charge and discharge capacitor is discharged; v1And charging the charge-discharge capacitor to a maximum value.
5. The circuit of any of claims 2-4, further comprising: the resistance values of the third resistor and the fourth resistor are both lower than 100 ohms;
the second end of the second resistor is connected with the emitter of the first triode through the third resistor; the emitter of the first triode is grounded through the third resistor and the first resistor and the charge-discharge capacitor respectively;
and the base electrode of the first triode is connected with the input voltage of the power management chip through the fourth resistor.
6. The circuit of any of claims 2-4, further comprising a diode, wherein the collector of the second transistor is coupled to the power management chip via the diode, wherein the cathode of the diode is coupled to the collector of the second transistor, and the anode of the diode is coupled to the power management chip.
7. The logic circuit of the electronic equipment is characterized by comprising a logic board, a clock line, a data line, a signal board for providing a clock signal and a data signal, two pull-up resistors and a power failure detection circuit, wherein the logic board comprises a power management chip and a time schedule controller;
the signal board is respectively connected with the power management chip through a clock line and a data line, the power management chip is also connected with the time schedule controller, the signal board respectively transmits clock signals and data signals to the power management chip from the clock line and the data line, the clock signals and the data signals are relayed to the time schedule controller by the power management chip, one of the two pull-up resistors clamps the clock signals transmitted by the clock line to a high level, and the other pull-up resistor clamps the data signals transmitted by the data line to the high level;
the power failure detection circuit comprises a first triode, a second triode and an energy storage unit, wherein the first triode is a PNP type triode, and the second triode is an NPN type triode; the base of the first triode is connected with the input voltage of the power management chip, the emitter of the first triode is connected with the input voltage of the power management chip through the energy storage unit, the collector of the first triode is connected with the base of the second triode, the emitter of the second triode is grounded, the collector of the second triode is connected with the reference voltage of the power management chip, and the energy storage unit is used for discharging when the input voltage is reduced to 0V so as to conduct the first triode.
8. The logic circuit of claim 7, wherein the signal board comprises a first printed circuit board and a system-on-chip, the system-on-chip being configured to provide the clock signal and the data signal, the system-on-chip being disposed on the first printed circuit board, the clock line and the data line both being signal lines of an I2C serial bus; the power management chip comprises an I2C interface, and the system-on-chip is respectively connected with the I2C interface through the clock line and the data line and then connected with the timing controller through the I2C interface.
9. The logic circuit of claim 8, wherein the power management chip further comprises a voltage regulator, a capacitor, a digital-to-analog conversion register, a program controller, a dc controller, and an amplifier;
the I2C interface, the digital-to-analog conversion register, the program controller, the direct current controller and the amplifier are connected in series, the voltage stabilizer is used for accessing the input voltage and generating a reference voltage, and the base electrode of the first triode and the energy storage unit are both connected with the input end of the voltage stabilizer so as to access the input voltage of the power management chip; and the collector electrode of the second triode is connected with the direct current controller so as to be connected with the reference voltage of the power management chip, and the voltage stabilizer is grounded through the capacitor.
10. The logic circuit of any of claims 7-9, the logic board further comprising a second printed circuit board, the power management chip, the timing controller, and the power down detection circuit all disposed on the second printed circuit board.
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| CN111667785A (en) * | 2020-07-07 | 2020-09-15 | 京东方科技集团股份有限公司 | Control circuit, Tcon board and display device |
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| CN110992866B (en) | 2022-12-06 |
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