CN107517046A - A kind of multi-clock selection switching circuit, clock switching chip and method - Google Patents
A kind of multi-clock selection switching circuit, clock switching chip and method Download PDFInfo
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- CN107517046A CN107517046A CN201710502648.2A CN201710502648A CN107517046A CN 107517046 A CN107517046 A CN 107517046A CN 201710502648 A CN201710502648 A CN 201710502648A CN 107517046 A CN107517046 A CN 107517046A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Abstract
The invention discloses a kind of multi-clock selection switching circuit, clock switching chip and method, wherein multi-clock selection switching circuit includes：The Clock gating submodule equal with clock input signal quantity, only one is used to pass through output multi-channel input clock in these Clock gating submodules, and remaining Clock gating submodule is used to forbid output multi-channel input clock；The Enable Pin of each Clock gating submodule cascades with one and logic gate component respectively, for being respectively that Clock gating submodule produces enable signal；The output end of all Clock gating submodules is respectively connecting to that same input quantity is equal with clock input signal quantity or an input of logic gate component；Or the output end of logic gate component is the output end that multi-clock selects switching circuit.
Description
Technical field
The invention belongs to chip circuit design field, more particularly to a kind of multi-clock selection switching circuit, clock switching core
Piece and method.
Background technology
At present, clock switch circuit is conceived to the switching (switching between mainly two clocks) for how realizing clock,
How to avoid producing burr and control the frequency of output clock to change to realize that clock switches using hardware circuit.
But these clock switch circuits there is also it is certain the problem of, be mainly reflected in：Clock switch circuit is relatively simple,
Few inventions can embody a concentrated reflection of the circuit of multiple advantages on one clock switch circuit, the stability of some circuits and can
It is also not high enough by property.
Number of patent application is the hair of the research institute of China Electronic Science and Technology Corporation the 47th of " 201410754184.0 "
Bright patent application " dynamic switching circuit of clock and method ", it can realize the free switching of two clock signals, it is ensured that any
The moment clock signal of output is all input clock signal all the way therein, but it is there is also certain deficiency, when not possessing more
The advantages of clock impulse- free robustness switching circuit.
Number of patent application is special for the invention of the Shanghai Huahong Grace Semiconductor Manufacturing Corporation of " 201410608180.1 "
Profit application " clock switch circuit ", which show a kind of clock switch circuit, can eliminate burr during clock switching.But it is also deposited
In certain deficiency, this circuit can not effectively reduce the influence that metastable state is brought to circuit.
Number of patent application is " a kind of to be used for clock switching for the application for a patent for invention of the University Of Tianjin of " 201610599180.9 "
The automatic reset structure of process ", this invention can export reset signal automatically when clock selection signal changes, and
After the completion of clock switch circuit switching, reset signal is automatically removed, makes controlled circuit normal work.But there is also certain for it
Deficiency, this automatic reset structure is complex, configures underaction.
Number of patent application is the patent of invention of the big IC system engineering technology in Jiangsu east of " 201220705460.0 "
Apply for " a kind of clock switch circuit " which show a kind of new clock switch circuit, thering is that hardware configuration is simple, configuration spirit
The advantages of living and stable performance.But this invention can not explicitly point out two-way or how multipath clock carries out selection and cut
Change.
In summary, single for clock switching in the prior art, clock handoff procedure can produce burr, metastable production
The technical problem such as raw, still lacks effective solution.
The content of the invention
In order to solve the deficiencies in the prior art, the invention provides a kind of multi-clock to select switching circuit, multi-clock choosing
The clock that selecting switching circuit can input is extended, and the switching of multichannel input clock can be achieved, can also arbitrarily be switched
Sequentially, the mode of operation for integrated circuit provides very strong flexibility.
A kind of multi-clock selection switching circuit of the present invention, including：The Clock gating equal with clock input signal quantity
Submodule, only one is used to pass through output multi-channel input clock in these Clock gating submodules, and remaining Clock gating is sub
Module is used to forbid output multi-channel input clock；
The Enable Pin of each Clock gating submodule cascades with one and logic gate component respectively, for being respectively clock gate
Control submodule and produce enable signal；
The output end of all Clock gating submodules is respectively connecting to same input quantity and clock input signal number
Measure equal or logic gate component a input；Or the output end of logic gate component is that multi-clock selects the defeated of switching circuit
Go out end.
Further, the quantity at least two of clock input signal.
Further, each Clock gating submodule cascades the enable signal formed including one by two d type flip flops
Synchronizer, one by d type flip flop and one two input and logic gate component, and Clock gating submodule can ensure enabled letter
Number clock input trailing edge carry out latch operation will not cause sequential competition problem.
Further, if under any input condition, clock input maintains high level when always needing not run, then is used for
Forbidding the Clock gating submodule of output multi-channel input clock includes two cascaded D-flip-flops and one two input and gate member
Part, the output end of two cascaded D-flip-flops are connected to the input with two input logic gating elements, and clock input is patrolled with two inputs
Another input for collecting gating element is connected.
Further, when the quantity of clock input signal keeps low level for two and hard reset signal, for avoid with
Switching postpones afterwards, with keeping the first with gate of any Clock gating sub-module cascade for being connected of low level hard reset signal
The input of part is serially connected with a NOT logic gating element.
Further, when the quantity of clock input signal is at least three, per the increase control signal of input clock all the way,
And it is synchronous with per clock all the way that clock inputs control signal.
Present invention also offers the method for work of multi-clock selection switching circuit.
The method of work of the multi-clock selection switching circuit of the present invention, including：
Clock input signal is inputted to the clock input signal of Clock gating submodule, only a Clock gating submodule
By output multi-channel input clock, remaining Clock gating submodule forbids output multi-channel input clock；
Cascaded respectively with the Enable Pin of each Clock gating submodule and logic gate component, respectively Clock gating submodule
Block produces enable signal；
The output signal of Clock gating submodule inputs equal with clock input signal quantity to same input quantity
Or logic gate component, finally by or logic gate component selection all the way clock input signal export.
Further, this method also includes：When the quantity of clock input signal keeps low electricity for two and hard reset signal
Usually, to avoid then switching from postponing, with any Clock gating submodule level for keeping low level hard reset signal to be connected
It is joining to be serially connected with a NOT logic gating element with logic gate component input.
Further, this method also includes：When the quantity of clock input signal is at least three, per input clock all the way
Increase control signal, and clock input control signal is synchronous with per clock all the way.
Present invention also offers a kind of clock to switch chip.
The clock switching chip of the present invention, switching circuit is selected comprising multi-clock described above.
Compared with prior art, the beneficial effects of the invention are as follows：
(1) multi-clock of the invention selection switching circuit, there is provided one kind prevents clock from dynamically being cut between different clock-domains
Occurs the circuit of burr when changing, circuit switching at runtime is convenient, and reliability and stability are higher, and metastable state probability of happening is low, energy
The effective appearance for reducing burr.Meanwhile this circuit employs the integrated of clock MUX IP.
(2) multi-clock of the invention selection switching circuit, can effectively eliminate be likely to occur in clock handoff procedure it is competing
Strive, occur the purpose of burr when preventing clock switching at runtime so as to reach；Clock MUX IP's is integrated, improves circuit
Stability and reliability；Using synchronizer, the probability that metastable state occurs can be efficiently reduced.
(3) multi-clock of the invention selection switching circuit, there is the advantages of flexible configuration, stable performance.Solves clock
Switch single, clock handoff procedure can produce burr, metastable the technical problem such as to produce, ensure that can input clock expanded
During exhibition, the stability and reliability of circuit.
Brief description of the drawings
The Figure of description for forming the part of the application is used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its illustrate be used for explain the application, do not form the improper restriction to the application.
Fig. 1 is the clock selector circuit top level structure of two clocks input.
Fig. 2 is the integrated circuit structure of three input clock selecting modules.
Fig. 3 is clock gating unit " CLOCK_ON_RESET " circuit inner structure.
Fig. 4 is clock gating unit " CLOCK_OFF_RESET " circuit inner structure.
Fig. 5 is clock gating unit " CLOCK_OFF_RESET-uncontrollable clock_in " versions.
Embodiment
It is noted that described further below is all exemplary, it is intended to provides further instruction to the application.It is unless another
Indicate, all technologies used herein and scientific terminology are with usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is also intended to include plural form, additionally, it should be understood that, when in this manual using term "comprising" and/or " bag
Include " when, it indicates existing characteristics, step, operation, device, component and/or combinations thereof.
As background technology is introduced, the deficiencies in the prior art, in order to solve technical problem as above, this Shen
It please propose a kind of multi-clock selection switching circuit.
As shown in figure 1, two clock input clock selectors herein are made up of 6 elements, 2 section clock gate therein
Submodule " CLOCK_ON_RESET " forbids output or by defeated with " CLOCK_OFF_RESET " for 2 road input clocks
Go out.What Clock gating submodule " CLOCK_ON_RESET " above cascaded with " CLOCK_OFF_RESET " uses with door " AND " logic
In producing enable signal (enable), Clock gating submodule " CLOCK_ON_RESET " and " CLOCK_ for each submodule
OR gate " OR " logic for one two input that OFF_RESET " is cascaded below is to " CLOCK_ON_RESET " and " CLOCK_OFF_
After RESET " output is carried out or operated, the final input clock of only selection all the way is exported.Wherein clock selection circuit mould
OR gate " OR " logic is cascaded behind block to be customized, ensure OR gate " OR " from logical zero to the rise time of " 1 " with from logic
The fall time of " 1 " to " 0 " is quick and symmetrical, and the control signal for being used to produce enabled " enable " is can to integrate production
Raw.
As shown in figure 3, Clock gating module, which includes one, is cascaded enabled " enable " signal formed by two d type flip flops
Synchronizer and a clock gating unit combined by d type flip flop and AND with door, and by customization, ensure enabled
" enable " signal carries out latch operation not in the trailing edge of clock input " input_0_clock " or " input_1_clock "
Sequential competition problem can be caused.There is the clock gating unit of two versions herein：" CLOCK_ON_RESET " version is hard multiple
When position (hard_reset) is effective, clock output is enabled；" CLOCK_OFF_RESET " version is hard reset (hard_reset)
When invalid, clock output is forbidden.
In a clock selection circuit, can absolutely not there are more than two Clock gating component " CLOCK_ON_
RESET " modules, if last output clock " output_clock " can not change during reset, one is used respectively
Individual " CLOCK_ON_RESET " clock gating unit and " CLOCK_OFF_RESET " clock gating unit；If during output
Clock " output_clock " allows to change during reset, then using " CLOCK_ON_RESET " Clock gating and two
" CLOCK_OFF_RESET " clock gating unit.
As shown in figure 1, when hard reset signal " hard_reset_n " keeps low level, first via input clock
" input_0_clock " is driven to the final output port " output_clock " of module, and clock selection signal " clock_
Select " can remain low level " 0 " (if selection clock input_0_clock) in advance, avoid the delay then switched
Problem.
In Clock gating module, each clock gating unit " CLOCK_ON_RESET " and " CLOCK_OFF_
RESET " output " clock_off " be all cross-coupled feed back to before another Clock gating module with door " AND "
Input.
Clock selection signal " clock_select " not necessarily with any input clock all the way：" input_0_clock " or
Person " input_1_clock " synchronizes, if any input clock signal " input_0_clock " and " input_1_
Clock " is without upset, then clock selection signal " clock_select " must be maintained at low level " 0 ".
As shown in Fig. 2 the clock selection circuit module of N roads input is more more complex than two input clock selection circuits, but N
The basic circuit component with two input clock selection circuit module same types has been used inside the clock selection circuit of road.Due to N
Road clock input selecting module, this circuit structure can expand to any multichannel (N>=3) clock input selection circuit, and
Its principle is the same, therefore 3 input selection circuits are only discussed herein.
Two input clock selection circuits need a clock gating unit " CLOCK_ON_RESET " and " CLOCK_OFF_
RESET " units, if being further added by input clock all the way, just need to increase a Clock gating " CLOCK_OFF_RESET " in addition
Unit (does not allow the clock gating unit for increasing CLOCK_ON_RESET types).Relative to 2 road clocks input selecting modules, 3
Input selection circuit (N>=3) the input control signal to integral module has made change slightly：To increase per input clock all the way
Increase control signal, and clock input control signal can be with synchronizing per clock all the way.
For before " CLOCK_ON_RESET " unit with door " AND ", its clock input select signal " disable_n "
(low level is effective) is carried out with " clock_off " signal that remaining " CLOCK_OFF_RESET " clock gating unit is fed back
With operation；For before " CLOCK_OFF_RESET " unit with " AND " door, to " disable " (high level is effective) with
" clock_off " signal operated with " AND ".
As shown in figure 3, the clock selection circuit, including clock gating unit " clock-gate cell " and one two
The synchronizer of level cascade；" clock-gate cell " can perform reliable open and pass through or no thoroughfare input clock gate
Clock, without causing short impulse disturbances noise in output terminal of clock.The trigger " flip-flop " being contained in stone, make
For the second level of synchronizer.First order trigger in the synchronizer of two trigger cascades receives the letter of enabled " enable "
Number, all it is the trailing edge progress signal latch in clock as the trigger of the second level.The synchronizer of two-stage cascade is for using
45nm techniques with the clock frequency currently run be enough.Hard reset signal " hard_reset_n " is believed with clock
Number it is asynchronous.
Although hard reset signal " hard_reset_n " is provided with the trigger of the first order in synchronizer, to the second level
Trigger is zeroed out operation, and the first time clock pulses after asynchronous reset will be set first order second level trigger
To the correct state of latch.If the trigger of the second level is also set such as first order trigger, all input clocks are all
It can be locked, clock upset is produced without exporting again.
There are two kinds of circuit structure selections, it is resolved that whether there is controllability in clock input.If clock input always needs
Export or low level is maintained when not running, then clock gating unit " CLOCK_OFF_RESET " unit, uses Fig. 4 electricity
Line structure.If under any input condition, clock input maintains high level when always needing not run, then clock gating unit
" CLOCK_OFF_RESET " unit, uses Fig. 5 circuit structure.
For clock gating unit " CLOCK_OFF_RESET ", it includes gate part " clock-gate cell " and two
The synchronizer of level trigger cascade.Gate part " clock-gate cell " can reliably open or close this clock, without
Short pulse can be caused in output end.
Second level trigger in stone module is used for the second level of synchronizer, and the trigger of the first order and the second level is all
Trailing edge on clock edge is latched.The synchronizer of two-stage cascade, clock frequency will in the manufacturing process and design of consideration
Ask, two-stage cascade is enough.If the trigger of more similar first order not enough, can be added.Hard reset " hard_
Reset_n " signals are asynchronous resets.
For this " CLOCK_OFF_RESET " version, when that need not overturn, clock preferably must be held in low level.For
" CLOCK_OFF_RESET-uncontrollable clock_in " versions, the module include and door " AND " clock gating unit
With the synchronizer of two-stage cascade, " clock-gate cell " are not used.The first order and second level trigger in synchronizer are all
Latched in clock falling edge.Consider technique limitation and the clock frequency speed of service, the synchronizer of two-stage cascade is
Enough.If can not meet, more levels need to cascade up.Hard reset is asynchronous reset signal, and clock is uncontrollable
's.
The multi-clock selection switching circuit of the present invention, there is provided one kind prevents clock between different clock-domains during switching at runtime
There is the circuit of burr, circuit switching at runtime is convenient, and reliability and stability are higher, and metastable state probability of happening is low, can be effective
Reduction burr appearance.Meanwhile this circuit employs the integrated of clock MUX IP.
The multi-clock selection switching circuit of the present invention, can effectively eliminate the competition being likely to occur in clock handoff procedure,
Occurs the purpose of burr when preventing clock switching at runtime so as to reach；Clock MUX IP's is integrated, improves the steady of circuit
Qualitative and reliability；Using synchronizer, the probability that metastable state occurs can be efficiently reduced.
The multi-clock selection switching circuit of the present invention, has the advantages of flexible configuration, stable performance.Solves clock switching
Single, clock handoff procedure can produce burr, metastable the technical problem such as to produce, ensure that can input clock be extended
Cheng Zhong, the stability and reliability of circuit.
The method of work of the multi-clock selection switching circuit of the present invention, including：
Clock input signal is inputted to the clock input signal of Clock gating submodule, only a Clock gating submodule
By output multi-channel input clock, remaining Clock gating submodule forbids output multi-channel input clock；
Cascaded respectively with the Enable Pin of each Clock gating submodule and logic gate component, respectively Clock gating submodule
Block produces enable signal；
The output signal of Clock gating submodule inputs equal with clock input signal quantity to same input quantity
Or logic gate component, finally by or logic gate component selection all the way clock input signal export.
In another embodiment, this method also includes：When the quantity of clock input signal is protected for two and hard reset signal
When holding low level, to avoid then switching from postponing, with any Clock gating for keeping low level hard reset signal to be connected
Module-cascade is serially connected with a NOT logic gating element with the input of logic gate component.
In another embodiment, this method also includes：When the quantity of clock input signal is at least three, per defeated all the way
Enter clock increase control signal, and clock input control signal is synchronous with per clock all the way.
Present invention also offers a kind of clock to switch chip.
The clock switching chip of the present invention, switching circuit is selected comprising above-mentioned multi-clock as shown in Figure 1 or 2.
Although above-mentioned the embodiment of the present invention is described with reference to accompanying drawing, model not is protected to the present invention
The limitation enclosed, one of ordinary skill in the art should be understood that on the basis of technical scheme those skilled in the art are not
Need to pay various modifications or deformation that creative work can make still within protection scope of the present invention.
Claims (10)
1. a kind of multi-clock selects switching circuit, it is characterised in that including：The Clock gating equal with clock input signal quantity
Submodule, only one is used to pass through output multi-channel input clock in these Clock gating submodules, and remaining Clock gating is sub
Module is used to forbid output multi-channel input clock；
The Enable Pin of each Clock gating submodule cascades with one and logic gate component respectively, for being respectively Clock gating
Module produces enable signal；
The output end of all Clock gating submodules is respectively connecting to same input quantity and clock input signal quantity phase
Deng or logic gate component an input；Or the output end of logic gate component is the output that multi-clock selects switching circuit
End.
2. a kind of multi-clock selection switching circuit as claimed in claim 1, it is characterised in that the quantity of clock input signal is extremely
It is two less.
3. a kind of multi-clock selection switching circuit as claimed in claim 1, it is characterised in that each Clock gating submodule is equal
Including one by two d type flip flops cascade the enable signal synchronizer formed, one by d type flip flop and one two input with patrolling
Gating element is collected, and Clock gating submodule can ensure that enable signal carries out latch operation in the trailing edge that clock inputs and will not drawn
Play sequential competition problem.
A kind of 4. multi-clock selection switching circuit as claimed in claim 1, it is characterised in that if under any input condition,
Clock input maintains high level when always needing not run, then is used for the Clock gating submodule for forbidding output multi-channel input clock
Including two cascaded D-flip-flops and one two input and logic gate component, the output end of two cascaded D-flip-flops is connected to and two
The input of input logic gating element, clock input are connected with another input of two input logic gating elements.
5. a kind of multi-clock selection switching circuit as claimed in claim 2, it is characterised in that when the quantity of clock input signal
When keeping low level for two and hard reset signal, to avoid then switching from postponing, with keeping low level hard reset signal
Connected any Clock gating sub-module cascade is serially connected with a NOT logic gating element with the input of logic gate component.
6. a kind of multi-clock selection switching circuit as claimed in claim 2, it is characterised in that when the quantity of clock input signal
At at least three, per the increase control signal of input clock all the way, and clock input control signal is synchronous with per clock all the way.
A kind of 7. method of work of multi-clock selection switching circuit as claimed in claim 1, it is characterised in that including：
Clock input signal, which is inputted to the clock input signal of Clock gating submodule, only a Clock gating submodule, to be passed through
Output multi-channel input clock, remaining Clock gating submodule forbid output multi-channel input clock；
Cascaded respectively with the Enable Pin of each Clock gating submodule and logic gate component, respectively Clock gating submodule produce
Raw enable signal；
The output signal of Clock gating submodule input to same input quantity it is equal with clock input signal quantity or
Logic gate component, finally by or logic gate component selection all the way clock input signal export.
8. the method for work of multi-clock selection switching circuit as claimed in claim 7, it is characterised in that this method also includes：
When the quantity of clock input signal is two and hard reset signal keeps low level, to avoid then switching from postponing, with
It is keeping the connected any Clock gating sub-module cascade of low level hard reset signal to be serially connected with logic gate component input
One NOT logic gating element.
9. the method for work of multi-clock selection switching circuit as claimed in claim 7, it is characterised in that this method also includes：
When the quantity of clock input signal is at least three, per the increase control signal of input clock all the way, and clock input control
Signal is synchronous with per clock all the way.
10. a kind of clock switches chip, it is characterised in that is cut comprising the multi-clock selection as described in any in claim 1-6
Change circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710502648.2A CN107517046A (en) | 2017-06-27 | 2017-06-27 | A kind of multi-clock selection switching circuit, clock switching chip and method |
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|---|---|---|---|
| CN201710502648.2A CN107517046A (en) | 2017-06-27 | 2017-06-27 | A kind of multi-clock selection switching circuit, clock switching chip and method |
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| CN109948787A (en) * | 2019-02-26 | 2019-06-28 | 山东师范大学 | Arithmetic unit, chip and method for neural network convolutional layer |
| CN111769824A (en) * | 2020-07-13 | 2020-10-13 | 电子科技大学 | Configurable delay circuit |
| CN112214064A (en) * | 2019-07-11 | 2021-01-12 | 珠海格力电器股份有限公司 | Clock control method and device applied to chip system |
| CN113472325A (en) * | 2021-06-21 | 2021-10-01 | 京微齐力(深圳)科技有限公司 | Clock multiplexer and electronic equipment |
| CN113504809A (en) * | 2021-07-09 | 2021-10-15 | 广州安凯微电子股份有限公司 | Dynamic switching method, device and system of multi-channel clock |
| CN117422043A (en) * | 2023-12-19 | 2024-01-19 | 上海芯璐科技有限公司 | Circuit structure with clock network and control method thereof |
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| CN113504809B (en) * | 2021-07-09 | 2024-01-19 | 广州安凯微电子股份有限公司 | Dynamic switching method, device and system for multipath clocks |
| CN117422043A (en) * | 2023-12-19 | 2024-01-19 | 上海芯璐科技有限公司 | Circuit structure with clock network and control method thereof |
| CN117422043B (en) * | 2023-12-19 | 2024-03-19 | 上海芯璐科技有限公司 | Circuit structure with clock network and control method thereof |
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Application publication date: 20171226 |