CN112214064B - Clock control method and device applied to chip system - Google Patents
Clock control method and device applied to chip system Download PDFInfo
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- CN112214064B CN112214064B CN201910626030.6A CN201910626030A CN112214064B CN 112214064 B CN112214064 B CN 112214064B CN 201910626030 A CN201910626030 A CN 201910626030A CN 112214064 B CN112214064 B CN 112214064B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Abstract
The application relates to a clock control method and device applied to a chip system. The method comprises the following steps: the switching device can obtain an effective output clock signal according to the effective first clock input signal or the ineffective first clock input signal. Under the condition that the first clock input signal is normal and effective, the switching device keeps the original output clock signal as the clock source of the external circuit; if the first clock input signal is abnormal, the switching device switches the second clock signal in time to serve as an output clock signal, so that the circuit is ensured to keep the original normal operation, and the reliability of the chip clock is ensured.
Description
Technical Field
The present disclosure relates to the field of integrated chip technologies, and in particular, to a clock control method and apparatus for a chip system.
Background
The clock is the heart of the circuit, the stability and the reliability of the clock are the basis for the stable operation of the circuit, and the loss or the abnormity of the clock can cause the final function failure or the performance of the circuit to not meet the design requirements.
In the prior art, when a clock is lost or abnormal, a clock signal is switched by using a static frequency conversion mode, the frequency conversion is carried out after a circuit is required to stop running, and then the circuit is awakened, so that the circuit cannot be switched in the running process of the circuit.
Therefore, it is desirable to provide a working method with a simple implementation manner and capable of improving the reliability of the clock, so as to avoid the circuit operation abnormality caused by the instability of the clock.
Disclosure of Invention
In order to solve the above technical problem, the present application provides a clock control method and apparatus applied to a chip system.
In a first aspect, the present application provides a clock control method applied to a chip system, where the method includes:
the switching device obtains an effective output clock signal according to the effective first clock input signal;
the switching device obtains an effective output clock signal based on the ineffective first clock input signal.
Preferably, the switching device comprises a first clock generator, a flip-flop, a second clock generator and a clock switching module;
the switching device obtains an effective output clock signal according to an effective first clock input signal, and comprises:
the first clock generator obtains an effective first clock signal according to an effective first clock input signal;
the trigger obtains an effective control signal according to an effective first clock input signal and an effective first clock signal;
the second clock generator receives a second clock input signal, and the second clock generator obtains an invalid second clock signal according to an effective control signal and the second clock input signal;
the clock switching module obtains an effective output clock signal according to the effective first clock signal, the ineffective second clock signal and the effective control signal.
Preferably, the switching device includes a first clock generator, a flip-flop, a second clock generator and a clock switching module, and the switching device obtains an effective output clock signal according to an ineffective first clock input signal, including:
the first clock generator obtains an invalid first clock signal according to an invalid first clock input signal;
the trigger obtains an invalid control signal according to the invalid first clock input signal and the invalid first clock signal;
the second clock generator receives a second clock input signal, and the second clock generator obtains an effective second clock signal according to an invalid control signal and the second clock input signal;
the clock switching module obtains an effective output clock signal according to the ineffective first clock signal, the effective second clock signal and the ineffective control signal.
Preferably, the first clock generator includes a logical or operation module and a first clock generation module, obtains an effective control signal according to an effective first clock input signal, and includes:
when the first clock input signal is an effective signal, the first input end of the logic or operation module receives the effective first clock input signal, the second input end of the logic or operation module receives a control signal with an effective initial value, the logic or operation module obtains an effective first enable signal according to the effective first clock input signal and the control signal with the effective initial value,
the first clock generation module obtains an effective first clock signal according to an effective first enable signal;
the flip-flop derives an effective control signal from the effective first clock input signal and the effective first clock signal.
Preferably, the second clock generator includes a logical negation operation module, a logical and operation module, and a second clock generation module, and the second clock generator obtains an invalid second clock signal according to an effective control signal and the second clock input signal, including:
the logic negation operation module obtains an invalid logic negation signal according to the valid control signal;
the logic inversion operation module sends an invalid logic inversion signal to a first input end of the logic and operation module, a second input end of the logic and operation module receives a second clock input signal, and the logic and operation module obtains an invalid second enable signal according to the invalid logic inversion signal and the valid second clock input signal;
and the second clock generation module obtains an invalid second clock signal according to the invalid second enable signal.
Preferably, the second clock generator obtains an invalid second clock signal according to the valid control signal and the second clock input signal, and includes:
and the clock switching module selects the first clock signal as an output clock signal according to the effective first clock signal, the ineffective second clock signal and the effective control signal.
Preferably, the second clock generator includes a logical negation operation module, a logical and operation module, and a second clock generation module, and the flip-flop obtains an invalid control signal according to an invalid first clock input signal and an invalid first clock signal, including:
when the first clock input signal is an invalid signal, the first input end of the logic or operation module receives the invalid first clock input signal, the second input end of the logic or operation module receives a control signal with an effective initial value, the logic or operation module obtains an effective first enable signal according to the invalid first clock input signal and the control signal with the effective initial value,
the first clock generation module obtains an effective first clock signal according to an effective first enable signal,
the trigger obtains an invalid control signal according to the invalid first clock input signal and the valid first clock signal;
the valid first clock signal enters the next cycle, the first input end of the logic or operation module receives the invalid first clock input signal, the second input end of the logic or operation module receives the invalid control signal, the logic or operation module obtains the invalid first enable signal according to the invalid first clock input signal and the invalid control signal,
the first clock generation module obtains an invalid first clock signal according to the invalid first enable signal,
the flip-flop obtains an invalid control signal based on the invalid first clock input signal and the invalid first clock signal.
Preferably, the second clock generator obtains an active second clock signal according to the inactive control signal and the second clock input signal, and includes:
the logic negation operation module obtains an effective logic negation signal according to the ineffective control signal;
the logic inversion operation module sends an effective logic inversion signal to a first input end of the logic and operation module, a second input end of the logic and operation module receives an effective second clock input signal, and the logic and operation module obtains an effective second enabling signal according to the effective logic inversion signal and the effective second clock input signal;
and the second clock generation module obtains an effective second clock signal according to the effective second enable signal.
Preferably, the clock switching module obtains an effective output clock signal according to the ineffective first clock signal, the effective second clock signal and the ineffective control signal, and includes:
and the clock switching module selects the second clock signal as an output clock signal according to the invalid first clock signal, the valid second clock signal and the invalid control signal.
In a second aspect, the present application provides an apparatus applied to a system-on-a-chip, the apparatus comprising:
the first clock generator is used for obtaining a first clock signal according to a first clock input signal;
the trigger is used for obtaining a control signal according to the first clock input signal and the first clock signal;
the second clock generator is used for receiving an effective second clock input signal and obtaining a second clock signal according to the effective second clock input signal and the control signal;
and the clock switching module is used for obtaining an output clock signal according to the first clock signal, the second clock signal and the control signal.
The invention has the beneficial effects that:
the invention discloses a clock control method and a clock control device applied to a chip system, wherein the method comprises the following steps: the switching device can obtain an effective output clock signal according to the effective first clock input signal or the ineffective first clock input signal. Under the condition that the first clock input signal is normal and effective, the switching device keeps the original output clock signal as the clock source of the external circuit; if the first clock input signal is abnormal, the switching device switches the second clock signal in time to serve as an output clock signal, so that the circuit is ensured to keep the original normal operation, and the reliability of the chip clock is ensured.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.
FIG. 1 is a schematic block diagram of a clocking method applied to a system-on-chip in one embodiment;
FIG. 2 is a flowchart of a clock control method applied to a system-on-chip according to an embodiment;
FIG. 3 is a flow chart of an embodiment for deriving an active output clock signal from an active first clock input signal;
FIG. 4 is a flow diagram of deriving an active output clock signal from an inactive first clock input signal according to one embodiment;
FIG. 5 is a flow diagram of selecting a first clock signal as an output clock signal in one embodiment;
FIG. 6 is a flow diagram of selecting a second clock signal as an output clock signal in one embodiment;
fig. 7 is a schematic structural diagram of a clock control apparatus applied to a system on a chip according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic block diagram of a clock control method applied to a chip system according to an embodiment, a first input terminal of a logical or operation module 1011 receives a first clock input signal, an output terminal of the logical operation module is connected to an input terminal of a first clock generation module 1012, an output terminal of the first clock generation module 1012 is connected to a clock signal terminal of a flip-flop 102, a signal input terminal of the flip-flop 102 receives the first clock input signal, an output terminal of the flip-flop 102 is connected to the logical or operation module 1011, an output terminal of the flip-flop 102 is connected to a first input terminal of a clock switching module 104, an output terminal of the flip-flop 102 is further connected to an input terminal of a logical negation operation module 1031, an output terminal of the logical negation operation module 1031 is connected to a first input terminal of the logical and module 1012, a second input terminal of the logical and module receives a second clock input signal, an output terminal of the logical and operation module 1032 is connected to an input terminal of a second clock generation module 1033, an output terminal of the second clock generation module 1033 is connected to a second input terminal of the clock switching module 104, and an output terminal of the clock switching module 104 is connected to an output terminal of the clock switching module 104. The or logic module 1011 in fig. 1 obtains a first enable signal according to a first clock input signal and a control signal in an initial state, the first clock generation module 1012 obtains a first clock signal according to the first enable signal, the flip-flop 102 obtains a control signal according to the first clock input signal and the first clock signal, the negation logic module 1031 obtains a negation logic signal according to the control signal, the and logic module 1032 obtains a second enable signal according to the second clock input signal and the negation logic signal, the second clock generation module 1033 obtains a second clock signal according to the second enable signal, and the clock switching module 104 obtains an output clock signal according to the first clock signal, the second clock signal, and the control signal.
In an embodiment of the present invention, fig. 2 is a flowchart of a clock control method applied to a system on chip in an embodiment, and referring to fig. 2, a clock control method applied to a system on chip includes:
s100, the switching device obtains an effective output clock signal according to an effective first clock input signal;
s200, the switching device obtains an effective output clock signal according to the invalid first clock input signal.
The invention discloses a clock control method applied to a chip system, which receives a first clock input signal through a switching device, and the switching device outputs an effective output clock signal no matter whether the first clock input signal is effective or not. The switching device is used for ensuring that a subsequent circuit connected with the switching device has continuous and reliable clock signals, ensuring the stable operation of a chip system, outputting reliable clock signals without stopping the operation of the switching clock, and keeping the original output clock signals as clock sources of an external circuit under the condition that the first clock input signal is normal and effective; if the first clock input signal is abnormal, the switching device switches the second clock signal in time to serve as an output clock signal, so that the circuit is ensured to keep the original normal operation, and the reliability of the chip clock is ensured.
In an embodiment of the present invention, fig. 3 is a flowchart illustrating an embodiment of obtaining an effective output clock signal according to an effective first clock input signal, and referring to fig. 1 and fig. 3, the switching apparatus includes a first clock generator 101, a flip-flop 102, a second clock generator 103, and a clock switching module 104;
the switching device obtains an effective output clock signal according to an effective first clock input signal, and the step S100 includes the following specific steps:
s110, obtaining an effective first clock signal by the first clock generator 101 according to the effective first clock input signal;
s120, the trigger 102 obtains an effective control signal according to an effective first clock input signal and an effective first clock signal;
s130, the second clock generator 103 receives a second clock input signal, and the second clock generator 103 obtains an invalid second clock signal according to the valid control signal and the second clock input signal;
s140, the clock switching module 104 obtains an effective output clock signal according to the effective first clock signal, the ineffective second clock signal and the effective control signal.
Obtaining an effective output clock signal according to the effective first clock signal and the ineffective second clock signal, wherein the effective output clock signal represents that the first clock generator 101 normally operates to provide the first clock signal at the moment, the second clock generator 103 is in a closed state and cannot provide the effective second clock signal, and only the first clock generator operates in the state, so that the chip system is ensured to operate in a lower power consumption state.
In an embodiment of the present invention, fig. 4 is a flowchart illustrating an embodiment of obtaining a valid output clock signal according to an invalid first clock input signal, and referring to fig. 1 and 4, the switching device obtains a valid output clock signal according to an invalid first clock input signal, and the step S200 includes the following specific steps:
s210, obtaining an invalid first clock signal by the first clock generator 101 according to the invalid first clock input signal;
s220, the trigger 102 obtains an invalid control signal according to the invalid first clock input signal and the invalid first clock signal;
s230, the second clock generator 103 receives a second clock input signal, and the second clock generator 103 obtains an effective second clock signal according to the invalid control signal and the second clock input signal;
s240, the clock switching module 104 obtains an effective output clock signal according to the ineffective first clock signal, the effective second clock signal and the ineffective control signal.
The method comprises the steps of obtaining effective output clock signals according to invalid first clock signals and effective second clock signals, representing that the input signals of the first clock are abnormal at the moment, so that the first clock generator 101 cannot provide the effective first clock signals, switching to the second clock generator to work and operate through a switching device, providing the second clock signals as the output clock signals, ensuring normal operation of a circuit, avoiding the problem that reliable clock signals cannot be output due to the abnormal input signals of the first clock or the abnormal input signals of the first clock generator, ensuring the reliability of a chip system clock, and ensuring that the chip system operates in a lower power consumption state only by one clock operation.
In an embodiment of the present invention, fig. 5 is a flowchart illustrating an embodiment of selecting a first clock signal as an output clock signal, and referring to fig. 1 and fig. 5, the first clock generator 101 includes a logical or operation module 1011 and a first clock generation module 1012, and obtains an effective control signal according to an effective first clock input signal, and step S110 specifically includes the following steps:
s111, when the first clock input signal is an effective signal, a first input end of the logical or operation module 1011 receives the effective first clock input signal, a second input end of the logical or operation module 1011 receives a control signal whose initial value is effective, and the logical or operation module 1011 obtains an effective first enable signal according to the effective first clock input signal and the control signal whose initial value is effective;
s112, the first clock generating module 1012 obtaining an effective first clock signal according to the effective first enable signal;
step S120 specifically includes the following steps:
s121, the flip-flop 102 obtains an effective control signal according to the effective first clock input signal and the effective first clock signal.
The second clock generator 103 includes a logical negation operation module 1031, a logical and operation module 1032, and a second clock generation module 1033, where the second clock generator 103 obtains an invalid second clock signal according to an effective control signal and the second clock input signal, and the step S130 specifically includes the following steps:
s131, the logical inversion operation module 1031 obtains an invalid logical inversion signal according to the valid control signal;
s132, the logical negation operation module 1031 sends the invalid logical negation signal to the first input end of the logical and operation module 1032, the second input end of the logical and operation module 1032 receives the second clock input signal, and the logical and operation module 1032 obtains an invalid second enable signal according to the invalid logical negation signal and the valid second clock input signal;
s133, the second clock generating module 1033 obtains an invalid second clock signal according to the invalid second enable signal.
The second clock generator 103 obtains an invalid second clock signal according to the valid control signal and the second clock input signal, and the step S140 specifically includes the following steps:
s141, the clock switching module 104 selects the first clock signal as the output clock signal according to the valid first clock signal, the invalid second clock signal and the valid control signal.
In this state, no matter whether the second clock input signal of the input logic and operation module 1032 is valid or invalid, the valid control signal does not affect the second clock generation module 1033 to obtain an invalid second clock signal, so that only one clock is guaranteed to run, the first clock generation module 1012 generates the first clock signal, and the second clock generation module 1033 is in a closed state, so that the system-on-chip keeps clock signal output and keeps low-power-consumption running.
In an embodiment of the present invention, fig. 6 is a flowchart of selecting a second clock signal as an output clock signal in an embodiment, and referring to fig. 1 and fig. 6, obtaining an invalid control signal according to an invalid first clock input signal, where step S210 specifically includes the following steps:
s211, when the first clock input signal is an invalid signal, the first input end of the logical or operation module 1011 receives the invalid first clock input signal, the second input end of the logical or operation module 1011 receives a control signal whose initial value is valid, and the logical or operation module 1011 obtains a valid first enable signal according to the invalid first clock input signal and the control signal whose initial value is valid;
s212, the first clock generating module 1012 obtaining an effective first clock signal according to the effective first enable signal;
step S220 specifically includes the following steps:
s221, the trigger 102 obtains an invalid control signal according to the invalid first clock input signal and the valid first clock signal;
s222, the valid first clock signal enters the next period, the first input end of the logical or operation module 1011 receives the invalid first clock input signal, the second input end of the logical or operation module 1011 receives the invalid control signal, and the logical or operation module 1011 obtains the invalid first enable signal according to the invalid first clock input signal and the invalid control signal;
s223, the first clock generating module 1012 obtaining an invalid first clock signal according to the invalid first enable signal;
s224, the flip-flop 102 obtains an invalid control signal according to the invalid first clock input signal and the invalid first clock signal.
The second clock generator 103 obtains an effective second clock signal according to the invalid control signal and the second clock input signal, and step S230 specifically includes the following steps:
s231, the logical inversion module 1031 obtains an effective logical inversion signal according to the invalid control signal;
s232, the logical negation operation module 1031 sends an effective logical negation signal to the first input end of the logical and operation module 1032, the second input end of the logical and operation module 1032 receives an effective second clock input signal, and the logical and operation module 1032 obtains an effective second enable signal according to the effective logical negation signal and the effective second clock input signal;
s233, the second clock generating module 1033 obtains an effective second clock signal according to the effective second enable signal.
The clock switching module 104 obtains an effective output clock signal according to the ineffective first clock signal, the effective second clock signal and the ineffective control signal, and the step S240 specifically includes the following steps:
s241, the clock switching module 104 selects the second clock signal as the output clock signal according to the invalid first clock signal, the valid second clock signal and the invalid control signal.
When the first clock input signal or the first clock signal is abnormal, the flip-flop 102 obtains an effective first enable signal according to an invalid first clock input signal and a control signal which is not changed and still has an effective value, the first clock generation module obtains the effective first clock signal according to the effective first enable signal, but the first clock signal enters the next period, the control signal is changed due to the influence of the first clock input signal, the effective control signal is changed into the invalid control signal, the first clock generation module stops outputting the first clock signal, the invalid control signal enables the second clock generation module to generate the second clock signal, the chip system still has clock signal output, the reliable operation of the chip system is ensured, once the first clock input signal and the first clock signal are abnormal, the first clock generation module outputs the first clock signal and switches to the second clock generation module to output the second clock signal, the first clock signal and the second clock signal are all realized by a simple logic circuit, software intervention is not needed, and the real-time performance of the chip system is improved.
In an embodiment of the present invention, fig. 7 is a schematic structural diagram of a clock control apparatus applied to a system on chip in an embodiment, and referring to fig. 7, the present invention provides an apparatus applied to a system on chip, where the apparatus includes:
a first clock generator 101, configured to obtain a first clock signal according to a first clock input signal;
the flip-flop 102 is configured to obtain a control signal according to the first clock input signal and the first clock signal;
a second clock generator 103, configured to receive the effective second clock input signal and obtain a second clock signal according to the effective second clock input signal and the control signal;
the clock switching module 104 is configured to obtain an output clock signal according to the first clock signal, the second clock signal, and the control signal.
The first clock generator 101 includes a logical or operation module 1011 and a first clock generation module 1012, the logical or operation module 1011 obtains a first enable signal according to the first clock input signal, and the first clock generation module 1012 obtains a first clock signal according to the first enable signal.
The second clock generator 103 includes a logical inversion operation module 1031, a logical and operation module 1032, and a second clock generation module 1033, where the logical inversion operation module 1031 obtains a logical inversion signal according to the control signal, the logical and operation module 1032 obtains a second enable signal according to the logical inversion signal and the second clock input signal, and the second clock generation module 1033 obtains a second clock signal according to the second enable signal.
The invention discloses a device applied to a chip system, which obtains a first clock signal through a first clock generator 101 according to a first clock input signal; obtaining a control signal according to the first clock input signal and the first clock signal through a trigger 102; obtaining a second clock signal by the second clock generator 103 according to the valid second clock input signal and the control signal; and obtaining an output clock signal through the clock switching module 104 according to the first clock signal, the second clock signal and the control signal. The device can provide reliable clock signals for the chip system, monitors the abnormal state of the output of the first clock signal in real time, closes the second clock sending module when the output of the first clock signal is normal, only one clock runs, monitors the abnormality of the input signal of the first clock or the first clock signal, and switches to the second clock generating module 1033 to output the second clock signal in time to ensure the reliable running of the chip system.
The invention discloses a clock control method and a clock control device applied to a chip system, wherein the method comprises the following steps: the switching device can obtain an effective output clock signal according to the effective first clock input signal or the ineffective first clock input signal. Under the condition that the first clock input signal is normal and effective, the switching device keeps the original output clock signal as the clock source of the external circuit; if the first clock input signal is abnormal, the switching device switches the second clock signal in time to serve as an output clock signal, so that the circuit is ensured to keep the original normal operation, and the reliability of the chip clock is ensured.
The device comprises: obtaining a first clock signal according to a first clock input signal by a first clock generator 101; obtaining a control signal according to the first clock input signal and the first clock signal through the trigger 102; obtaining a second clock signal according to the effective second clock input signal and the control signal through the second clock generator 103; and obtaining an output clock signal through the clock switching module 104 according to the first clock signal, the second clock signal and the control signal. The device can provide reliable clock signals for the chip system, monitors the abnormal state of the output of the first clock signal in real time, closes the second clock sending module when the output of the first clock signal is normal, only one clock runs, monitors the abnormality of the input signal of the first clock or the first clock signal, and switches to the second clock generating module 1033 to output the second clock signal in time to ensure the reliable running of the chip system.
The effective first clock signal or the effective second clock signal is used for indicating that the first clock signal or the second clock signal is generated, and the invalid first clock signal or the invalid second clock signal is used for indicating that no first clock signal or no second clock signal is generated; the active first clock input signal, the control signal, the first enable signal, the logic negation signal, and the second enable signal are used to indicate that the signals are at a high level, and the inactive first clock input signal, the control signal, the first enable signal, the logic negation signal, and the second enable signal are used to indicate that the signals are at a low level.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A clock control method applied to a chip system is applied to a switching device, the switching device comprises a first clock generator, a trigger, a second clock generator and a clock switching module, the second clock generator comprises a logical negation operation module, a logical AND operation module and a second clock generation module, and the method is characterized by comprising the following steps:
the switching device obtains an effective output clock signal according to the effective first clock input signal;
the switching device obtains an effective output clock signal according to the ineffective first clock input signal;
wherein the switching device obtains an effective output clock signal according to an effective first clock input signal, comprising: the first clock generator obtains an effective first clock signal according to an effective first clock input signal; the trigger obtains an effective control signal according to an effective first clock input signal and an effective first clock signal; the second clock generator receives a second clock input signal, and the second clock generator obtains an invalid second clock signal according to an effective control signal and the second clock input signal; the clock switching module obtains an effective output clock signal according to the effective first clock signal, the ineffective second clock signal and the effective control signal;
the second clock generator obtains an invalid second clock signal according to the valid control signal and the second clock input signal, and includes: the logic negation operation module obtains an invalid logic negation signal according to the valid control signal; the logic and operation module sends an invalid logic inversion signal to a first input end of the logic and operation module, a second input end of the logic and operation module receives a second clock input signal, and the logic and operation module obtains an invalid second enabling signal according to the invalid logic inversion signal and the valid second clock input signal; and the second clock generation module obtains an invalid second clock signal according to the invalid second enable signal.
2. The method of claim 1, wherein the switching device comprises a first clock generator, a flip-flop, a second clock generator, and a clock switching module, and wherein the switching device derives an active output clock signal from an inactive first clock input signal, comprising:
the first clock generator obtains an invalid first clock signal according to the invalid first clock input signal;
the trigger obtains an invalid control signal according to the invalid first clock input signal and the invalid first clock signal;
the second clock generator receives a second clock input signal, and the second clock generator obtains an effective second clock signal according to an invalid control signal and the second clock input signal;
the clock switching module obtains an effective output clock signal according to the ineffective first clock signal, the effective second clock signal and the ineffective control signal.
3. The method of claim 1, wherein the first clock generator comprises a logical or operation module and a first clock generation module, and wherein deriving the active control signal from the active first clock input signal comprises:
when the first clock input signal is an effective signal, a first input end of the logic or operation module receives the effective first clock input signal, a second input end of the logic or operation module receives a control signal of which an initial value is effective, and the logic or operation module obtains an effective first enable signal according to the effective first clock input signal and the control signal of which the initial value is effective;
the first clock generation module obtains an effective first clock signal according to an effective first enable signal;
the flip-flop derives an effective control signal from the effective first clock input signal and the effective first clock signal.
4. The method of claim 1, wherein the second clock generator derives an inactive second clock signal based on an active control signal and the second clock input signal, comprising:
and the clock switching module selects the first clock signal as an output clock signal according to the effective first clock signal, the ineffective second clock signal and the effective control signal.
5. The method of claim 3, wherein the second clock generator comprises a logical negation operation module, a logical AND operation module, and a second clock generation module, and the flip-flop derives an invalid control signal according to the invalid first clock input signal and the invalid first clock signal, comprising:
when the first clock input signal is an invalid signal, a first input end of the logic or operation module receives the invalid first clock input signal, a second input end of the logic or operation module receives a control signal of which an initial value is valid, the logic or operation module obtains a valid first enable signal according to the invalid first clock input signal and the control signal of which the initial value is valid, the first clock generation module obtains a valid first clock signal according to the valid first enable signal, and the trigger obtains the invalid control signal according to the invalid first clock input signal and the valid first clock signal;
the effective first clock signal enters the next period, the first input end of the logic or operation module receives the ineffective first clock input signal, the second input end of the logic or operation module receives the ineffective control signal, the logic or operation module obtains an ineffective first enable signal according to the ineffective first clock input signal and the ineffective control signal, the first clock generation module obtains an ineffective first clock signal according to the ineffective first enable signal, and the trigger obtains an ineffective control signal according to the ineffective first clock input signal and the ineffective first clock signal.
6. The method of claim 2, wherein the second clock generator derives an active second clock signal based on the inactive control signal and the second clock input signal, comprising:
the logic negation operation module obtains an effective logic negation signal according to the ineffective control signal;
the logic inversion operation module sends an effective logic inversion signal to a first input end of the logic and operation module, a second input end of the logic and operation module receives an effective second clock input signal, and the logic and operation module obtains an effective second enabling signal according to the effective logic inversion signal and the effective second clock input signal;
and the second clock generation module obtains an effective second clock signal according to the effective second enable signal.
7. The method of claim 2, wherein the clock switching module deriving the valid output clock signal according to the invalid first clock signal, the valid second clock signal, and the invalid control signal, comprising:
and the clock switching module selects the second clock signal as an output clock signal according to the invalid first clock signal, the valid second clock signal and the invalid control signal.
8. An apparatus for use in a system-on-chip, the apparatus configured to perform the method of any of claims 1-7.
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