CN210006000U - embedded system hardware reset circuit - Google Patents
embedded system hardware reset circuit Download PDFInfo
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- CN210006000U CN210006000U CN201920625019.3U CN201920625019U CN210006000U CN 210006000 U CN210006000 U CN 210006000U CN 201920625019 U CN201920625019 U CN 201920625019U CN 210006000 U CN210006000 U CN 210006000U
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Abstract
The utility model discloses an embedded system hardware reset circuit, including the master controller, the power manager, peripheral circuits, enable logic circuit, reset control circuit, buffer circuit and with logic circuit, enable logic circuit's input, reset control circuit's input, be connected with logic circuit's third input and the output of master controller, buffer circuit's 0 input is connected with enable logic circuit's output, buffer circuit's second input is connected with reset control circuit's output, buffer circuit's output with logic circuit's second input is connected, be connected with logic circuit's input and power manager's output, be connected with logic circuit's output and the input of master controller, be connected with logic circuit's second output and peripheral circuits's input, the master controller is connected with the power manager both-way electricity, can effectively improve system's stability and reliability.
Description
Technical Field
The utility model relates to a reset control technical field especially relates to kinds of embedded system hardware reset circuit.
Background
With the rapid development of electronic technology, an embedded processor based on an ARM core is widely applied to the fields of automobiles, industry, commerce and the like, when an abnormal condition occurs in software or hardware during the working process of the embedded processor, the embedded processor needs to be reset, so that parts in the whole system or the system are restarted to restore the initial state.
Disclosure of Invention
The embodiment of the utility model provides an aim at provides kinds of embedded system hardware reset circuit, can effectively improve the stability and the reliability of system.
In order to achieve the above object, an embodiment of the present invention provides kinds of embedded system hardware reset circuits, including a master controller, a power manager, a peripheral circuit, an enable logic circuit, a reset control circuit, a buffer circuit, and a logic circuit;
the input end of the enabling logic circuit, the input end of the reset control circuit and the third input end of the and logic circuit are connected with the output end of the master controller;
an th input end of the buffer circuit is connected with the output end of the enabling logic circuit, a second input end of the buffer circuit is connected with the output end of the reset control circuit, and an output end of the buffer circuit is connected with a second input end of the AND logic circuit;
the input end of the and logic circuit is connected with the output end of the power manager, the output end of the and logic circuit is connected with the input end of the master controller, and the second output end of the and logic circuit is connected with the input end of the peripheral circuit;
the main controller is in bidirectional electric connection with the power supply manager.
As a modification of the above scheme, the enable logic circuit includes an enable logic, an th resistor, a second resistor, a third resistor and a th capacitor;
the input end of the enabling logic circuit is connected with the th pin and the second pin of the enabling logic device;
the terminal of the th resistor is connected with the th pin of the enable logic, and the terminal is grounded;
the terminal of the second resistor is connected to the second pin of the enable logic, and the terminal is grounded;
a third pin of the enabling logic device is grounded;
a fourth pin of the enable logic device is connected with an th end of the third resistor and an output end of the enable logic circuit;
the fifth pin of the enable logic is connected with a power supply, the second end of the third resistor and the th end of the th capacitor, and the second end of the th capacitor is grounded.
As an improvement of the above scheme, the buffer circuit includes a buffer, a second capacitor, a third capacitor, and a fourth resistor;
the th pin of the buffer is connected with the th input end of the buffer circuit, and the second pin of the buffer is connected with the second input end of the buffer circuit;
a third pin of the buffer is grounded;
a fourth pin of the buffer is connected with an th end of the fourth resistor, a th end of the third capacitor and an output end of the buffer circuit, and a second end of the third capacitor is grounded;
and a fifth pin of the buffer is connected with a second end of the fourth resistor, a power supply and an th end of the second capacitor, and a second end of the second capacitor is grounded.
As an improvement of the above scheme, the reset control circuit includes a reset controller, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor and a fifth capacitor;
an th end of the eighth resistor is connected with the th pin of the reset controller and the output end of the reset control circuit, and a second end of the eighth resistor is connected with a power supply;
a second pin of the reset controller is grounded;
the end of the seventh resistor is connected with the third pin of the reset controller, and the end of the seventh resistor is grounded;
a fourth pin of the reset controller is connected with an input end of the reset control circuit and an th end of the sixth resistor, and a second end of the sixth resistor is grounded;
and a fifth pin of the reset controller is connected with an th end of the fifth resistor and a th end of the fifth capacitor, a second end of the fifth capacitor is grounded, a end of the fourth capacitor is connected with a second end of the fifth resistor, and the end of the fourth capacitor is grounded.
As a modification of the above, the and logic circuit includes a th logic circuit and a second logic circuit;
a input of the th logic circuit is connected to a input of the and logic circuit, a second input of the th logic circuit is connected to a second input of the and logic circuit, and an output of the th logic circuit is connected to a th output of the and logic circuit;
an input of the second logic circuit is connected to a third input of the AND logic circuit, a second input of the second logic circuit is connected to a second input of the AND logic circuit, and an output of the second logic circuit is connected to a second output of the AND logic circuit.
, the logic circuit includes a logic device, a ninth resistor and a sixth capacitor;
the pin of the logic device is connected to the second input terminal of the logic circuit through the ninth resistor;
the second pin of the logic is connected to the input of the logic circuit;
a third pin of the logic is grounded;
the fourth pin of the logic is connected to the output of the logic circuit;
the fifth pin of the logic is connected to a power supply and the terminal of the sixth capacitor, and the second terminal of the sixth capacitor is grounded.
, the second logic circuit includes a second logic, a tenth resistor, a tenth resistor and a seventh capacitor;
the th pin of the second logic device is connected with the second input end of the second logic circuit through the tenth resistor;
the second pin of the second logic device is connected with the th input end of the second logic circuit;
a third pin of the second logic device is grounded;
a fourth pin of the second logic device is connected with the output end of the second logic circuit through the tenth resistor;
and a fifth pin of the second logic device is connected with a power supply and an th end of the seventh capacitor, and a second end of the seventh capacitor is grounded.
As an improvement of the above scheme, a second input end of the peripheral circuit is connected with an output end of the master controller.
Compared with the prior art, the utility model discloses a kinds of embedded system hardware reset circuit, through embedded system hardware reset circuit include master controller, power manager, peripheral hardware circuit, enable logic circuit, reset control circuit, buffer circuit and with logic circuit, the input of enable logic circuit, the input of reset control circuit, with 2 logic circuit's third input end with the output of master controller is connected, the th input end of buffer circuit with enable logic circuit's output is connected, buffer circuit's second input end with reset control circuit's output is connected, buffer circuit's output with logic circuit's second input end is connected, main control logic circuit's the input end with the output of power manager is connected, with logic circuit's the th output with the input of master controller, logic circuit's second output with the input end of peripheral hardware circuit is connected, the master control circuit with power manager's two-way electricity is connected, when the power manager two-way electricity is connected, when embedded system hardware reset control circuit and reset control circuit is carried out the normal operation, the power manager control circuit is reset control circuit and reset control circuit, the peripheral hardware reset control circuit is carried out through the interval and reset control circuit is carried out, the useful reset control circuit, the reliability is improved through the interval of the embedded system hardware reset control circuit, the peripheral hardware reset control circuit and the peripheral hardware reset control circuit is carried out on the embedded system hardware reset control circuit, the host controller, the stability of the embedded system hardware reset control circuit, the embedded system hardware reset control circuit is carried out, the special control circuit, the inserted control circuit is carried out on the reset control circuit, the host controller is carried out on the reset control circuit, the reset control circuit.
Drawings
Fig. 1 is a schematic structural diagram of kinds of embedded system hardware reset circuits in the embodiment of the present invention;
fig. 2 is a circuit diagram of an embedded system hardware reset circuit according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of , but not all embodiments.
Referring to fig. 1, it is a schematic structural diagram of embedded system hardware reset circuits in the embodiment of the present invention, including a master controller 100, a power manager 200, a peripheral circuit 300, an enable logic circuit 400, a reset control circuit 500, a buffer circuit 600, and an and logic circuit 700;
an input terminal of the enable logic circuit 400, an input terminal of the reset control circuit 500, and a third input terminal of the and logic circuit 700 are connected to an output terminal of the master 100;
an th input terminal of the buffer circuit 600 is connected to the output terminal of the enable logic circuit 400, a second input terminal of the buffer circuit 600 is connected to the output terminal of the reset control circuit 500, and an output terminal of the buffer circuit 600 is connected to a second input terminal of the and logic circuit 700;
the input end of the and logic circuit 700 is connected with the output end of the power manager 200, the output end of the and logic circuit 700 is connected with the input end of the master 100, the second output end of the and logic circuit 700 is connected with the input end of the peripheral circuit 300;
the master 100 is bidirectionally electrically connected to the power manager 200.
It should be noted that, the reset control circuit 500 is configured to generate an external reset signal to reset the master 100, the enable logic circuit 400 is configured to perform a logic and operation on a plurality of enable signals, and the buffer circuit 600 is configured to use the enable output signal generated by the enable logic circuit 400 to control the effectiveness of the reset control circuit 500 for outputting the external reset signal, in this embodiment, the and logic circuit 700 is configured to perform a reset control on the master 100 and the peripheral circuit 300, wherein the and logic circuit 700 includes a logic circuit 701 and a second logic circuit 702, and further the logic circuit 701 provides the reset source for the master 100 from the reset control circuit 500 and the power manager 200, and the second logic circuit 702 provides the reset source for the peripheral circuit 300 from the reset control circuit 500 and the master 100. the power manager 200 is configured to provide power for the embedded system, and is configured to cooperate with the master 100, so that the master 100 can operate in different power modes, and further, when the power manager 200 operates abnormally or enters a specific operating mode, the power manager 200 outputs a power signal, and, for example, when the power management function of the embedded system is required for performing a power-on-time sequence control function of the embedded system 300.
In the normal operation process of the embedded system, timer interrupts are generated at intervals of timing inside the master controller 100, and the reset control circuit 500 timer clear signals are provided through the external port, if the reset control circuit 500 does not receive the clear signal sent by the master controller 100 within the fixed time interval, external reset signals are output.
When the embedded system is in an abnormal operation process, the power manager 200 supplies power to the system and outputs reset signals, the main controller 100 starts the function of the reset control circuit 500 through the enable logic circuit 400 and the buffer circuit 600, the reset control circuit 500 outputs external reset signals, the external reset signal of the reset control circuit 500 and the reset signal output by the power manager 200 perform reset control on the main controller 100 through the logic circuit , and the reset output signal is automatically generated and output after the reset input signal of the main controller 100 is valid, so that the reset output signal of the main controller 100 and the external reset signal of the reset control circuit 500 perform reset control on the peripheral circuit 300 through the logic circuit 700, and the function of the peripheral circuit 300 is that when the main controller 100 is in a reset state, the peripheral circuit 300 can also keep synchronous with the main controller 100, and all parts of the system can be started normally.
Preferably, referring to fig. 2, which is a circuit diagram of the hardware reset circuit of the embedded system in the embodiment of the present invention, the enable logic circuit 400 includes an enable logic U1, a th resistor R1, a second resistor R2, a third resistor R3, and a th capacitor C1;
the input end of the enabling logic circuit 400 is connected with the th pin and the second pin of the enabling logic U1;
the end of the th resistor R1 is connected with the th pin of the enable logic U1, and the end is grounded;
the end of the second resistor R2 is connected with the second pin of the enable logic U1, and the end is grounded;
the third pin of the enable logic U1 is grounded;
a fourth pin of the enable logic U1 is connected to the th terminal of the third resistor R3 and the output terminal of the enable logic circuit 400;
the fifth pin of the enable logic U1 is connected to a power supply, the second terminal of the third resistor R3, and the terminal of the -th capacitor C1, and the second terminal of the -th capacitor C1 is grounded.
It should be noted that, in this embodiment, the enable logic U1 is logic and , and may be sn74ahc1g08dbvr, the th pin and the second pin of the enable logic U1 are input terminals of a two-input and , the third pin is grounded, the fifth pin is connected to a power supply, and the fourth pin is a signal output terminal, the master controller 100 outputs two logic control signals GPIO _ WD _ EN1 and GPIO _ WD _ EN2 to the enable logic U , which are used for enabling control, and further the enable logic U1 performs a logic and operation on the two logic control signals.
Preferably, as shown in fig. 2, the buffer circuit 600 includes a buffer U2, a second capacitor C2, a third capacitor C3, and a fourth resistor R4;
the th pin of the buffer U2 is connected with the th input of the buffer circuit 600, and the second pin of the buffer U2 is connected with the second input of the buffer circuit 600;
a third pin of the buffer U2 is grounded;
a fourth pin of the buffer U2 is connected to the th terminal of the fourth resistor R4, the th terminal of the third capacitor C3, and the output terminal of the buffer circuit 600, and the second terminal of the third capacitor C3 is grounded;
the fifth pin of the buffer U2 is connected to the second terminal of the fourth resistor R4, the power supply, and the terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is grounded.
It should be noted that the buffer U2 may be an sn74lvc1g125dbv, wherein the th pin of the buffer U2 connected to the output terminal of the enable logic circuit 400 is an option card input terminal OE, the second pin connected to the output terminal of the RESET control circuit 500 is an input terminal a, and the fourth pin is an output terminal, further, when the enable output signal (normal logic state output, logic 0, logic 1) input to the th pin is 1, the enable output signal is enabled, the buffer U2 is gated, the external RESET signal input to the second pin is directly transmitted to the output terminal, and the output terminal sends a WD _ RESET _ OUT signal to the and logic circuit to turn on the function of the RESET control circuit 500.
Preferably, as shown in fig. 2, the reset control circuit 500 includes a reset controller U3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, and a fifth capacitor C5;
a terminal of the eighth resistor R8 is connected to the th pin of the reset controller U3 and the output terminal of the reset control circuit 500, and a second terminal of the eighth resistor R8 is connected to a power supply;
a second pin of the reset controller U3 is grounded;
the end of the seventh resistor R7 is connected with the third pin of the reset controller U3, and the end is grounded;
a fourth pin of the reset controller U3 is connected to the input terminal of the reset control circuit 500 and the terminal of the sixth resistor R6, and the second terminal of the sixth resistor R6 is grounded;
the fifth pin of the reset controller U3 is connected to the th end of the fifth resistor R5 and the th end of the fifth capacitor C5, the second end of the fifth capacitor C5 is grounded, the end of the fourth capacitor C4 is connected to the second end of the fifth resistor R5, and the end is grounded.
It should be noted that the reset controller U3 may be CAT824STDI-gt3, where the pin of the reset controller U3 is a low level reset output terminal to output an external reset signal to control the main controller 100 and the peripheral circuit 300 to reset, the third pin is a high level reset output terminal, the fourth pin is an input terminal, the timer reset signal GPIO _ WDI output by the main controller 100 is connected to the input terminal of the reset controller U3, the timer inside the reset controller U3 in a normal operating state overflows times every , the reset controller U3 outputs the external reset signal after the timer overflows, and further, in a state where the enable output signal is valid, if the main controller 100 cannot output the reset signal before the timer in the reset controller U3 overflows, the reset controller U3 outputs the reset signal, and in a case where the reset controller runs, the external reset signal output by the reset U3 causes the main controller 100 to perform a cold reset operation.
The and logic 700 includes a th logic 701 and a second logic 702;
an input of the th logic circuit 701 is connected to the th input of the and logic circuit 700, a second input of the th logic circuit 701 is connected to the second input of the and logic circuit 700, and an output of the th logic circuit 701 is connected to the th output of the and logic circuit 700;
an input of the second logic circuit 702 is coupled to the third input of the AND logic circuit 700, a second input of the second logic circuit 702 is coupled to the second input of the AND logic circuit 700, and an output of the second logic circuit 702 is coupled to the second output of the AND logic circuit 700.
, as shown in FIG. 2, the logic circuit 701 includes a logic U4, a ninth resistor R9 and a sixth capacitor C6;
the th pin of the th logic U4 is connected to the second input terminal of the th logic circuit 701 through the ninth resistor R9;
the second pin of the logic U4 is connected with the input terminal of the logic circuit 701;
the third pin of the logic U4 is grounded;
the fourth pin of the logic U4 is connected with the output end of the logic circuit 701;
the fifth pin of the logic U4 is connected to a power supply and the terminal of the sixth capacitor C6, and the second terminal of the sixth capacitor C6 is grounded.
, as shown in FIG. 2, the second logic circuit 702 includes a second logic unit U5, a tenth resistor R10, a tenth resistor R11 and a seventh capacitor C7;
the th pin of the second logic device U5 is connected to the second input terminal of the second logic circuit 702 through the tenth resistor R10;
a second pin of the second logic U5 is connected to a input of the second logic 702;
a third pin of the second logic device U5 is grounded;
the fourth pin of the second logic U5 is connected to the output of the second logic circuit 702 through the tenth resistor R11;
the fifth pin of the second logic device U5 is connected to a power supply and the th terminal of the seventh capacitor C7, and the second terminal of the seventh capacitor C7 is grounded.
It should be noted that the logic U4 and the second logic U5 are logic and , which may be sn74ahc1g08dbvr, the RESET output of the buffer U2 and the RESET signal PMIC _ RESET output by the power manager 200 are respectively input to the pin and the second pin of the logic U4, the logic U4 output PORz signal is connected to the RESET input pin of the master 100, usually the master 100 has only power-on RESET input pins, but the master 100 may need to respond to multiple power-on RESET input sources, which may be implemented by using the logic circuit 700 as for the purpose of , the RESET of the master 100 is controlled by the RESET controller and the power manager, both of which have the same priority, any generating RESET commands may trigger the RESET of the master 100, similarly, the RESET output of the buffer U2 and the RESET signal output of the CPU _ tout 100 are connected to the second pin rsut 5, and the RESET circuit 100 is initialized by the peripheral initialization process of the peripheral system initialization of the peripheral system according to the second logic circuit 300.
Preferably, as shown in fig. 1, a second input terminal of the peripheral circuit 300 is connected to an output terminal of the master 100.
It should be noted that the master 100 can perform a hot reset operation on the peripheral circuit 300 without restarting the system. When the master 100 is reset, the peripheral circuit 300 is necessarily reset accordingly.
Compared with the prior art, the utility model discloses an embedded system hardware reset circuit, through when the embedded system abnormal operation, power manager is the system power supply and exports reset signal, simultaneously through enabling logic circuit and buffer circuit, main control unit opens reset control circuit's function, and then reset control circuit does not receive the zero clearing signal that the master controller sent in fixed time interval, then output reset signal, and then reset control circuit and power manager through with logic circuit carry out reset control to the master controller, reset control circuit and master controller are through carrying out reset control to peripheral circuit with logic circuit, the utility model discloses a control mode based on master controller, multiple reset sources such as dedicated reset control circuit and power manager, independently carry out reset control to master controller and peripheral circuit, can effectively improve embedded system's stability and reliability.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.
Claims (8)
1, embedded system hardware reset circuits, which are characterized by comprising a main controller, a power manager, a peripheral circuit, an enable logic circuit, a reset control circuit, a buffer circuit and a logic circuit;
the input end of the enabling logic circuit, the input end of the reset control circuit and the third input end of the and logic circuit are connected with the output end of the master controller;
an th input end of the buffer circuit is connected with the output end of the enabling logic circuit, a second input end of the buffer circuit is connected with the output end of the reset control circuit, and an output end of the buffer circuit is connected with a second input end of the AND logic circuit;
the input end of the and logic circuit is connected with the output end of the power manager, the output end of the and logic circuit is connected with the input end of the master controller, and the second output end of the and logic circuit is connected with the input end of the peripheral circuit;
the main controller is in bidirectional electric connection with the power supply manager.
2. The embedded system hardware reset circuit of claim 1 wherein the enable logic circuit comprises an enable logic, an th resistor, a second resistor, a third resistor, and a th capacitor;
the input end of the enabling logic circuit is connected with the th pin and the second pin of the enabling logic device;
the terminal of the th resistor is connected with the th pin of the enable logic, and the terminal is grounded;
the terminal of the second resistor is connected to the second pin of the enable logic, and the terminal is grounded;
a third pin of the enabling logic device is grounded;
a fourth pin of the enable logic device is connected with an th end of the third resistor and an output end of the enable logic circuit;
the fifth pin of the enable logic is connected with a power supply, the second end of the third resistor and the th end of the th capacitor, and the second end of the th capacitor is grounded.
3. The embedded system hardware reset circuit of claim 1, wherein the buffer circuit comprises a buffer, a second capacitor, a third capacitor, and a fourth resistor;
the th pin of the buffer is connected with the th input end of the buffer circuit, and the second pin of the buffer is connected with the second input end of the buffer circuit;
a third pin of the buffer is grounded;
a fourth pin of the buffer is connected with an th end of the fourth resistor, a th end of the third capacitor and an output end of the buffer circuit, and a second end of the third capacitor is grounded;
and a fifth pin of the buffer is connected with a second end of the fourth resistor, a power supply and an th end of the second capacitor, and a second end of the second capacitor is grounded.
4. The embedded system hardware reset circuit of claim 1, wherein the reset control circuit comprises a reset controller, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor, and a fifth capacitor;
an th end of the eighth resistor is connected with the th pin of the reset controller and the output end of the reset control circuit, and a second end of the eighth resistor is connected with a power supply;
a second pin of the reset controller is grounded;
the end of the seventh resistor is connected with the third pin of the reset controller, and the end of the seventh resistor is grounded;
a fourth pin of the reset controller is connected with an input end of the reset control circuit and an th end of the sixth resistor, and a second end of the sixth resistor is grounded;
and a fifth pin of the reset controller is connected with an th end of the fifth resistor and a th end of the fifth capacitor, a second end of the fifth capacitor is grounded, a end of the fourth capacitor is connected with a second end of the fifth resistor, and the end of the fourth capacitor is grounded.
5. The embedded system hardware reset circuit of claim 1 wherein the and logic circuitry includes a th logic circuitry and a second logic circuitry;
a input of the th logic circuit is connected to a input of the and logic circuit, a second input of the th logic circuit is connected to a second input of the and logic circuit, and an output of the th logic circuit is connected to a th output of the and logic circuit;
an input of the second logic circuit is connected to a third input of the AND logic circuit, a second input of the second logic circuit is connected to a second input of the AND logic circuit, and an output of the second logic circuit is connected to a second output of the AND logic circuit.
6. The embedded system hardware reset circuit of claim 5 wherein the logic circuit includes a logic, a ninth resistor, and a sixth capacitor;
the pin of the logic device is connected to the second input terminal of the logic circuit through the ninth resistor;
the second pin of the logic is connected to the input of the logic circuit;
a third pin of the logic is grounded;
the fourth pin of the logic is connected to the output of the logic circuit;
the fifth pin of the logic is connected to a power supply and the terminal of the sixth capacitor, and the second terminal of the sixth capacitor is grounded.
7. The embedded system hardware reset circuit of claim 5 wherein the second logic circuit comprises a second logic, a tenth resistor, a tenth resistor, and a seventh capacitor;
the th pin of the second logic device is connected with the second input end of the second logic circuit through the tenth resistor;
the second pin of the second logic device is connected with the th input end of the second logic circuit;
a third pin of the second logic device is grounded;
a fourth pin of the second logic device is connected with the output end of the second logic circuit through the tenth resistor;
and a fifth pin of the second logic device is connected with a power supply and an th end of the seventh capacitor, and a second end of the seventh capacitor is grounded.
8. The embedded system hardware reset circuit of claim 1, wherein a second input of the peripheral circuit is connected to an output of the master.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920625019.3U CN210006000U (en) | 2019-04-30 | 2019-04-30 | embedded system hardware reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920625019.3U CN210006000U (en) | 2019-04-30 | 2019-04-30 | embedded system hardware reset circuit |
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| CN210006000U true CN210006000U (en) | 2020-01-31 |
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| CN201920625019.3U Active CN210006000U (en) | 2019-04-30 | 2019-04-30 | embedded system hardware reset circuit |
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| CN (1) | CN210006000U (en) |
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