CN203117836U - Clock switching circuit - Google Patents
Clock switching circuit Download PDFInfo
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- CN203117836U CN203117836U CN201220705460.0U CN201220705460U CN203117836U CN 203117836 U CN203117836 U CN 203117836U CN 201220705460 U CN201220705460 U CN 201220705460U CN 203117836 U CN203117836 U CN 203117836U
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Abstract
The utility model discloses a clock switching circuit, comprising a first level trigger, a second level logic circuit and a third level data selector, wherein the first level trigger comprises an odd-even dual-way trigger; the input end of the first level trigger is respectively connected with an original clock signal, a reset signal, a frequency division signal and a frequency division clock signal, and the first level trigger generates an odd-even frequency division signal and inputs the odd-even frequency division signal to the second level logic circuit; the input end of the second level logic circuit is connected with an odd-even selection signal and outputs a delayed frequency division signal under the control of the odd-even selection signal; and the delayed frequency division signal, the original clock signal and the frequency division clock signal are connected with the input end of the third level data selector, and under the control of the delayed frequency division signal, the third level data selector outputs one signal of the original clock signal and the frequency division clock signal. The clock switching circuit disclosed by the utility model has the advantages of simple hardware structure, flexible configuration and stable performance.
Description
Technical field
The utility model belongs to the digital integrated circuit field, especially relates to a kind of carrot-free clock switch circuit.
Background technology
Digital circuit is usually operated at different clock zones.In many cases, these circuit need switch between different clocks.And these clocks are normally got by same clock division, in common clock division circuits, normally finish the selection of last clock by data selector.Though common data selector can be finished the switching to input clock signal, but because the difference of input clock frequency, and select the asynchronous of control signal, be easy in the process of switching, cause distance between the jagged or adjacent hopping edge of clock signal less than the moderate semiperiod.This unsettled clock handoff procedure causes the false triggering event easily, and can influence the stability of circuit.
The utility model content
The technical problems to be solved in the utility model is, at the above-mentioned defective of prior art, provides the clock switch circuit of a kind of simple in structure, stable performance and applying flexible.
For achieving the above object, the adoptable technical scheme of the utility model is:
A kind of clock switch circuit, described clock switch circuit comprise first order trigger, second level logical circuit and third level data selector, and wherein said first order trigger comprises strange, even two-way trigger; The input end of described first order trigger connects original clock signal, reset signal, fractional frequency signal and sub-frequency clock signal respectively, and described first order trigger produces the odd even fractional frequency signal and imports described second level logical circuit; The input end of described second level logical circuit connects odd even and selects signal and select the fractional frequency signal after the output time-delay under the signal controlling in described odd even; Fractional frequency signal after the described time-delay, original clock signal and sub-frequency clock signal are connected the input end of described third level data selector, under the control of the fractional frequency signal after the described time-delay, described third level data selector is selected road signal in the described original clock signal of output and the sub-frequency clock signal.
Preferably, in described clock switch circuit, described third level data selector is the alternative data selection circuit.
Preferably, in described clock switch circuit, described first order trigger is D flip-flop.
Preferably, in described clock switch circuit, when the frequency division multiple greater than 3 the time, described clock switch circuit also is provided with the counter for the effective edge of record number.
Clock switch circuit of the present utility model has that hardware configuration is simple, the advantage of flexible configuration and stable performance.
Will be appreciated that, the feature in the above each side of the utility model can be in scope of the present utility model independent assortment, and be not subjected to the restriction of its order---as long as the technical scheme after the combination drops in the connotation of the present utility model.
Description of drawings
Below in conjunction with drawings and Examples clock switch circuit of the present utility model is described further, in the accompanying drawing:
Fig. 1 is clock transfer process synoptic diagram, and T0 and T1 conversion constantly is respectively no burr conversion and jagged conversion;
Fig. 2 is the building-block of logic of clock switch circuit of the present utility model;
Fig. 3 is the particular circuit configurations figure of clock switch circuit of the present utility model;
Fig. 4 is the clock switching signal sequential chart of clock switch circuit of the present utility model;
Fig. 5 is the even frequency division synoptic diagram of clock switch circuit of the present utility model, is respectively the synoptic diagram of two frequencys multiplication and six frequencys multiplication;
Fig. 6 is the strange frequency division synoptic diagram of clock switch circuit of the present utility model.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the utility model, should understand these embodiments only is used for explanation the utility model and is not used in restriction scope of the present utility model, after reading the utility model, those skilled in the art all falls within the application's claim institute restricted portion to the modification of the various equivalent form of values of the present utility model.
Figure 1 shows that the transfer process synoptic diagram of clock.The clock that the utility model is discussed switches based on following condition: i.e. two-way clock signal, wherein one the tunnel got by another road frequency division, so two paths of signals phase approximation unanimity.Wanting to be implemented between such two-way or multiple signals handoff procedure does not have burr and produce, and its core concept and method are: the hopping edge that requires to switch the selection signal of clock occurs in two paths of signals in the cycle with level.As shown in Figure 1: when consistent as if the two-way clock level, for example from T0 constantly, switch this moment, and clock can not have the burr conversion; On the contrary, when taking place as if the hopping edge of selecting signal, for example from T1 constantly, the level of two paths of signals is inconsistent, and then handoff procedure can produce burr, so namely can influence the stability of circuit.Therefore, the utility model is based on this thought, two kinds of frequency division modes of branch odd even (being respectively negative edge triggering and rising edge triggers) when this conversion regime has guaranteed that two clock levels unanimity is dropped in the hopping edge of selection signal, have so just realized carrot-free transfer process.Following Fig. 2 of concrete circuit structure and shown in Figure 3.
As shown in Figure 2, the utility model adopts three grades of synchronizing circuit cascades.Fractional frequency signal NOTDIV connects the input end of first order circuit (first order trigger), when needs carry out the clock switching, fractional frequency signal NOTDIV changes a level, under the synchronization of clock signals of input triggers, by the two-way trigger odd even fractional frequency signal is carried out assignment respectively, the difference of frequency division multiple during according to real work is divided into two kinds of situations of odd even, under the both of these case, the mode difference that concrete clock switches.After first order circuit (first order trigger) output, enter second level logical circuit, select signal to select by odd even, the signal of output connects the selecting side of final data selector switch, and selects to be output as former clock or frequency-dividing clock.Select this moment signal through time-delay, and guarantee two-way clock signal level unanimity this moment, so the switching that carry out between clock this moment can't produce burr.
Figure 3 shows that physical circuit figure of the present utility model.First order circuit (first order trigger) comprises two triggers of odd even, and original clock signal clk is carried out rising edge triggering and negative edge triggering respectively.Second level logical circuit comprises selecting one of parity signal and door and or door.The alternative data selector of tertiary circuit (data selector) for being used for the clock signal of output is selected can be selected the more data selector of multichannel number in the reality as required.The signal that comprises in this circuit has: reset signal reset, and fractional frequency signal notdiv, original clock signal clk, sub-frequency clock signal divclk, odd even is selected signal evenorodd, and output signal is the carrot-free clock signal outclk of handoff procedure.Sub-frequency clock signal divclk is got by original clock signal clk frequency division, and odd even selects signal to be used for the two-way output of the first order is selected, and selects wherein one tunnel chip selection signal as third level data selector.Specifically introduce first order trigger circuit, first order circuit is divided into the odd even two-way, and the two-way trigger is all to clock signal clk and reset signal RESET sensitivity, but the triggering mode difference of two-way.When circuit is strange frequency division, detect the negative edge of clock signal, when detecting the negative edge of clock signal, judge fractional frequency signal NOTDIV and sub-frequency clock signal DIVCLK, wherein, regulation only could be switched during for low level at sub-frequency clock signal DIVCLK signal, with this understanding, judge the level height of fractional frequency signal NOTDIV signal, this signal is the former clock of high representative output, and this signal is the low output frequency division clock that represents; In like manner, when circuit is even frequency division, detect rising edge of clock signal, when detecting rising edge of clock signal, judge fractional frequency signal NOTDIV and sub-frequency clock signal DIVCLK, wherein, regulation only could be switched during for low level at sub-frequency clock signal DIVCLK, and with this understanding, the level of judgement fractional frequency signal NOTDIV just, this signal is the former clock of high representative output, and this signal is the low output frequency division clock that represents; The assignment of odd even two-way is in full accord, and difference is triggering mode, and strange frequency division triggers negative edge, and even frequency division triggers rising edge, and this determines by the frequency division mode is different.Specifically hereinafter describe in detail.
Known to from Fig. 4, when needs switch clock, fractional frequency signal NOTDIV changes, do not switch clock signal this moment, but when the triggering edge of former clock, this edge will guarantee the same level of two paths of signals simultaneously, and the odd even fractional frequency signal is carried out assignment, select one the tunnel to export to MUX by logical circuit again, finish once complete no burr conversion.In this use is novel, can between the different clock of the consistent frequency of a plurality of phase places, switch, only need in the end to place MUX according to actual demand, because the selection signal of this MUX through time-delay, switches no burr between two paths of signals in the time of can guaranteeing saltus step.
Because the core concept of this application is to require the hopping edge when the two-way clock level is consistent just to carry out switching between clock, therefore, the design's key is to find the hopping edge of specific clk clock, carves conversion at this moment and can make the output clock not have burr.When we are defined in divclk and are low level the hopping edge of clk clock is judged, because more convenient like this.
As shown in Figure 5, if current state is even frequency division, and the frequency division multiple is twice, the frequency that is the divclk signal is half of clk signal, when the divclk signal when low, clk signal rising edge arrives, and module is judged the notdiv signal, if the notdiv signal is zero, namely require frequency division, then trigger is 0 with the notdiv_even assignment, selects through the odd even of second level circuit, owing to be two divided-frequency, the evenorodd signal is selected notdiv_even, export to tertiary circuit, be output as frequency-dividing clock through data selector, and this clk signal and divclk signal constantly is all high level, therefore transfer process does not have the burr generation, and be after detecting the hopping edge of clk to the assignment of notdiv_even and notdiv_odd, therefore this moment, clk was changed to the same level with divclk, therefore can not produce burr.More than be the process of clockwise frequency-dividing clock conversion when former, opposite conversion also is same process, and only notdiv_even is changed to 1.
2 frequency divisions are a special case in the even frequency division, more common higher multiple idol frequency division, this is more more complex, if the frequency division multiple is 4,6,8 .... when waiting, need an extra counter counter, clk rising edge when with this divclk signal being low level is counted, and could carry out assignment to the notdiv_even signal when having only to last rising edge, simultaneously the counter counter is carried out zero clearing.Because the saltus step of divclk ability is for high, if count value also is less than with regard to assignment and can makes transfer process burr occur when having only last rising edge.The assignment of counter Counter is determined that by divide ratio the frequency division multiple is more big, and the number of the required meter of counter counter is more many, required figure place is also more many, but general frequency division multiple can be too not high, and therefore common counter counter only needs 2 to 3 just can be satisfied, and required hardware is also very simple.Namely the T2 in Fig. 5 changes constantly and can produce burr, can not produce burr and transform constantly at T3, T4.
It more than is the detailed process of even frequency division, strange frequency division and even frequency division difference are, strange frequency division has two kinds of situations, and a kind of situation and be not suitable for rising edge and detect wherein, therefore will carry out negative edge to strange frequency division and detect, this also is the reason that first order circuit (first order trigger) will two triggers of branch odd even.
As shown in Figure 6, level height is the opposite three frequency division that either way belongs to just in time, and following a kind of situation therefore strange frequency division will be detected with negative edge, and negative edge detects either way being suitable for when the divclk signal can not detect with rising edge when low, as shown in the figure, when divclk is low level, when detecting first negative edge of clk signal, two-way clock level unanimity, this does not change constantly burr can occur, as in the T5 time trigger.And different with even frequency division is, strange frequency division is to judge that two paths of signals all be just convertible when hanging down, therefore do not need the negative edge of counter counter to count, only need detect first negative edge and just can change, the strange minimum multiple of frequency division is three frequency division, also can detect a negative edge.
More than be the detailed process of clock conversion, what be different from other clock switch circuits is, commutation circuit of the present utility model is switched clock and is carried out a small time-delay, carry out switching between clock to find a specific moment point, to realize carrot-free transfer process, from describe, also can find out this application flexible configuration, hardware is very simple, only need two simply the logic gate of trigger and minute quantity just can realize.
Claims (4)
1. clock switch circuit, it is characterized in that: described clock switch circuit comprises first order trigger, second level logical circuit and third level data selector, wherein said first order trigger comprises strange, even two-way trigger; The input end of this first order trigger connects original clock signal, reset signal, fractional frequency signal and sub-frequency clock signal respectively, and this first order trigger produces the odd even fractional frequency signal and imports described second level logical circuit; The input end of this second level logical circuit connects odd even and selects signal and select the fractional frequency signal after the output time-delay under the signal controlling in described odd even; Fractional frequency signal after this time-delay, original clock signal and sub-frequency clock signal are connected the input end of described third level data selector, under the control of the fractional frequency signal after this time-delay, described third level data selector is selected road signal in the described original clock signal of output and the sub-frequency clock signal.
2. clock switch circuit according to claim 1, it is characterized in that: described third level data selector is the alternative data selection circuit.
3. clock switch circuit according to claim 1 and 2, it is characterized in that: described first order trigger is D flip-flop.
4. clock switch circuit according to claim 1 is characterized in that: when the frequency division multiple greater than 3 the time, described clock switch circuit also is provided with the counter for the effective edge of record number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220705460.0U CN203117836U (en) | 2012-12-19 | 2012-12-19 | Clock switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220705460.0U CN203117836U (en) | 2012-12-19 | 2012-12-19 | Clock switching circuit |
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| CN203117836U true CN203117836U (en) | 2013-08-07 |
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| CN201220705460.0U Expired - Lifetime CN203117836U (en) | 2012-12-19 | 2012-12-19 | Clock switching circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016041278A1 (en) * | 2014-09-16 | 2016-03-24 | 深圳市中兴微电子技术有限公司 | Dynamic clock switching method and apparatus as well as computer readable medium |
| CN105553447A (en) * | 2014-11-03 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Clock switching circuit |
| CN109905106A (en) * | 2019-03-15 | 2019-06-18 | 湖南国科微电子股份有限公司 | A kind of data selection circuit, chip and electronic equipment |
| WO2019114043A1 (en) * | 2017-12-12 | 2019-06-20 | 天津瑞发科半导体技术有限公司 | On-chip reference clock automatic selection circuit |
| CN114518781A (en) * | 2022-01-07 | 2022-05-20 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN118017998A (en) * | 2024-04-08 | 2024-05-10 | 深圳中微电科技有限公司 | Frequency division clock switching circuit without burr and zero time delay |
-
2012
- 2012-12-19 CN CN201220705460.0U patent/CN203117836U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016041278A1 (en) * | 2014-09-16 | 2016-03-24 | 深圳市中兴微电子技术有限公司 | Dynamic clock switching method and apparatus as well as computer readable medium |
| CN105553447A (en) * | 2014-11-03 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Clock switching circuit |
| CN105553447B (en) * | 2014-11-03 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Clock switch circuit |
| WO2019114043A1 (en) * | 2017-12-12 | 2019-06-20 | 天津瑞发科半导体技术有限公司 | On-chip reference clock automatic selection circuit |
| CN109905106A (en) * | 2019-03-15 | 2019-06-18 | 湖南国科微电子股份有限公司 | A kind of data selection circuit, chip and electronic equipment |
| CN109905106B (en) * | 2019-03-15 | 2023-09-26 | 湖南国科微电子股份有限公司 | Data selection circuit, chip and electronic equipment |
| CN114518781A (en) * | 2022-01-07 | 2022-05-20 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN114518781B (en) * | 2022-01-07 | 2024-05-14 | 西安电子科技大学 | Dual-mode adjustable high-precision baud rate clock generator and frequency division method |
| CN118017998A (en) * | 2024-04-08 | 2024-05-10 | 深圳中微电科技有限公司 | Frequency division clock switching circuit without burr and zero time delay |
| CN118017998B (en) * | 2024-04-08 | 2024-06-11 | 深圳中微电科技有限公司 | Frequency division clock switching circuit without burr and zero time delay |
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| C14 | Grant of patent or utility model | ||
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Address after: No.15 Xinghuo Road, Jiangbei new district, Nanjing, Jiangsu Province, 210031 Patentee after: Dongji Technology Co.,Ltd. Address before: No. 23, Wenzhu Road, Huashen Avenue, Yuhua District, Nanjing, Jiangsu 210012 Patentee before: JIANGSU SEUIC TECHNOLOGY Co.,Ltd. |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130807 Effective date of abandoning: 20220317 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20130807 Effective date of abandoning: 20220317 |