CN102487273B - Reset circuit of anti-fuse type FPGA (Field Programmable Gate Array) system - Google Patents
Reset circuit of anti-fuse type FPGA (Field Programmable Gate Array) system Download PDFInfo
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Abstract
The invention belongs to the technical field of a reset circuit, particularly relates to the reset circuit of an anti-fuse type FPGA (Field Programmable Gate Array) system, and aims at providing a circuit which can be reliably reset for the anti-fuse type FPGA system. The reset circuit of the anti-fuse type FPGA system comprises an external reset threshold circuit, a power-on reset signal generating circuit and an asynchronous reset signal generating circuit, wherein the external reset threshold circuit is connected with the asynchronous reset signal generating circuit for supplying an external reset signal for the asynchronous reset signal generating circuit, the power-on reset signal generating circuit is connected with the asynchronous reset signal generating circuit for supplying a power-on reset signal for the asynchronous reset signal generating circuit, and the asynchronous reset signal generating circuit receives the external reset signal and the power-on reset signal so as to generate an asynchronous reset signal. According to the reset circuit for the anti-fuse type FPGA system, disclosed by the invention, the asynchronous reset signal generating circuit is adopted, two stages of BUFFERs, a matching logic or a gate is simultaneously arranged, the competition adventure of an asynchronous reset signal edge and a clock edge is eliminated, and the asynchronous reset of the anti-fuse type FPGA system is realized.
Description
Technical field
The invention belongs to reset circuit technical field, be specifically related to a kind of anti-fuse-type FPGA system reset circuit.
Background technology
In existing FPGA system, the method for designing of reset circuit is in FPGA, asynchronous reset signal to be carried out synchronously, produces synchronous reset signal, and in the time that effective edge of the clock signal of introducing in FPGA system changes, to being reset, signal plays reset response.It should be noted that in the time powering on, it is the effective precondition of synchronous reset that clock source powers on that stable output and FPGA power on and configure Chengdu.The FPGA that general FPGA(produces such as xilinx company) due to the characteristic of device itself, inner GSR signal is automatically pressed designing requirement reset or set all registers and latch in the time that configuration finishes.But for anti-fuse-type FPGA, while powering on, internal register is not configured automatically.This reset circuit is inapplicable to anti-fuse-type FPGA, and is synchronous reset, cannot realize the asynchronous reset that anti-fuse-type FPGA requires.
Summary of the invention
The object of this invention is to provide a kind of anti-fuse-type FPGA system reset circuit of the reliable reset for anti-fuse-type FPGA system.
The present invention is achieved in that
A kind of anti-fuse-type FPGA system reset circuit, it comprises external reset threshold circuit, power-on reset signal generative circuit and asynchronous reset signal generative circuit; Described external reset threshold circuit is connected with asynchronous reset signal generative circuit, and it receives remote control reset signal, removes the shake in remote control reset signal, for asynchronous reset signal generative circuit provides external reset signal; Power-on reset signal generative circuit is connected with asynchronous reset signal generative circuit, and it provides power-on reset signal for asynchronous reset signal generative circuit; Asynchronous reset signal generative circuit receives external reset signal and power-on reset signal, and the burr that the race hazard in filtering external reset signal and power-on reset signal causes generates asynchronous reset signal, and this asynchronous reset signal is synchronously discharged; Described asynchronous reset signal generative circuit, after the burr that the race hazard in filtering external reset signal and power-on reset signal causes, carries out logical AND operation, generates asynchronous reset signal.
External reset threshold circuit as above comprises pull-up resistor, the first build-out resistor, the first matching capacitance, the first reverser, capacitance, the second build-out resistor, the first protection diode and the second protection diode; One end of pull-up resistor is connected with power supply, and the other end is connected with one end of the first build-out resistor and the anode of the first protection diode; The negative terminal of the first protection diode receives remote control reset signal; The other end of the first build-out resistor is connected with one end of the first matching capacitance and the input of the first reverser; The other end ground connection of the first matching capacitance; The output of the first reverser is connected with one end of capacitance; The other end of capacitance is connected with negative terminal, one end of the second build-out resistor and the input of the second reverser of the second protection diode; The positive ending grounding of the other end of the second build-out resistor and the second protection diode; The output of the second reverser is connected with first input end and second input of asynchronous reset signal generative circuit, outwards exports external reset signal.
The resistance of pull-up resistor value 2k Ω as above, the first build-out resistor is that the electric capacity of 10k Ω, the first matching capacitance is 0.47 μ F.
Power-on reset signal generative circuit as above comprises the 3rd build-out resistor, the second matching capacitance, the 3rd reverser and the 4th reverser; One end of the 3rd build-out resistor is connected with power supply, and the other end of the 3rd build-out resistor is connected with one end of the second matching capacitance and the input of the 3rd reverser; The other end ground connection of the second matching capacitance; The output of the 3rd reverser is connected with the input of the 4th reverser; The output of the 4th reverser is connected with the 3rd input and the four-input terminal of asynchronous reset signal generative circuit, outwards exports power-on reset signal.
The resistance of the 3rd build-out resistor as above is that the electric capacity of 750k Ω, the second matching capacitance is 0.47 μ F.
Asynchronous reset signal generative circuit as above comprises a BUFFER, the 2nd BUFFER, the 3rd BUFFER, the 4th BUFFER, the first logic sum gate, the second logic sum gate, logical AND gate, the first d type flip flop and the second d type flip flop;
The first input end of the first logic sum gate is the first input end of asynchronous reset signal generative circuit, and the input of a BUFFER is the second input of asynchronous reset signal generative circuit;
The output of the one BUFFER is connected with the input of the 2nd BUFFER, and the output of the 2nd BUFFER is connected with the second input of the first logic sum gate; The output of the first logic sum gate is connected with the first input end of logical AND gate;
The first input end of the second logic sum gate is the 3rd input of asynchronous reset signal generative circuit, and the input of the 3rd BUFFER is the four-input terminal of asynchronous reset signal generative circuit;
The output of the 3rd BUFFER is connected with the input of the 4th BUFFER; The output of the 4th BUFFER is connected with the second input of the second logic sum gate;
The output of the second logic sum gate is connected with the second input of logical AND gate; The output of logical AND gate is connected with the clear terminal of the first d type flip flop and the clear terminal of the second d type flip flop; The input end of clock receive clock signal of the first d type flip flop, the output of the first d type flip flop is connected with the input of the second d type flip flop; The input end of clock receive clock signal of the second d type flip flop; The output of the second d type flip flop outwards sends asynchronous reset signal.
Asynchronous reset signal generative circuit as above is realized based on FPGA.
The anti-fuse FPGA of asynchronous reset signal generative circuit as above based on being reset realizes.
External reset signal as above is the pulse signal of Low level effective, and the amplitude of said external reset signal is 3.3V or 5V, and pulse duration is greater than 10ms; Power-on reset signal low level width is greater than 25ms.
The invention has the beneficial effects as follows:
The present invention adopts external reset signal threshold circuit, and this circuit adopts capacitor charge and discharge principle, has effectively removed the shake in remote control reset signal.By changing the parameter of circuit, can change the threshold value of this circuit, realize the filtering to different in width dither signal.
The present invention adopts asynchronous reset signal generative circuit, two-stage BUFFER, matching logic or door are set simultaneously, eliminate the race hazard on asynchronous reset signal edge and clock edge, realized the synchronous release of asynchronous reset and the asynchronous reset signal of anti-fuse-type FPGA system.Solve common asynchronous reset signal edge and clock along having in the situation of race hazard, caused the difficult problem that asynchronous reset is invalid.
Accompanying drawing explanation
Fig. 1 is the structure principle chart of a kind of anti-fuse-type FPGA system reset circuit of the present invention;
Fig. 2 is the circuit theory diagrams of a kind of anti-fuse-type FPGA system reset circuit external reset threshold circuit of the present invention;
Fig. 3 is the circuit theory diagrams of a kind of anti-fuse-type FPGA system reset circuit power-on reset signal generative circuit of the present invention;
Fig. 4 is the circuit theory diagrams of a kind of anti-fuse-type FPGA system reset circuit asynchronous reset signal generative circuit of the present invention;
In figure: 2. pull-up resistor, 3. the first protection diode, 4. the first matching capacitance; 5. the first build-out resistor; 6. the first reverser, 7. capacitance, 8. the second build-out resistor, 9. the second protection diode; 10. the second reverser; 11. the one BUFFER, 12. the 2nd BUFFER, 13. first logic sum gates; 14. the 3rd build-out resistors; 15. second matching capacitance, 16. the 3rd reversers, 17. the 4th reversers; 18. the 3rd BUFFER; 19. the 4th BUFFER, 20. second logic sum gates, 21. logical AND gates; 23. first d type flip flops, 24. second d type flip flops.
Embodiment
Below in conjunction with drawings and Examples, the anti-fuse-type FPGA system reset circuit of one of the present invention is introduced:
As shown in Figure 1, a kind of anti-fuse-type FPGA system reset circuit, comprises external reset threshold circuit, power-on reset signal generative circuit and asynchronous reset signal generative circuit.
Described external reset threshold circuit is connected with asynchronous reset signal generative circuit, and it receives remote control reset signal, removes the shake in remote control reset signal, for asynchronous reset signal generative circuit provides external reset signal.Described external reset signal is the pulse signal of Low level effective, and the amplitude of said external reset signal is 3.3V or 5V, and pulse duration is greater than 10ms.
In the present embodiment, for anti-fuse-type FPGA A42MX36, the amplitude of asynchronous reset signal is 5V, and pulse duration is 10ms.External reset threshold circuit comprises pull-up resistor 2, the first build-out resistor 5, the first matching capacitance 4, the first reverser 6, capacitance 7, the second build-out resistor 8, the first protection diode 3 and the second protection diode 9.One end of pull-up resistor 2 is connected with power supply (5V or 3.3V), and the other end is connected with one end of the first build-out resistor 5 and the anode of the first protection diode 3.The negative terminal of the first protection diode 3 receives remote control reset signal.The other end of the first build-out resistor 5 is connected with one end of the first matching capacitance 4 and the input of the first reverser 6.The other end ground connection of the first matching capacitance 4.The output of the first reverser 6 is connected with one end of capacitance 7.The other end of capacitance 7 is connected with negative terminal, one end of the second build-out resistor 8 and the input of the second reverser 10 of the second protection diode 9.The positive ending grounding of the other end of the second build-out resistor 8 and the second protection diode 9.The output of the second reverser 10 is connected with first input end and second input of asynchronous reset signal generative circuit, outwards exports external reset signal.
Described remote control reset signal is open collector output, and normality is not on-state, and level "0" is effective.In the present embodiment, the remote control reset signal duration is greater than 10ms.
External reset signal threshold circuit adopts capacitor charge and discharge principle, and thresholding width depends on the value of pull-up resistor 2, the first build-out resistor 5, the first matching capacitance 4.To need filtering to be less than the burr signal of 6ms, be example by effective reset signal more than 6ms, pull-up resistor 2 value 2k Ω, the first build-out resistor 5 value 10k Ω, the first matching capacitance 4 value 0.47 μ F.In the time occurring that pulse duration is less than the burr of 6ms on remote control reseting signal line, burr is by filtering.In the time that remote control reset signal width is greater than 6ms, remote control reset signal is passed through asynchronous reset signal generative circuit by threshold circuit and is entered FPGA.Guarantee the filtering of burr mistake reset signal and effectively the passing through of normal external reset signal to introducing in circuit by external reset threshold circuit.
Power-on reset signal generative circuit is connected with asynchronous reset signal generative circuit, it provides power-on reset signal for asynchronous reset signal generative circuit, anti-fuse-type FPGA device power-on time is not more than 25ms, and therefore power-on reset signal low level width should be greater than 25ms.In the present embodiment, power-on reset signal low level time is 125ms.Described power-on reset signal generative circuit comprises the 3rd build-out resistor 14, the second matching capacitance 15, the 3rd reverser 16 and the 4th reverser 17.One end of the 3rd build-out resistor 14 is connected with power supply (5V or 3.3V), and the other end of the 3rd build-out resistor 14 is connected with one end of the second matching capacitance 15 and the input of the 3rd reverser 16.The other end ground connection of the second matching capacitance 15.The output of the 3rd reverser 16 is connected with the input of the 4th reverser 17.The output of the 4th reverser 17 is connected with the 3rd input and the four-input terminal of asynchronous reset signal generative circuit, outwards exports power-on reset signal.
Above-mentioned reverser is preferably Schmidt's characteristic reverser.
Power-on reset signal pulse duration is mainly definite by the 3rd build-out resistor 14 and the second matching capacitance 15, and the pass of pulse duration and the 3rd build-out resistor 14 and the second matching capacitance 15 is
v
cCfor the source voltage that the 3rd build-out resistor 14 connects, V is the separation of reverser low level and high level.
Take anti-fuse-type FPGA A42MX36 parameter designing as example, the electrification reset time of design is 125ms, V=1.5V, and the source voltage that build-out resistor connects is 5V, the 3rd build-out resistor 14 is got 750k Ω, the second matching capacitance 15 value 0.47 μ F.
Asynchronous reset signal generative circuit receives external reset signal and power-on reset signal, the burr that race hazard in filtering external reset signal and power-on reset signal causes, then carry out logical AND operation, generate asynchronous reset signal, and this asynchronous reset signal is synchronously discharged.
In the present embodiment, asynchronous reset signal generative circuit comprises a BUFFER11, the 2nd BUFFER12, the 3rd BUFFER18, the 4th BUFFER19, the first logic sum gate 13, the second logic sum gate 20, logical AND gate 21, the first d type flip flop 23, the second d type flip flop 24.
The first input end of the first logic sum gate 13 is the first input end of asynchronous reset signal generative circuit, and the input of a BUFFER11 is the second input of asynchronous reset signal generative circuit.
The output of the one BUFFER11 is connected with the input of the 2nd BUFFER12, and the output of the 2nd BUFFER12 is connected with the second input of the first logic sum gate 13.The output of the first logic sum gate 13 is connected with the first input end of logical AND gate 21.
The first input end of the second logic sum gate 20 is the 3rd input of asynchronous reset signal generative circuit, and the input of the 3rd BUFFER18 is the four-input terminal of asynchronous reset signal generative circuit.
The output of the 3rd BUFFER18 is connected with the input of the 4th BUFFER19.The output of the 4th BUFFER19 is connected with the second input of the second logic sum gate 20.
The output of the second logic sum gate 20 is connected with the second input of logical AND gate 21.The output of logical AND gate 21 is connected with the clear terminal of the first d type flip flop 23 and the clear terminal of the second d type flip flop 24.The input end of clock receive clock signal of the first d type flip flop 23, the output of the first d type flip flop 23 is connected with the input of the second d type flip flop 24.The input end of clock receive clock signal of the second d type flip flop 24.The output of the second d type flip flop 24 outwards sends asynchronous reset signal.
Realize the logic control of two kinds of reset signals based on FPGA by hardware description language, thereby generate the final asynchronous reset signal using of anti-fuse FPGA.Power-on reset signal enters after FPGA, first through 2 grades of BUFFER, generates the time delayed signal of power-on reset signal, i.e. power-on reset signal (B).Power-on reset signal and power-on reset signal (B) carry out or logic generates power-on reset signal (temp); External reset signal enters after FPGA, first through 2 grades of BUFFER, generates the time delayed signal of external reset signal, i.e. external reset signal (B).External reset signal and external reset signal (B) are carried out or logic generates external reset signal (temp).Because BUFFER is the bottom hardware of FPGA, therefore the physics time delay of 2 BUFFER is fixed value, the chances are 6ns, adopts the external reset signal (temp) that generates with upper type and power-on reset signal (temp) effectively to prevent the burr of the ns level causing due to digital circuit race hazard.External reset signal (temp) and power-on reset signal (temp) carry out generating asynchronous reset signal (temp) with logic, asynchronous reset signal (temp) connects the clear terminal of 2 grades of d type flip flops (D1, D2), the system clock of the clock termination FPGA of D1, D2 trigger, the logic VCC of the D input termination FPGA inside of D1 trigger, the output Q of D1 trigger connects the D input of D2 trigger, and the output Q of D2 trigger is the asynchronous reset signal generating.This kind of logic realization the generation of asynchronous reset signal and the synchronous release of asynchronous reset signal of anti-fuse-type FPGA system.Solve common asynchronous reset signal edge and clock along having in the situation of race hazard, caused the difficult problem that asynchronous reset is invalid.In the present embodiment, can on the anti-fuse FPGA being reset, adopt existing techniques in realizing asynchronous reset signal generative circuit.
Claims (9)
1. an anti-fuse-type FPGA system reset circuit, is characterized in that: it comprises external reset threshold circuit, power-on reset signal generative circuit and asynchronous reset signal generative circuit; Described external reset threshold circuit is connected with asynchronous reset signal generative circuit, and it receives remote control reset signal, removes the shake in remote control reset signal, for asynchronous reset signal generative circuit provides external reset signal; Power-on reset signal generative circuit is connected with asynchronous reset signal generative circuit, and it provides power-on reset signal for asynchronous reset signal generative circuit; Asynchronous reset signal generative circuit receives external reset signal and power-on reset signal, and the burr that the race hazard in filtering external reset signal and power-on reset signal causes generates asynchronous reset signal, and this asynchronous reset signal is synchronously discharged; Described asynchronous reset signal generative circuit, after the burr that the race hazard in filtering external reset signal and power-on reset signal causes, carries out logical AND operation, generates asynchronous reset signal.
2. circuit according to claim 1, is characterized in that: described external reset threshold circuit comprises pull-up resistor (2), the first build-out resistor (5), the first matching capacitance (4), the first reverser (6), capacitance (7), the second build-out resistor (8), the first protection diode (3) and the second protection diode (9); One end of pull-up resistor (2) is connected with power supply, and the other end is connected with one end of the first build-out resistor (5) and the anode of the first protection diode (3); The negative terminal of the first protection diode (3) receives remote control reset signal; The other end of the first build-out resistor (5) is connected with one end of the first matching capacitance (4) and the input of the first reverser (6); The other end ground connection of the first matching capacitance (4); The output of the first reverser (6) is connected with one end of capacitance (7); The other end of capacitance (7) is connected with negative terminal, one end of the second build-out resistor (8) and the input of the second reverser (10) of the second protection diode (9); The positive ending grounding of the other end of the second build-out resistor (8) and the second protection diode (9); The output of the second reverser (10) is connected with the first input end of asynchronous reset signal generative circuit and the second input, outwards exports external reset signal.
3. circuit according to claim 2, is characterized in that: described pull-up resistor (2) value 2k Ω, the resistance of the first build-out resistor (5) are that the electric capacity of 10k Ω, the first matching capacitance (4) is 0.47 μ F.
4. circuit according to claim 1, is characterized in that: described power-on reset signal generative circuit comprises the 3rd build-out resistor (14), the second matching capacitance (15), the 3rd reverser (16) and the 4th reverser (17); One end of the 3rd build-out resistor (14) is connected with power supply, and the other end of the 3rd build-out resistor (14) is connected with one end of the second matching capacitance (15) and the input of the 3rd reverser (16); The other end ground connection of the second matching capacitance (15); The output of the 3rd reverser (16) is connected with the input of the 4th reverser (17); The output of the 4th reverser (17) is connected with the 3rd input and the four-input terminal of asynchronous reset signal generative circuit, outwards exports power-on reset signal.
5. circuit according to claim 4, is characterized in that: the resistance of the 3rd described build-out resistor (14) is that the electric capacity of 750k Ω, the second matching capacitance (15) is 0.47 μ F.
6. circuit according to claim 1, is characterized in that: described asynchronous reset signal generative circuit comprises a BUFFER(11), the 2nd BUFFER(12), the 3rd BUFFER(18), the 4th BUFFER(19), the first logic sum gate (13), the second logic sum gate (20), logical AND gate (21), the first d type flip flop (23) and the second d type flip flop (24);
The first input end of the first logic sum gate (13) is the first input end of asynchronous reset signal generative circuit, a BUFFER(11) input be the second input of asynchronous reset signal generative circuit;
The one BUFFER(11) output and the 2nd BUFFER(12) input be connected, the 2nd BUFFER(12) output be connected with the second input of the first logic sum gate (13); The output of the first logic sum gate (13) is connected with the first input end of logical AND gate (21);
The first input end of the second logic sum gate (20) is the 3rd input of asynchronous reset signal generative circuit, the 3rd BUFFER(18) input be the four-input terminal of asynchronous reset signal generative circuit;
The 3rd BUFFER(18) output and the 4th BUFFER(19) input be connected; The 4th BUFFER(19) output be connected with the second input of the second logic sum gate (20);
The output of the second logic sum gate (20) is connected with the second input of logical AND gate (21); The output of logical AND gate (21) is connected with the clear terminal of the first d type flip flop (23) and the clear terminal of the second d type flip flop (24); The input end of clock receive clock signal of the first d type flip flop (23), the output of the first d type flip flop (23) is connected with the input of the second d type flip flop (24); The input end of clock receive clock signal of the second d type flip flop (24); The output of the second d type flip flop (24) outwards sends asynchronous reset signal.
7. circuit according to claim 6, is characterized in that: described asynchronous reset signal generative circuit is realized based on FPGA.
8. circuit according to claim 7, is characterized in that: the anti-fuse FPGA of described asynchronous reset signal generative circuit based on being reset realizes.
9. circuit according to claim 1, is characterized in that: the pulse signal that described external reset signal is Low level effective, and the amplitude of said external reset signal is 3.3V or 5V, pulse duration is greater than 10ms; Power-on reset signal low level width is greater than 25ms.
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| CN103500125B (en) * | 2013-10-10 | 2016-07-06 | 中国科学院上海技术物理研究所 | A kind of radiation-resistant data handling system based on FPGA and method |
| CN103944546A (en) * | 2014-03-28 | 2014-07-23 | 山东华芯半导体有限公司 | Device and method for preventing reset signal inside chip from losing efficacy |
| CN105070311A (en) * | 2015-07-23 | 2015-11-18 | 安徽华东光电技术研究所 | Processing method of multi-signal board level clock domain crossing |
| CN105591637B (en) * | 2015-11-24 | 2018-12-11 | 居水荣 | The module that automatically resets in integrated circuit |
| CN105958977B (en) * | 2016-06-15 | 2022-01-21 | 湖南工业大学 | Narrow pulse filtering method |
| CN106776392A (en) * | 2016-12-14 | 2017-05-31 | 天津光电通信技术有限公司 | A kind of FPGA docks the innovatory algorithm of single-chip microcomputer FSMC interfaces |
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| JP5174515B2 (en) * | 2008-04-09 | 2013-04-03 | 株式会社日立製作所 | Semiconductor integrated circuit device |
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| CN1924758A (en) * | 2005-09-02 | 2007-03-07 | 中兴通讯股份有限公司 | Multi-clock domain system reset circuit |
| CN101299159A (en) * | 2008-07-01 | 2008-11-05 | 深圳市远望谷信息技术股份有限公司 | Clock switch circuit |
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