CN106776392A

CN106776392A - A kind of FPGA docks the innovatory algorithm of single-chip microcomputer FSMC interfaces

Info

Publication number: CN106776392A
Application number: CN201611152784.5A
Authority: CN
Inventors: 李羚梅; 张鹏泉; 汪震; 范玉进; 曹晓冬; 刘政鹏; 苏晓旭; 蒋航
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2016-12-14
Filing date: 2016-12-14
Publication date: 2017-05-31

Abstract

The present invention discloses the innovatory algorithm that a kind of FPGA docks single-chip microcomputer FSMC interfaces, by judging chip selection signal activation manipulation, then judges to read to enable signal and write enable signal, determines concrete operations content.What the present invention was capable of stability and high efficiency carries out data interaction using between STM32 single-chip microcomputer FSMC modules and FPGA, while keeping current mechanism not change, ensure the integrality and correctness of data, the mode for repeating to latch with flag bit, it is to avoid the situation of data hazard occurs.

Description

A kind of FPGA docks the innovatory algorithm of single-chip microcomputer FSMC interfaces

Technical field

The present invention relates to a kind of sequential coupling working solution, more particularly to a kind of FPGA docking single-chip microcomputer FSMC interfaces Innovatory algorithm.

Background technology

FSMC (Flexible Static Memory Controller, variable static storage controller) is STM32 series Single-chip microcomputer uses a kind of new memory expansion technology.There is unique advantage in terms of outside memory expansion, can root Needed according to systematic difference, easily carry out the extension of different type Large Copacity static memory.And FPGA (Field- Programmable Gate Array, field programmable gate array) as a kind of logical device for being capable of flexible programming, needing When carrying out high speed data transfer with STM32 series monolithics, one piece of static memory itself will be usually modeled as STM32 Read-write, so as to complete data interaction between the two.

FSMC interfaces are a kind of quite easy storage operation technologies for STM32 series monolithics, but during its read-write Sequence is limited to the driving clock of single-chip microcomputer itself；Interfaced FPGA device is equally with driving clock strong correlation, it is necessary to precisely SECO come ensure communication in signal/data correctness and stability.But due to STM32 series monolithics and FPGA it Between signal drive the clock to have sizable gap (FPGA signals drive clock be much larger than STM32 series monolithics), then make Into signal race hazard between the two, cause a wherein side normally to obtain data/signal and (be common in and receive data One side).Thus in order to solve the problem, it is necessary to carry out certain sequential coupling work.

The content of the invention

The present invention discloses sequential coupling working solution between a kind of FPGA and STM32 series monolithics.

To achieve these goals, the present invention uses following scheme：

A kind of FPGA docks the innovatory algorithm of single-chip microcomputer FSMC interfaces, including step：

A. single-chip microcomputer operation is waited；

B. the chip selection signal transmitted by the single-chip microcomputer is received；

C. judge with the signal of the chip selection signal it is to read to enable signal or write enable signal；

D. concrete operations are performed；

E. terminate.

Concrete operations are performed wherein described in Step d includes write operation and read operation.

The write operation step includes (step f-i)：

F. judge the write enable signal rising edge, moment latch address bus and data/address bus occur in the rising edge On data；

G. produce and latch index pulse；

H. delayed latch index pulse；

The data of the address bus that i. will be latched into when delay pulse is triggered are saved on corresponding address bus.

The read operation step includes (step j-k)：

J. reading to gather the data on address bus during enable signal is effective；

K. returned in corresponding data to data bus according to the address bus for receiving.

The chip selection signal, the reading enable signal and the write enable signal is Low level effective.

Preferably, the FPGA is the Spartan6 XC6SLX100 chips of Xilinx companies；The FSMC is ST companies STM32F429 chips.

All steps also need to set the foundation of the address setup time of the FSMC, low address hold time and data before starting Time.

Preferably, the address setup time of the FSMC is 8HLK, and the low address hold time is 16HLCK, the data Setup time is 8HCLK.

What the present invention was capable of stability and high efficiency carries out data interaction using between STM32 single-chip microcomputer FSMC modules and FPGA, While keeping current mechanism not change, it is ensured that the integrality and correctness of data, the mode for repeating to latch with flag bit, The situation of data hazard is avoided to occur.

Brief description of the drawings

Fig. 1 is FPGA of the present invention and FSMC chain graphs.

Fig. 2 is FPGA ends time sequence control logic flow chart of the present invention.

Fig. 3 is FSCM read operations timing diagram of the present invention.

Fig. 4 is FSCM write operations timing diagram of the present invention.

Specific embodiment

The specific embodiment of the invention is described in detail below in conjunction with the accompanying drawings.

As shown in figure 1, FPGA is electrically connected by the soft core RAM of itself with the FSMC of STM32 series monolithics.NE#, NOE#, NWE# are respectively the chip selection signal of FSMC control signals, read to enable signal, write enable signal, are Low level effective. ADDR represents the address signal given by FSMC, and DATA is the two-way data communication signal of FPGA soft core RAM and FSMC interaction. INT is the interrupt notification signal that FPGA is returned to ARM.The read-write operation of core construction RAM soft to FPGA inside is initiated by ARM, NE# signals represent that ARM have selected FPGA as control object when enabling effective, and with NOE#/NWE# signals represent current simultaneously The operation for carrying out is to read RAM operations, still writes RAM operations.When operation is operated to read RAM, NE#, NOE# holding enable effective State, NEW# is kept enabling disarmed state, while the address for reading data will be needed to be placed in ADDR buses, now FPGA is received Data are delivered in DATA buses after above-mentioned signal, then is taken away by ARM.When operation is operated to write RAM, NE#, NWE# signal are protected Enable effective status is held, NOW# signals keep enabling disarmed state, while data and its corresponding address of write-in will be needed Deliver to respectively in DATA, ADDR bus, FPGA is stored data into corresponding address after above-mentioned signal is received.Interrupt signal The function both sides of INT can freely reach an agreement on, both can be as reading RAM notification signals, it is also possible to used as writing RAM notification signals.

STM32 series monolithics with FPGA when being docked, it should be ensured that when its FSMC addresses setup time, address keep Between be arranged to appropriate parameter with data setup time, it is ensured that itself and NE#, NWE#, NOE# signal keep synchronous, to meet The sequential standard of FPGA, otherwise influences whether that FPGA latches the data in ADDR buses and DATA buses.(as used Xilinx public affairs The STM32F429 chips of the Spartan6 XC6SLX100 chips docking ST companies of department, recommendation setting FSMC addresses setup time, Low address hold time and data setup time are respectively 8HLK, 16HLCK, 8HCLK) and FPGA ends because its drive clock rate compared with Height, then then can control the time of its coherent signal by logic control, provided by the present invention to be what FPGA ends to be used Sequential logic.Logical flow chart is as shown in Figure 2.

Fig. 3 and Fig. 4 are respectively the read-write operation timing diagram of FSMC, and wherein A represents address bus ADDR, and it is total that D represents data Line DATA, NEx, NOE, NWE represent chip selection signal NE# respectively, read to enable signal NOE# and write enable signal NWE#, NBL generation Literary name section selection signal.

During read operation, chip selection signal NE# is dragged down first, notifies that FPGA device has been chosen, while total in ADDR Address is set up on line, then drags down NOE# signals to represent that current carry out is read operation.FPGA is then waited for be sent to data In DATA buses, in the rising edge of NOE# signals, DATA data are latched.

During write operation, chip selection signal NE# is dragged down first, notifies that FPGA device has been chosen, while total in ADDR Address is set up on line, then drags down NWE# signals to represent that current carry out is write operation.Then setting up data, to be sent to DATA total On line.FPGA should latch DATA data in the rising edge of NWE# signals.

Except above-described embodiment uses ARM chip STM32F429, other ARM chips such as STM32F103, STM32F207 etc. Also can be used the program to enter line interface to dock.

The beneficial effects of the invention are as follows being capable of being carried out using between STM32 single-chip microcomputer FSMC modules and FPGA for stability and high efficiency Data interaction, while keeping current mechanism not change, it is ensured that the integrality and correctness of data, is repeated with flag bit The mode of latch, it is to avoid the situation of data hazard occurs.

Specific embodiment of the invention has been described in detail above, but the content is only preferable implementation of the invention Example, it is impossible to be considered as limiting practical range of the invention.All impartial changes made according to the present patent application scope, improve or Combination etc., all should still belong within patent covering scope of the invention.

Claims

1. a kind of FPGA docks the innovatory algorithm of single-chip microcomputer FSMC interfaces, including step：

A. single-chip microcomputer operation is waited；

D. concrete operations are performed；

E. terminate.

2. innovatory algorithm according to claim 1, it is characterised in that：Described in Step d perform concrete operations include write operation or Read operation.

3. innovatory algorithm according to claim 2, it is characterised in that：The write operation step includes：

F. judge the write enable signal rising edge, occur in moment latch address bus and data/address bus in the rising edge Data；

G. produce and latch index pulse；

H. delayed latch index pulse；

4. innovatory algorithm according to claim 2, it is characterised in that：The read operation step includes：

5. according to any innovatory algorithms of claim 1-4, it is characterised in that：The chip selection signal, the reading enable signal Low level effective is with the write enable signal.

6. innovatory algorithm according to claim 1, it is characterised in that：The FPGA is Xilinx companies Spartan6XC6SLX100 chips；The FSMC is the STM32F429 chips of ST companies.

7. innovatory algorithm according to claim 6, it is characterised in that：When needing the address that the FSMC is set to set up before operation Between, low address hold time and data setup time.

8. innovatory algorithm according to claim 7, it is characterised in that：The address setup time of the FSMC is 8HLK, described Low address hold time is 16HLCK, and the data setup time is 8HCLK.