CN105163108A - Image data dummy source - Google Patents
Image data dummy source Download PDFInfo
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- CN105163108A CN105163108A CN201510468718.8A CN201510468718A CN105163108A CN 105163108 A CN105163108 A CN 105163108A CN 201510468718 A CN201510468718 A CN 201510468718A CN 105163108 A CN105163108 A CN 105163108A
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Abstract
The invention discloses an image data dummy source including a communication interface unit, a storage unit, a buffer memory unit, an output interface unit, a control unit and a power source management unit. The image data dummy source can simulate practical working modes and working procedures of a camera, can generate analog image data and enabling signals for frame synchronization and line synchronization, can change image data freely and has advantages of being small in size, convenient to carry, simple and convenient to use, stable and reliable in working performance and the like. The image data dummy source has a good application prospect and can be applied to any equipment with Channel Link bus interface and has good hardware compatibility. At the same time, the invention also discloses a communication method of the image data dummy source.
Description
Technical field
The present invention relates to a kind of view data dummy source, belong to communication technical field.
Background technology
In the development process of some specialized camera, need the image capture device that development is corresponding, and can normally work in order to test pattern collecting device, need to build complete signal link and debug.Now input as image according to real camera, extra risk can be brought to camera, especially when camera development cost is higher, extra cost can be increased.Therefore develop special view data dummy source and carry out the course of work of analogue camera and data output interface is necessary.
The means of camera image dummy source common at present mainly contain: use hardware circuit image data generating, or in controller storage inside piece image data.
Inventor finds in the process of research, and this camera image dummy source exists following shortcoming: data mode is single, can not realize exporting the signals such as the view data of multiframe and frame synchronization, row be synchronous, and view data not easily changes flexibly.
Summary of the invention
The object of the invention is to design a kind of view data dummy source, this view data dummy source uses real camera to input as image to avoid when image capture device is tested, the mode of operation of actual camera, workflow can be simulated, produce the signals such as view data and frame synchronization, row be synchronous, and view data flexibly changing can be made.
Object of the present invention carrys out specific implementation by the following technical programs:
A kind of view data dummy source, comprises communications interface unit, memory cell, buffer unit, output interface unit and control unit;
Described communications interface unit comprises control command communication interface and rewriting data communication interface;
Described control command communication interface is connected with host computer, adopts full duplex serial communication mode, in order to receive order and the auxiliary data of host computer transmission, and passback response instruction;
Described rewriting data communication interface, one end is received on computer by USB line, and the other end is then connected with control unit, realizes receiving the view data that will write from computer,
Described control unit is connected with described memory cell by bus, thus stores in view data write memory unit;
Described buffer unit is connected with described control unit by bus, in order to caching image data, solves memory cell read-out speed and the unmatched problem of data output rate;
The input of described output interface unit is connected with the output of described control unit, according to data transmit-receive agreement, adopt the high speed LVDS interface output image data of TIA/EIA-644 standard, parallel data can be converted into ChannelLink serial data, and output clock, send to the display terminal be connected with described output interface unit output to show.
Further, also Power Management Unit is comprised;
Described Power Management Unit is connected with described communications interface unit, memory cell, buffer unit, output interface unit and control unit respectively, for powering to view data dummy source.
Further, described control unit adopts FPGA (Field-ProgrammableGateArray, field programmable gate array), for realize the drived control of chip in described view data dummy source, the unloading of data, mode of operation and workflow judgement control.
Further, between described memory cell and buffer unit, also comprise data concatenation module, for splicing and the packing of view data.
Further, described buffer unit is SRAM (StaticRAM, static random access memory) chip;
Memory cell is FLASH memory unit;
Described control unit adopts FPGA module to realize, and realizes FLASH memory, the drived control of sram chip, the unloading of data, and the judgement realizing mode of operation and workflow controls.
Further, described control unit comprises: rewriting data communication interface modules, ping-pong buffer module, FLASH driver module, mode selection module, data concatenation module, SRAM driver module, control command communication interface modules and ChannelLink interface module;
Input and the USB of described rewriting data communication interface modules turn serial port bridging chip and are connected, and the output of described rewriting data communication interface modules is connected with the input of ping-pong buffer module; The output of described ping-pong buffer module is connected with FLASH driver module; Described FLASH driver module is connected with FLASH memory; The output of described FLASH driver module splices with data and is connected, and the output of described data concatenation module drives with SRAM and is connected, and described SRAM driver module is connected with sram chip;
The input of described mode selection module is connected with wire jumper, and the output of described mode selection module is connected with the input of FLASH driver module;
Control command communication interface modules is connected with driven in series/receiver;
ChannelLink interface module is connected with serial transmitter.
Further, after control command communication interface receives the command frame of controller transmission, confirm the machine address code, calculation check code, if address code and check code are correctly, replys, is in accepting state after response; If address code or check code incorrect; do not reply, also do not perform any operation.
Further, described output interface unit can produce corresponding frame synchronization and the synchronous enabled signal of row.
The invention also discloses a kind of communication means of view data dummy source, the method comprises the following steps:
S1: after system electrification, performs corresponding workflow according to the mode of operation of wire jumper Determines memory cell;
S2: memory cell is under the pattern read, the control command that wait-receiving mode host computer is sent also performs corresponding operation;
Further, step S1 specifically comprises:
S11: wire jumper state is WriteMode, unlocks memory cell, erase operation;
After unblock, erasure completion, transmit completion signal to computer, computer sends view data by serial ports, and is written in memory cell by view data under the control of the control unit;
S12: wire jumper state is reading mode, then read view data from memory cell.
Further, step S2 specifically comprises:
S21: the instruction that wait-receiving mode host computer is sent;
S22: receive beginning photographing instruction, reads the view data stored in a memory cell, after buffer unit buffer memory, passes to display terminal by output interface unit by schedule speed;
S23: receive stopping photographing instruction, after the view data of present frame being sent, stopping reading view data, returns step S21;
S24: receive gain and arrange instruction, then move to left view data after one and export, and again receives after gain arranges instruction, get back to initial condition and continue output image;
S25: if receive control unit reset instruction, return step S21.
View data dummy source provided by the invention, real camera can be substituted be used for carrying out image capture device debugging, there is following characteristics: mode of operation and workflow that actual camera can be simulated, produce the signals such as view data and frame synchronization, row be synchronous, view data can be changed flexibly, and have volume little, be easy to carry, simple and convenient, stable work in work, the advantage such as reliable.This image simulation source is with a wide range of applications, and may be used for adopting in the equipment of ChannelLink bus interface, has good hardware compatibility.
Accompanying drawing explanation
According to drawings and embodiments the present invention is described in further detail below.
Fig. 1 is the schematic diagram of view data dummy source of the present invention;
Fig. 2 is the structured flowchart of view data dummy source of the present invention;
Fig. 3 is the structured flowchart of control unit of the present invention;
Fig. 4 is the workflow diagram of view data dummy source of the present invention.
Embodiment
Be described in detail embodiments of the invention below in conjunction with accompanying drawing, wherein, Fig. 1 is the work connection diagram of view data dummy source system of the present invention.Computer adopts general AccessPort software, and view data is sent to view data dummy source from computer.Image simulation source receives view data and is stored in self FLASH memory.Host computer sends order and auxiliary data to view data dummy source.Image simulation source after sram cache, exports display terminal display by ChannelLink interface the view data self stored.
Fig. 2 is the structured flowchart of view data dummy source of the present invention.View data dummy source take FPGA as core, operationally FPGA first the view data be pre-stored in flash storage is read in and buffer memory in sram, then by ChannelLink interface output image; The view data that FPGA can also be sent by serial ports receiving computer also carries out programming again to flash storage; The communication interface of view data dummy source and host computer adopts the serial communication mode of full duplex LVDS level.
Fig. 3 is the structured flowchart of control unit of the present invention.Control unit comprises: model selection, control command communication interface, rewriting data communication interface, FLASH driving, SRAM driving, the splicing of ChannelLink interface, ping-pong buffer, data.Control unit drives the device such as FLASH memory, SRAM memory, and carries out process output according to agreement to data.In addition, FPGA also achieves the work such as data buffer storage process, data splicing.
Fig. 4 is the workflow diagram of view data dummy source of the present invention.Control mode of operation and the workflow in image digital simulation source rationally and effectively.
Embodiment one
A kind of view data dummy source, comprises communications interface unit, memory cell, buffer unit, output interface unit and control unit;
Described communications interface unit comprises control command communication interface and rewriting data communication interface;
Described control command communication interface is connected with host computer, adopts full duplex serial communication mode, can receive order and the auxiliary data of host computer transmission, and passback response instruction;
Concrete, described control command communication interface is connected with host computer, adopts the serial communication mode of full duplex LVDS level, LVDS signal is converted to Transistor-Transistor Logic level signal, can receive order and the auxiliary data of host computer transmission, and passback response instruction.
Described rewriting data communication interface, one end is received on computer by USB line, the other end is then connected with control unit, realize receiving the view data that will write from computer, view data is write in FLASH memory, the view data that FLASH memory unit is sent for storing computer.The baud rate of rewriting data communication interface can select corresponding baud rate, according to actual needs as 115200bps.
Described control unit is connected with described memory cell by bus, thus stores in view data write memory unit;
Described buffer unit is connected with described control unit by bus, in order to caching image data, solves memory cell read-out speed and the unmatched problem of data output rate;
The input of described output interface unit is connected with the output of described control unit, according to data transmit-receive agreement, adopt the high speed LVDS interface output image data of TIA/EIA-644 standard, parallel data can be converted into ChannelLink serial data, and output clock, send to the display terminal be connected with described output interface unit output to show.
Further, also Power Management Unit is comprised;
Described Power Management Unit is connected with described communications interface unit, memory cell, buffer unit, output interface unit and control unit respectively, for powering to view data dummy source.
Further, described control unit adopts FPGA (Field-ProgrammableGateArray, field programmable gate array), for realize the drived control of chip in described view data dummy source, the unloading of data, mode of operation and workflow judgement control.
Further, between described memory cell and buffer unit, also comprise data concatenation module, for splicing and the packing of view data.
Further, described buffer unit is SRAM (StaticRAM, static random access memory) chip;
Memory cell is FLASH memory unit;
Described control unit adopts FPGA module to realize, and realizes FLASH memory, the drived control of sram chip, the unloading of data, and the judgement realizing mode of operation and workflow controls.
Further, described control unit comprises: rewriting data communication interface modules, ping-pong buffer module, FLASH driver module, mode selection module, data concatenation module, SRAM driver module, control command communication interface modules and ChannelLink interface module;
Input and the USB of described rewriting data communication interface modules turn serial port bridging chip and are connected, and the output of described rewriting data communication interface modules is connected with the input of ping-pong buffer module; The output of described ping-pong buffer module is connected with FLASH driver module; Described FLASH driver module is connected with FLASH memory; The output of described FLASH driver module splices with data and is connected, and the output of described data concatenation module drives with SRAM and is connected, and described SRAM driver module is connected with sram chip;
The input of described mode selection module is connected with wire jumper, and the output of described mode selection module is connected with the input of FLASH driver module;
Control command communication interface modules is connected with driven in series/receiver;
ChannelLink interface module is connected with serial transmitter.
Further, after control command communication interface receives the command frame of controller transmission, confirm the machine address code, calculation check code, if address code and check code are correctly, replys, is in accepting state after response; If address code or check code incorrect; do not reply, also do not perform any operation.
Further, described output interface unit can produce corresponding frame synchronization and the synchronous enabled signal of row.
Embodiment two:
The invention also discloses a kind of communication means of view data dummy source, the method comprises the following steps:
S1: after system electrification, performs corresponding workflow according to the mode of operation of wire jumper Determines memory cell;
Before system electrification, also comprise: connect host computer, image simulation source and computer.
S2: memory cell is under the pattern read, the control command that wait-receiving mode host computer is sent also performs corresponding operation;
Close view data dummy source.
Further, step S1 specifically comprises:
S11: wire jumper state is WriteMode, unlocks memory cell, erase operation;
After unblock, erasure completion, transmit completion signal to computer, computer sends view data by serial ports, and is written in memory cell by view data under the control of the control unit;
S12: wire jumper state is reading mode, then read view data from memory cell.
Further, step S2 specifically comprises:
S21: the instruction that wait-receiving mode host computer is sent;
S22: receive beginning photographing instruction, reads the view data stored in a memory cell, after buffer unit buffer memory, passes to display terminal by output interface unit by schedule speed;
S23: receive stopping photographing instruction, after the view data of present frame being sent, stopping reading view data, returns step S21;
S24: receive gain and arrange instruction, then move to left view data after one and export, and again receives after gain arranges instruction, get back to initial condition and continue output image;
S25: if receive control unit reset instruction, return step S21.
The actuating equipment of the method in employing the present embodiment two can adopt the view data dummy source in embodiment one, and concrete structure is no longer repeated.
View data dummy source provided by the invention, real camera can be substituted be used for carrying out image capture device debugging, there is following characteristics: mode of operation and workflow that actual camera can be simulated, produce the signals such as view data and frame synchronization, row be synchronous, view data can be changed flexibly, and have volume little, be easy to carry, simple and convenient, stable work in work, the advantage such as reliable.This image simulation source is with a wide range of applications, and may be used for adopting in the equipment of ChannelLink bus interface, has good hardware compatibility.
Claims (10)
1. a view data dummy source, is characterized in that, comprises communications interface unit, memory cell, buffer unit, output interface unit and control unit;
Described communications interface unit comprises control command communication interface and rewriting data communication interface;
Described control command communication interface is connected with host computer, in order to receive order and the auxiliary data of host computer transmission, and passback response instruction;
Described rewriting data communication interface, one end is received on computer by USB line, and the other end is then connected with control unit, realizes receiving the view data that will write from computer,
Described control unit is connected with described memory cell by bus, stores in view data write memory unit;
Described buffer unit is connected with described control unit, in order to caching image data by bus;
The input of described output interface unit is connected with the output of described control unit, according to data transmit-receive agreement, adopt the high speed LVDS interface output image data of TIA/EIA-644 standard, parallel data is converted into ChannelLink serial data, and output clock, send to the display terminal be connected with described output interface unit output to show.
2. view data dummy source as claimed in claim 1, is characterized in that, also comprise Power Management Unit;
Described Power Management Unit is connected with described communications interface unit, memory cell, buffer unit, output interface unit and control unit respectively, for powering to view data dummy source.
3. view data dummy source as claimed in claim 1, it is characterized in that, described control unit adopts FPGA (Field-ProgrammableGateArray, field programmable gate array), for realize the drived control of chip in described view data dummy source, the unloading of data, mode of operation and workflow judgement control.
4. view data dummy source as claimed in claim 1, is characterized in that, also comprise data concatenation module between described memory cell and buffer unit, for splicing and the packing of view data.
5. view data dummy source as claimed in claim 1, it is characterized in that, described buffer unit is SRAM (StaticRAM, static random access memory) chip;
Memory cell is FLASH memory unit;
Described control unit adopts FPGA module to realize, and realizes FLASH memory, the drived control of sram chip, the unloading of data, and the judgement realizing mode of operation and workflow controls.
6. the view data dummy source as described in claim 1-5 any one claim, it is characterized in that, described control unit comprises: rewriting data communication interface modules, ping-pong buffer module, FLASH driver module, mode selection module, data concatenation module, SRAM driver module, control command communication interface modules and ChannelLink interface module;
Input and the USB of described rewriting data communication interface modules turn serial port bridging chip and are connected, and the output of described rewriting data communication interface modules is connected with the input of ping-pong buffer module; The output of described ping-pong buffer module is connected with FLASH driver module; Described FLASH driver module is connected with FLASH memory; The output of described FLASH driver module splices with data and is connected, and the output of described data concatenation module drives with SRAM and is connected, and described SRAM driver module is connected with sram chip;
The input of described mode selection module is connected with wire jumper, and the output of described mode selection module is connected with the input of FLASH driver module;
Control command communication interface modules is connected with driven in series/receiver;
ChannelLink interface module is connected with serial transmitter.
7. view data dummy source as claimed in claim 1, is characterized in that, after control command communication interface receives the command frame of controller transmission, confirm the machine address code, calculation check code, if address code and check code are correctly, replys, is in accepting state after response; If address code or check code incorrect; do not reply, also do not perform any operation.
8. a communication means for view data dummy source, is characterized in that, comprises the following steps:
S1: after system electrification, performs corresponding workflow according to the mode of operation of wire jumper Determines memory cell;
S2: memory cell is under the pattern read, the control command that wait-receiving mode host computer is sent also performs corresponding operation.
9. method as claimed in claim 8, it is characterized in that, step S1 specifically comprises:
S11: wire jumper state is WriteMode, unlocks memory cell, erase operation;
After unblock, erasure completion, transmit completion signal to computer, computer sends view data by serial ports, and is written in memory cell by view data under the control of the control unit;
S12: wire jumper state is reading mode, then read view data from memory cell.
10. method as claimed in claim 8, it is characterized in that, step S2 specifically comprises:
S21: the instruction that wait-receiving mode host computer is sent;
S22: receive beginning photographing instruction, reads the view data stored in a memory cell, after buffer unit buffer memory, passes to display terminal by output interface unit by schedule speed;
S23: receive stopping photographing instruction, after the view data of present frame being sent, stopping reading view data, returns step S21;
S24: receive gain and arrange instruction, then move to left view data after one and export, and again receives after gain arranges instruction, get back to initial condition and continue output image;
S25: if receive control unit reset instruction, return step S21.
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| CN201510468718.8A CN105163108A (en) | 2015-08-03 | 2015-08-03 | Image data dummy source |
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| CN105704543A (en) * | 2016-01-26 | 2016-06-22 | 武汉精测电子技术股份有限公司 | A portable picture signal source and a control method thereof |
| CN106885956A (en) * | 2016-12-28 | 2017-06-23 | 中国科学院长春光学精密机械与物理研究所 | Aircraft pod test simulation source device |
| CN110868559A (en) * | 2019-11-26 | 2020-03-06 | 中国电子科技集团公司第五十四研究所 | Camera Link image signal generating device and method |
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Application publication date: 20151216 |