CN103747197A - High-speed digital video storage system - Google Patents
High-speed digital video storage system Download PDFInfo
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- CN103747197A CN103747197A CN201310676992.5A CN201310676992A CN103747197A CN 103747197 A CN103747197 A CN 103747197A CN 201310676992 A CN201310676992 A CN 201310676992A CN 103747197 A CN103747197 A CN 103747197A
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Abstract
The invention provides a high-speed digital video storage system. The system comprises an interface unit, a comprehensive processing unit, storage units, a mother board and a power supply. A Cameralink camera outputs a digital image. The interface unit converts LVDS serial data into parallel data. When the comprehensive processing unit receives a recording instruction of a main control computer, the interface unit outputs the data to the storage units through the mother board. The storage units write image data record to a FLASH chip array. The high-speed digital video storage system is fast in speed, digital recording for various cameras can be realized by modifying few codes, and recording time and capacity can be selected based on needs.
Description
Technical field
The present invention relates to a kind of high-speed figure Video Storage System, be specifically related to a kind of high frame frequency digital picture that can export different types of cameralink digital camera and realize real non-destructive record, and synchronous recording is worked as frame synchronization information.
Background technology
High frame frequency camera is mainly used in the record test of using at a high speed with high-speed object collision process, such as rocket launching, aircraft takeoffs and landings, vehicle impact testing etc., in these trials, it is particularly important that the real time record of test data seems, traditional film type high-speed camera is from frame frequency speed or resolution all cannot meet current instructions for use.But along with the frame frequency of high frame frequency digital camera improves constantly, the data volume of the digital picture of output is also increasing, to the memory bandwidth of digital storage, also requires more and more higher.
The output interface of most high-speed camera digital picture all adopts standard cameralink, and camerlink interface is divided into three kinds of pattern full mode, medium mode and base mode.
The shortcoming of prior art: 1. speed is slow, memory bandwidth is low; 2. can only store a kind of camerlink camera; 3. the bandwidth of storage system and capacity are fixed, and cannot reasonably adjust according to actual user demand, cause the waste of system resource; 4. memory device and camera distance are far away, need to carry out the conversion of camerlink signal, cause equipment cable complicated, and are easily subject to signal interference.
Summary of the invention
The present invention, in order to solve the problem in background technology, provides a kind of high-speed figure Video Storage System.
Technical scheme of the present invention is:
A high-speed figure Video Storage System, its special character is:
Described high-speed figure Video Storage System comprises interface unit, integrated treatment unit, memory cell, motherboard and power supply;
Described interface unit comprises Cameralink interface chip, a FPGA, bus driver and power management chip;
Described integrated treatment unit comprises master cpu and the 2nd FPGA;
Described memory cell comprises at least one storing sub-units, and each storing sub-units comprises the 3rd FPGA, SRAM and FLASH chip array;
Outside Cameralink video camera is connected with a FPGA by Cameralink interface chip, and a FPGA is connected with motherboard by bus driver;
Master cpu is connected with external network, and master cpu is connected with motherboard by the 2nd FPGA;
The 3rd FPGA is connected with motherboard, and SRAM is connected with the 3rd FPGA respectively with FLASH chip array;
Described power supply is that Cameralink interface chip, a FPGA, bus driver, the 2nd FPGA, master cpu, the 3rd FPGA, SRAM and FLASH chip array are powered by power management chip.
Preferably, the maximum quantity of said memory cells is 5, and each memory cell comprises 2 storing sub-units, and the mode with streamline between each storing sub-units is worked.
Preferably, the quantity of Cameralink interface chip is 1-3.
Preferably, the quantity of above-mentioned SRAM is 2-3.
Preferably, a FLASH chip array comprises 8 or 10 FLASH chips, and the read-write operation of FLASH array is parallel work-flow.
Preferably, above-mentioned master cpu is chip TMS320DM6467.
Preferably, above-mentioned FLASH chip adopts K9WBG08U0M chip.
Preferably, an above-mentioned FPGA, the 2nd FPGA and the 3rd FPGA all adopt chip EP2S30F672I4N.
Preferably, above-mentioned bus driver adopts chip SN74LVTH16245.
Preferably, above-mentioned SRAM selects chip id T71T75602S133BGI.
Advantage of the present invention is:
1) storage speed is fast, and the highest memory bandwidth can reach 930MB/s;
2) by revising a small amount of code, just can realize the digital record to various camerlink cameras, and the time of record and capacity can select the quantity of memory plane according to using needs, make system there is best cost performance;
4) this memory device is directly connected with camera, connects near distance, only has a netting twine to be connected with outside, and whole system is simple in structure, and system reliability is high;
5) there is automatic diagnostic function.
Accompanying drawing explanation
Fig. 1 high-speed figure image storage system theory diagram;
Fig. 2 storage system external wiring diagram of the present invention;
Fig. 3 interface unit theory diagram;
Fig. 4 integrated treatment unit theory structure block diagram;
Fig. 5 memory cell theory structure block diagram;
Fig. 6 system controlling software flow chart.
Embodiment
High-speed figure Video Storage System adopts modular project organization, and as shown in Figure 1, high-speed figure Video Storage System comprises interface unit, integrated treatment unit, memory cell, motherboard and power supply to theory diagram;
As Fig. 3, interface unit comprises Cameralink interface chip (DS90CR288AMTD), a FPGA(EP2S30F672I4N), bus driver (SN74LVTH16245) and power management chip; Outside Cameralink video camera is connected with a FPGA by Cameralink interface chip, and a FPGA is connected with motherboard by bus driver.
As Fig. 4, integrated treatment unit comprises master cpu (TMS320DM6467T) and the 2nd FPGA; Master cpu is connected with external network, and master cpu is connected with motherboard by the 2nd FPGA;
As Fig. 5, memory cell comprises at least one storing sub-units, and each storing sub-units comprises the 3rd FPGA, SRAM and FLASH chip array; The 3rd FPGA is connected with motherboard, and SRAM is connected with the 3rd FPGA respectively with FLASH chip array;
Power supply is that Cameralink interface chip, a FPGA, bus driver, the 2nd FPGA, master cpu, the 3rd FPGA, SRAM and FLASH chip array are powered by power management chip.
10MHZ ± and 1HZ ± be register system external synchronization signal, during by B code, system provides.
Memory device external interface of the present invention is simple, and Fig. 2 is storage system external wiring diagram.Memory device of the present invention is directly connected with camera, connects near distance, only has a netting twine to be connected with outside, and whole system is simple in structure, and system reliability is high.
Below for each several part structure is elaborated.
Interface unit receives the LVDS differential signal of video camera output, after Cameralink interface chip (DS90CR288AMTD) decoding, parallel data is delivered to a FPGA, and data are outputed to motherboard through bus driver.For the image of different digital video camera output, only simply need to revise the software in a FPGA of interface unit, can meet memory requirement; Preferably, Cameralink interface chip is 3, can support the digital picture of full mode, medium mode and tri-kinds of forms of base mode of cameralink interface, meets the memory requirement of all cameralink video cameras.
Reception and the forwarding of master control order is mainly responsible in integrated treatment unit, receives main control computer instruction, realizes and the function such as records, stops, downloading, wipe; Receive the synchronous recording data of image; Real-time monitoring system recording status, shows and records residual capacity and time; Possesses fault self-diagnosis function; While downloading image, the data of memory cell are packaged into fixing bag, with crossing gigabit networking, upload the data to main control computer.
Master cpu is TMS320DM6467 unit, its inner integrated ARM9 kernel, adopt the embedded OS of linux, the drivings such as gigabit Ethernet, serial ports, EMIF that it is inner integrated, greatly shorten the development time of integrated treatment unit, and each equipment in system has been carried out to unified management, improved the overall performance of system, alleviated the design burden of hardware, and made the continuity of system research and development good.The inner integrated EMAC controller of DM6467, only need to extend out ethernet physical layer chip can realize gigabit Ethernet communication.
The FPGA of unit is mainly in charge of command transfer and the transfer of data between internal interface, command transfer all adopts coded format, avoided IO transmission may should be burr that shake produces and the risk of the trigger command that leads to errors, improved the reliability of system, transfer of data adopts 80 bit data bus, has improved the transmission bandwidth of system.
Memory cell comprises at least one storing sub-units, and each storing sub-units comprises the 3rd FPGA, SRAM and FLASH chip array; As can be seen from Figure 1 the present invention has 5 memory cell, every memory cell comprises 2 storing sub-units, during system works, 10 storing sub-units form the mode of operation of streamline with the memory bandwidth of raising system, can meet under the condition of memory bandwidth according to the instructions for use of Practical Project in addition, reducing the number of memory cells of system, with the hardware cost of control system, and now software portion needs to revise.Single storing sub-units capacity is 80GB, and system heap(ed) capacity is 400G, and along with the development of flash technology, the capacity of native system can expand to the capacity of TB.
Every the 3rd FPGA controls the read-write of 1 group of FLASH, when the 3rd FPGA receives after the data of interface unit, first data is deposited in SRAM, and then writes FLASH array.3 SRAM are responsible for the data buffer storage of 10 FLASH, and 3 SRAM form the data bit width of 80bit.SRAM selects IDT71T75602S133BGI, the synchronous SRAM that this chip is 512K * 36, and speed is 133MHZ.
FLASH adopts NANDFLASH, and in memory cell, the most complicated most crucial operation is the operation to NANDFLASH.NANDFLASH itself has the shortcoming that the bandwidth of writing is low, needs effective control logic reasonable in design to overcome these inherent defects.For writing the shortcoming that bandwidth is low, system adopts the way of parallel work-flow and pile line operation to improve bandwidth.FLASH adopts K9WBG08U0M, and its I/O bit wide is 8bit, separately has 6 control signals.In each storing sub-units, comprise 10 FLASH, every I/O bit wide is 8bit, with this, forms the data bit width of 80bit.In the control signal of NANDFLASH, R/B is owing to adopting open collector output, thus can line with.The R/B signal of one group of NAND is connected together and be pulled to power supply by a resistance.For guaranteeing driving force, other control signals adopt a form of two of driving to be provided by the 3rd FPGA, realize thus the Parallel Design of NANDFLASH interface.
Interface unit, control board, memory cell are all inserted on motherboard, and motherboard provides the signal between each board to connect, and for all the other each plates provide power supply, motherboard only provides 5V power supply.In order to realize the unitized management of interface, the unified circuit board connector SFM of samtec company and the connector of TFM series of adopting of connector of motherboard, specification is double 100 cores and 40 cores, spacing is 1.27mm, long 66.68mm and the 28.58mm, wide 5.72mm of being respectively.
Between interface unit, integrated treatment unit, memory cell, adopt FPGA as interface management chip, transfer of data is used self-defined parallel bus, and the transmission of order adopts coded format, prevents false triggering.
The present invention can real time record digital picture and the synchronizing information of image, after having recorded, by gigabit networking, downloads to control computer.The capacity of storage system can be adjusted according to actual user demand.
The workflow of native system is as follows: Cameralink video camera output digital image, interface unit is converted to parallel data by the LVDS serial data of Cameralink interface output, when integrated treatment unit receives after the recording instruction of main control computer, interface unit outputs to memory cell by motherboard by data, and memory cell writes FLASH array by Imagery Data Recording.Communication in system between each board all realizes by self-defined bus, and interface is controlled and to be completed by each FPGA, and main control computer is by gigabit Ethernet and integrated treatment unit communication, complete image record, wipe, the function such as download.System possesses memory address memory function, supports discontinuous stored record, after having recorded, can select to download image.When master control issues record order, the initial address of integrated treatment unit record storage system, every record one two field picture, the counting unit of integrated treatment unit adds 1, after receiving and ceasing and desisting order, the amount of images of the initial address of this record, end address, this record is recorded in the FLASH of integrated treatment unit, simultaneously by these data upload to main control computer, by main control computer, show recording status, can realize the memory function of memory address and select download image function.
The image of system real-time storage is downloaded by gigabit networking afterwards, by main control computer, realizes synthesizing image.The data of storing in memory cell are standards, and main control computer, according to actual image size, will save as the bmp form of standard after image packing.
The high-speed camera of MC1362 model of take is example, and under its maximum picture, frame frequency is 504fps@1280*1024, adopts the camerlink full pattern output of 8*10, and pixel clock is 75MHz, and pixel depth is 8bit.The data volume that this video camera is exported under the highest frame frequency is 630MB/s.
The TMS320DM6467 exploitation of register system main control software based on davinci, development platform ARM+linux installs Red Hat (SuSE) Linux OS on host, has set up the development mode of " host---Target Board ".Target Board operation system and system software, the exploitation of the recompile kernel of Target Board operating system used, driver and application program and debugging complete by host, download to target machine move on host after the program cross compile of editing by Ethernet interface.
On the basis of the kit that the uboot of system, linux-kernel, file-system provide at TI, carry out cutting and transplanting obtains.The driving of system and application program have been developed under linux environment.
Fig. 6 is the software flow pattern of integrated treatment unit, after system powers on, cpu sequentially loads uboot, linux-kernel, file-system and device drives, then the system initialization network port and procotol, GPIO interrupt, diagnose state of memory cells, then system enters program major cycle, inquire-receive main control computer instruction in major cycle, cpu resolves main control computer instruction, concrete instruction is issued to the FPGA of integrated treatment unit, the FPGA of this FPGA comport interface unit and memory cell realizes each command function.
In recording instruction, the interrupt signal of system is the picture frame signal of video camera output, interrupts rising edge and triggers, in interruption, receive that main control computer sends when two field picture synchronizing information, after a frame image data is transmitted, by the additional data receiving and image composite traces.
In download instruction, integrated treatment unit receives view data and the additional information of memory cell, and by its packing of data according to fixed size, according to Transmission Control Protocol, upload to main control computer, then by main control computer, these data are encapsulated according to the image size of video camera output.
In erasing instruction, memory cell receives after instruction, wipes the data of storing on FLASH array, after all FLASH have wiped, gives integrated treatment unit return state, and notice master control erasing instruction completes.
Claims (10)
1. a high-speed figure Video Storage System, is characterized in that:
Described high-speed figure Video Storage System comprises interface unit, integrated treatment unit, memory cell, motherboard and power supply;
Described interface unit comprises Cameralink interface chip, a FPGA, bus driver and power management chip;
Described integrated treatment unit comprises master cpu and the 2nd FPGA;
Described memory cell comprises at least one storing sub-units, and each storing sub-units comprises the 3rd FPGA, SRAM and FLASH chip array;
Outside Cameralink video camera is connected with a FPGA by Cameralink interface chip, and a FPGA is connected with motherboard by bus driver;
Master cpu is connected with external network, and master cpu is connected with motherboard by the 2nd FPGA;
The 3rd FPGA is connected with motherboard, and SRAM is connected with the 3rd FPGA respectively with FLASH chip array;
Described power supply is that Cameralink interface chip, a FPGA, bus driver, the 2nd FPGA, master cpu, the 3rd FPGA, SRAM and FLASH chip array are powered by power management chip.
2. high-speed figure Video Storage System according to claim 1, is characterized in that: the maximum quantity of described memory cell is 5, and each memory cell comprises 2 storing sub-units, and the mode with streamline between each storing sub-units is worked.
3. high-speed figure Video Storage System according to claim 1 and 2, is characterized in that: the quantity of Cameralink interface chip is 1-3.
4. high-speed figure Video Storage System according to claim 3, is characterized in that: the quantity of described SRAM is 2-3.
5. high-speed figure Video Storage System according to claim 4, is characterized in that: a FLASH chip array comprises 8 or 10 FLASH chips, and the read-write operation of FLASH array is parallel work-flow.
6. high-speed figure Video Storage System according to claim 5, is characterized in that: described master cpu is chip TMS320DM6467.
7. high-speed figure Video Storage System according to claim 6, is characterized in that: described FLASH chip adopts K9WBG08U0M chip.
8. high-speed figure Video Storage System according to claim 7, is characterized in that: a described FPGA, the 2nd FPGA and the 3rd FPGA all adopt chip EP2S30F672I4N.
9. high-speed figure Video Storage System according to claim 8, is characterized in that: described bus driver adopts chip SN74LVTH16245.
10. high-speed figure Video Storage System according to claim 9, is characterized in that: described SRAM selects chip id T71T75602S133BGI.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107370924A (en) * | 2017-07-18 | 2017-11-21 | 西安电子科技大学 | Image capturing system |
| CN107580174A (en) * | 2017-07-18 | 2018-01-12 | 西安电子科技大学 | Multi-function data acquisition card |
| CN108243185A (en) * | 2017-12-21 | 2018-07-03 | 中国科学院西安光学精密机械研究所 | Scientific grade CCD gigabit Ethernet communication system and method based on AX88180 |
| CN108417233A (en) * | 2017-02-09 | 2018-08-17 | 爱思开海力士有限公司 | Storage device and its write-in and read method and storage system |
| CN109142379A (en) * | 2018-09-19 | 2019-01-04 | 武汉意普科技有限责任公司 | SOC embedded machine vision equipment based on FPGA |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1642452A1 (en) * | 2003-03-03 | 2006-04-05 | KEYMED (MEDICAL & INDUSTRIAL EQUIPMENT) LIMITED | High-speed digital video camera system and controller therefor |
| CN101710256A (en) * | 2009-07-06 | 2010-05-19 | 中国科学院长春光学精密机械与物理研究所 | High speed image data acquisition and processing card based on Camera Link interface |
| CN102098562A (en) * | 2010-12-17 | 2011-06-15 | 中国科学院长春光学精密机械与物理研究所 | Device for lossless recording, storing and playing back high-speed images in real time without loss |
| CN103246754A (en) * | 2013-04-22 | 2013-08-14 | 中国科学院长春光学精密机械与物理研究所 | High-speed digital signal acquiring and storing system |
-
2013
- 2013-12-11 CN CN201310676992.5A patent/CN103747197A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1642452A1 (en) * | 2003-03-03 | 2006-04-05 | KEYMED (MEDICAL & INDUSTRIAL EQUIPMENT) LIMITED | High-speed digital video camera system and controller therefor |
| CN101710256A (en) * | 2009-07-06 | 2010-05-19 | 中国科学院长春光学精密机械与物理研究所 | High speed image data acquisition and processing card based on Camera Link interface |
| CN102098562A (en) * | 2010-12-17 | 2011-06-15 | 中国科学院长春光学精密机械与物理研究所 | Device for lossless recording, storing and playing back high-speed images in real time without loss |
| CN103246754A (en) * | 2013-04-22 | 2013-08-14 | 中国科学院长春光学精密机械与物理研究所 | High-speed digital signal acquiring and storing system |
Non-Patent Citations (1)
| Title |
|---|
| 吴萌: "一种高速、大容量图像存储系统设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417233A (en) * | 2017-02-09 | 2018-08-17 | 爱思开海力士有限公司 | Storage device and its write-in and read method and storage system |
| CN108417233B (en) * | 2017-02-09 | 2021-12-07 | 爱思开海力士有限公司 | Storage device, writing and reading method thereof, and storage system |
| CN107370924A (en) * | 2017-07-18 | 2017-11-21 | 西安电子科技大学 | Image capturing system |
| CN107580174A (en) * | 2017-07-18 | 2018-01-12 | 西安电子科技大学 | Multi-function data acquisition card |
| CN107370924B (en) * | 2017-07-18 | 2020-06-19 | 西安电子科技大学 | Image acquisition system |
| CN108243185A (en) * | 2017-12-21 | 2018-07-03 | 中国科学院西安光学精密机械研究所 | Scientific grade CCD gigabit Ethernet communication system and method based on AX88180 |
| CN108243185B (en) * | 2017-12-21 | 2020-05-12 | 中国科学院西安光学精密机械研究所 | Scientific grade CCD gigabit Ethernet communication system and method based on AX88180 |
| CN109142379A (en) * | 2018-09-19 | 2019-01-04 | 武汉意普科技有限责任公司 | SOC embedded machine vision equipment based on FPGA |
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