CN108243185A - Scientific grade CCD gigabit Ethernet communication system and method based on AX88180 - Google Patents
Scientific grade CCD gigabit Ethernet communication system and method based on AX88180 Download PDFInfo
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- CN108243185A CN108243185A CN201711396715.3A CN201711396715A CN108243185A CN 108243185 A CN108243185 A CN 108243185A CN 201711396715 A CN201711396715 A CN 201711396715A CN 108243185 A CN108243185 A CN 108243185A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
- H04L65/10—Architectures or entities
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The present invention relates to a kind of scientific grade CCD gigabit Ethernet communication systems and method based on AX88180, solve the problems such as 100,000,000 networks in conventional images Transmission system will appear communication blocking or even collapse, cause equipment the image collected loss of data.System includes network communications circuits plate and FPGA board；FPGA board includes fpga chip, eeprom chip and SDRAM chips, and fpga chip is connect with eeprom chip according to IIC agreements, and SDRAM chips connect the storage for carrying out data with fpga chip；Network communications circuits plate includes 45 interface of sequentially connected MAC layer chip, PHY layer chip and RJ, and MAC layer chip is AX88180, and PHY layer chip is 88E1111；The data of fpga chip acquisition are transferred to MAC layer chip and PHY layer chip, and PC host computers are transferred to through 45 interfaces of RJ；Fpga chip includes netinit module, package unpacks module, network protocol module, command analysis module, controls scheduler module, EEPROM parameter access modules, and the present invention also provides a kind of methods that the communication of scientific grade CCD gigabit Ethernet is realized based on above system.
Description
Technical field
The present invention relates to image high-speed transfers and control system field, and in particular to a kind of Scientific Grade based on AX88180
CCD gigabit Ethernets communication system and method, which controls AX88180 chips and PHY layer chip by FPGA, real
Existing gigabit Ethernet communication, and in the communication plan of FPGA internal operation communication protocols.
Background technology
In scientific research, usually under poor light condition object is observed and quantitative analysis, need Gao Ling at this time
Sensitivity, low noise, high linearity and Larger Dynamic range instrument and equipment carry out the acquisition process of image data, and image data
It can timely, be accurately transferred in PC host computers after acquisition, the practicability, reliable of image capture device will be directly related to
Property and image data index.In addition, some observation conditions can even damage observation people member, image is needed to adopt at this time
Collection equipment can be transmitted picture signal at a distance.
At present, it is mostly to be carried out by Camera link and USB interface for the image capture device of scientific research purposes
Data transmission and control, for example, PI Corp. PIXIS series cameras using USB2.0 interfaces, the biography of the image capture device
Defeated rate is relatively low, it is difficult to realize that PC host computers control more image capture devices simultaneously, and transmission range is shorter, can not realize
At a distance, it is more difficult to realize one-to-many control.
With the development of Embedded Ethernet Technology, more and more mini-plants will realize picture number by network interface
According to high speed, remote transmission, and a PC host computer easy to implement controls multiple images collecting device by network, if these
The image collected data are transferred to PC host computers by image capture device, it may be desirable to the network of a more high speed, very much
Occasion, 100,000,000 networks will appear communication blocking or even collapse, cause equipment the image collected loss of data, can cause very
Serious loss.
Invention content
Present invention aim to address 100,000,000 networks in conventional images Transmission system will appear communication blocking or even collapse,
The problems such as causing equipment the image collected loss of data provides a kind of scientific grade CCD gigabit Ethernet based on AX88180 and leads to
Believe system and method, which can realize that scientific grade CCD is interconnected with PC host computers by gigabit networking, can be by Scientific Grade
CCD the image collected high speed data transfer can realize the control command reception to PC host computers, order solution to PC host computers
Analysis, command process, order passback, and can realize UDP, the procotols such as ARP, ICMP (realizing ping functions), and hair can be passed through
Heartbeat packet is sent to check whether network blocks, makes respective handling.
The technical scheme is that：
A kind of scientific grade CCD gigabit Ethernet communication system based on AX88180, including network communications circuits plate and at least
One piece of FPGA board；The FPGA board includes fpga chip, eeprom chip and SDRAM chips, the fpga chip
It is connect with eeprom chip according to IIC agreements, the SDRAM chips connect the storage for carrying out data with fpga chip；The net
Network communication board includes sequentially connected MAC layer chip, PHY layer chip and RJ-45 interfaces, and the MAC layer chip is
AX88180, the PHY layer chip are 88E1111；The data of fpga chip acquisition are transferred to MAC layer chip and PHY layer chip,
PC host computers are transferred to through RJ-45 interfaces；The fpga chip inner function module includes netinit module, package unpacks
Module, network protocol module, command analysis module, control scheduler module, EEPROM parameter access modules；The control scheduling mould
Block unpacks module, network protocol module, command analysis module and EEPROM parameters and accesses with netinit module, package respectively
Module connect, be responsible for coordinate modules boot sequence and data transfer away to, after electrification reset, control scheduler module from
Parameter information is read in EEPROM parameter access modules, and is allocated to netinit module, starts netinit mould later
Block, the netinit module are connect with MAC layer chip, PHY layer chip, and function is configuration MAC layer chip, configuration PHY
Layer chip, startup send and receive submodule；The network protocol module carries out the processing of procotol, the procotol packet
Include ICMP agreements and ARP protocol；The network protocol module is connected with netinit module, be responsible for processing ARP protocol and
The data packet of ICMP agreements；The package unpacks module and is connected with netinit module, and packaged image data is sent,
The command analysis module is connected with netinit module, is responsible for the transmitting-receiving parsing of order, the command analysis module can be with
Order is parsed, order is distinguished and each order is returned into PC host computers one winding of formation.
Further, the netinit module include reset_mac modules, 88e1111_phy_initial modules,
Ax88180_mac_config modules, rec_pack modules, send_pack modules；The reset_mac modules are realized to MAC
The read-write of layer chip register and the register setting default initial values to MAC layer chip；The 88e1111_phy_
Initial modules realize PHY layer chip register read-write, and confirm the network hardware connection media type and PHY layer,
The type of MAC-layer interface；The ax88180_mac_config modules are configured according to the link state that PHY layer chip detects
MAC layer chip register, while negotiate the working method at both ends；The ax88180_mac_config modules complete MAC Address
Configuration, determine the type of received data packet, and open the transmitting-receiving flow control function of MAC layer chip；The rec_pack moulds
Block is directed toward the variation of the register RXCURT and RXBOUND of order caching by inquiry to receive data, and from the number of reception
According to MAC Address, the IP address that PC host computers are obtained in packet；The send_pack modules are sent by configuration register TX_CMD
Data, and send different configurations for the data packet to be sent of different length.
Further, the package unpacks module and is packaged image data according to udp protocol, including unpack module and
UDP package modules.
Further, the package unpacking module includes two block RAM ping-pong buffer modules, and ping-pong structure is used to cache number
According to synchronous to carry out package processing.
Further, the length of each UDP package modules data packet is 1074 bytes.
Meanwhile the present invention also provides a kind of method that the communication of scientific grade CCD gigabit Ethernet is realized based on above system,
Include the following steps：
1) it powers on, into netinit state；
2) in netinit state, the working condition of PHY layer chip and MAC layer chip is configured；
3) enter and intercept state；
4) connection is established；After determining that PC host computers send " connection ", with remembeing IP address and the MAC of the PC host computers
Location is deposited into the corresponding position of EEPROM, and order then is returned to PC host computers；What if other PC host computers were sent out sets
If putting order, passback " refusal order " data packet；
5) " acquisition " order of PC host computers is received, starts the image data of Image Acquisition front-end collection being transferred to PC
Host computer；When receiving configuration order of the PC host computers to Image Acquisition front end, then configuration order is sent after image output
It gives Image Acquisition front end corresponding chip, configuration information is stored into corresponding position in EEPROM, and the order is returned；When
When receiving " passive transmission " order of PC host computers, the image newly to arrive is first passed in SDRAM chips, is not sent actively, only
Have when host computers provide " transmission ", image just starts to transmit；When PC host computers send ON- and OFF- command, system, which reenters, to be intercepted
State waits for new PC host computers to connect.
Further, it further includes step 6) fpga chip and sent heartbeat packet to PC host computers every 15 seconds, if network-like
State is normal, and PC host computers reply rapidly confirmation packet, if it exceeds 2s does not receive confirmation packet yet, then fpga chip sends the heart again
Packet is jumped, if not receiving confirmation packet yet, then it is assumed that network blockage into state is intercepted, does not retransmit image data.
Further, step 3) is specially：If what is received is procotol, it is determined that is which kind of procotol, such as
Fruit is ARP protocol, then by the MAC Address of system and IP address deposit ARP data packets, is sent to PC host computers, and record PC
The MAC Address and IP address of host computer enter intercept state later；If ICMP agreements, then corresponding reply will be replied
Packet, later enter intercept state, return to corresponding udp protocol, check data packet length whether the command packet with agreement
Equal length, and check whether there is order flag bit in data packet；If it is determined that being order, then enter parsing link, and will
Order returns to PC host computers, is otherwise considered as not being order, without any processing, and keeps the state of intercepting.
Further, the working condition of the PHY layer chip and MAC layer chip includes determining network connecting media, network
Operating rate, MAC Address, setting transmitting-receiving flow control, initialization receiving module, sending module.
Further, the configuration order includes time for exposure, AD gains, AD or Time delay.
Advantages of the present invention is：
1. it is of the invention using gigabit network MAC layer chip AX88180 and kilomega network PHY layer chip 88E1111 as communication infrastructure,
By FPGA as control chip, and communication protocol is realized inside FPGA, the functions such as control scheduling, and then realize complete thousand
Mbit ethernet communicates, its main feature is that communication speed is high, it is reliable and stable, 100,000,000 nets are compared, communication bandwidth increasing is more than ten times larger, avoids
100 m ethernet can cause communication speed by CSMA/CD (carrier sense/collision detection) during the increase of network communication data amount
Decline, cause communication blocking, the problem of data cannot send out and be capped, cause loss of data, gigabit Ethernet communicate then by
In communication speed height, and this problem is well solved.
2. the present invention is no CPU design, only by hardware description language verilog, netinit, network association are realized
View, for data packet with unpacking, all links such as processing order, control scheduling have saved use cost, without being externally embedded to processor
It either using FPGA generation soft-core processors (niosii or microblaze etc.), and is handled, is owned without software
Function module is present in the form of hardware circuit in FPGA, realizes parallel high-speed processing, so as to fulfill at low cost, reliably
The high image transmitting of property and control system.
3. it is analyzed in resource from using, what resource used in MAC drivers of the invention was provided for ALTERA companies
The 1/2 of Triple-Speed Ethernet IP kernel resources, after increasing all function modules, the resource used is still slightly below
Triple-Speed Ethernet IP kernels.
4. present system, under network stabilization state, transmission speed 280Mb/s can meet high-speed image sampling equipment
Transmit image data and video data.
5. circuit board and one piece FPGA board grafting of the hardware platform of present system by one piece of responsible network communication
It forms, practicability is stronger, arbitrary FPGA board, as long as drawing a certain number of contact pins, with kilomega network communication module hardware electricity
This netinit module can be driven after the connection of road, is carried out data transmission.
6. present system is preferable to the adaptability of fpga chip, using only phaselocked loop IP kernel common in fpga chip,
FIFO cachings IP kernel, RAM storage IP kernels, and have this kind of IP kernel in the fpga chip of different manufacturers, and parameter and called side
Formula is similar, slightly changes, you can with directly using in different fpga chips, professional platform independence is good.
Description of the drawings
Fig. 1 is the network communications circuits harden structure block diagram of the present invention；
Fig. 2 is FPGA board structure diagram of the present invention；
Fig. 3 is each functional block diagram of FPGA board of the present invention；
Fig. 4 is present invention processing order flow chart；
Fig. 5 is gathered data flow chart of the present invention；
Fig. 6 uses ping-pong structure encapsulated data packet schematic diagram for the present invention.
Specific embodiment
Technical scheme of the present invention is clearly and completely described with reference to the accompanying drawings of the specification.
The scientific grade CCD gigabit Ethernet communication system based on AX88180 as shown in Figure 1 and Figure 2, including network communication
Circuit board and at least one piece of FPGA board；FPGA board includes fpga chip, eeprom chip and SDRAM chips, FPGA
Chip is connect with eeprom chip according to IIC agreements, and SDRAM chips connect the storage for carrying out data with fpga chip；By FPGA
Common I/O interface connect other one piece of circuit board, and draw the pin identical with other one piece of circuit board, network communications circuits
Plate includes sequentially connected MAC layer chip, PHY layer chip and the RJ-45 interfaces with network isolation transformer, MAC layer chip
AX88180, PHY layer chip are 88E1111；RJ-45 interfaces are used to be connected to cable, the interface of MAC layer chip and PHY layer chip
For RGMII interfaces；The pin that the extraction of MAC layer chip is connect with another piece of circuit board, present invention selection eeprom chip are
24LC256, SDRAM chip are HY57V641620E, but the present invention does not limit the type selecting of fpga chip, as long as the fpga chip
There are a certain amount of logical storage resources, a certain amount of I/O port supports phaselocked loop IP kernel and the IP kernel of FIFO, FPGA cores
The data of piece acquisition are transferred to MAC layer chip and PHY layer chip, and PC is transferred to through the RJ-45 interfaces with network isolation transformer
Host computer；FPGA belongs to field programmable logic device, by realizing each function module inside FPGA, controls other peripheral hardwares
The work of chip, and then realize the function of gigabit networking communication.
As shown in figure 3, fpga chip inner function module includes netinit module, package unpacks module, network association
Discuss module, command analysis module, control scheduler module, EEPROM parameter access modules；Wherein netinit module can make
Network chip works normally, and it is that encapsulate data into can be in the form of transmission over networks or from reception that package, which unpacks module,
Network packet obtains corresponding data, and netinit module carries out the processing of procotol, and command analysis module can be right
Order is parsed, and control module is in the effect of dispatch coordination.Control scheduler module is in center, with netinit
Module, package unpack module, network protocol module, command analysis module and are connected with EEPROM parameter access modules, are responsible for coordination
The boot sequence and data of modules are transferred away to after electrification reset, control scheduler module is from EEPROM parameter access modules
Middle reading parameter information, such as MAC Address, IP address etc., and netinit module is allocated to, start netinit mould later
Block, netinit module are connect with MAC layer chip, PHY layer chip, and function is configuration MAC layer chip, configuration PHY layer core
Piece, startup send and receive submodule；Network protocol module carry out procotol processing, procotol include ICMP agreements and
ARP protocol；Network protocol module is connected with netinit module, is responsible for the data packet of processing ARP protocol and ICMP agreements；Envelope
Packet unpacks module and is connected with netinit module, packaged image data is sent, command analysis module and network
Initialization module is connected, and is responsible for the transmitting-receiving parsing work of order, command analysis module can parse order, by command area
Divide and various orders are returned into PC host computers, to form a winding.
The present invention using gigabit network MAC layer chip AX88180 and kilomega network PHY layer chip 88E1111 as communication infrastructure, by
FPGA realizes communication protocol as control chip inside FPGA, the functions such as control scheduling, and then realizes complete gigabit
Ethernet communication, its main feature is that communication speed is high, it is reliable and stable, 100,000,000 nets are compared, communication bandwidth increasing is more than ten times larger, avoids
When network communication data amount increases, 100 m ethernet can cause communication speed by CSMA/CD (carrier sense/collision detection)
Decline, cause communication blocking, data cannot send out and be capped, and cause loss of data, gigabit Ethernet communication is then due to communication
Speed is high, and has well solved this problem.
All modules are described in detail below：
Netinit module mainly includes following submodule：Reset_mac modules, 88e1111_phy_
Initial modules, ax88180_mac_config modules, rec_pack modules, send_pack modules；
Wherein reset_mac modules realize the read-write to MAC layer chip register first, then again to MAC layer chip
Register sets default initial values.
88e1111_phy_initial modules realize that PHY layer chip register can normally be read and write, and confirm that network is hard
Part connects media type, is light or common cable and PHY layer and the type of MAC-layer interface.
Ax88180_mac_config modules are after the completion of PHY initialization is determined, the physical link that is detected according to PHY
MAC registers are configured in state, and it is 10Mbs, 100Mb or 1000Mb to determine operating rate, can also negotiate the work side at both ends
Formula, full duplex or half-duplex；
Ax88180_mac_config modules mainly complete the configuration of MAC Address, determine that the type of received data packet is (wide
Broadcast, multicast, unicast and the one or several kinds arbitrarily broadcast), and open the transmitting-receiving flow control function of MAC layer chip.
Rec_pack modules are directed toward the variation of the register RXCURT and RXBOUND of the order caching by inquiry to connect
Data are received, and MAC Address, the IP address of PC host computers are obtained from the data packet of reception.
Send_pack modules are used for transmission data, and for different length by registers such as configuration register TX_CMD
The data packet to be sent of degree has different transmission configurations.
MAC layer chip there are one 32K order caching, by a kind of annular access mode, the PHY layer chip that will be received
The datacycle sended over is placed on this order caching, and produces and unpack module to package.
Package unpacks module and includes unpacking module and UDP package modules, for image data to be sealed according to udp protocol
Dress, and according to the length set in advance with PC sections of host computers, and the parameter of host computer needs is added in, it is ultimately routed in network, when
When image data is excessive, ping-pong structure can be used data cached, parallel package, and then efficient packet is provided.
Network protocol module, procotol include ICMP, ARP protocol, and different agreements has different processing modes.
In ICMP protocol modules, the present invention for data check in request packets and reply packets and relationship, devise a kind of simplification
Verification and generating mode, request packets be the inquiry packet that sends of computer end, reply packet communication systems need to reply
Data packet, usual reply packets need one verification of generation and, but the verification due to the verification of request packets and with reply packets
With 16 ' h0800 of difference, therefore need not individually calculate verification and, and read the verifications of request packets in addition this difference
.
Command analysis module, the order between present system and PC host computers include two major class, and one kind is control kilomega network
The order of communication module in itself such as links, and disconnects, acquisition etc., and another kind of is to control the image capture module that is connected with system
Order, such as time for exposure, gain, biasing, interior external trigger.It in command analysis module, needs to distinguish order, and will be also
Various orders are returned into PC host computers, to form one winding, ensure link integrity, the order of mistake is also wanted and
When send refusal instruction to corresponding PC host computers.
EEPROM parameter access modules, when unexpected power down, the parameter that image capture device has been configured will
It loses, needs effective order being stored in eeprom chip, further include the MAC Address and IP address of PC host computers here.
Control scheduler module is in the position of core, because the channel between MAC layer chip and fpga chip is half-duplex
, or it data that channel is transmitted for network-external or is gone for sending data to network-external, therefore control module is used
In the right to use for distributing the channel so that entire this system smoothness work, without conflicting.
To prevent network congestion, invention increases heartbeat packet module, image capture device timing is sent to PC host computers
Heartbeat packet judges whether network has blocked by test returns packet, and makes respective handling.
As shown in fig. 6, module is unpacked in package, since Image Acquisition front end is that image a line a line is transferred to this system
, first by a line image buffer storage to RAM, to improve the speed of service, this system is opened up two block RAM ping-pong buffer modules and is delayed
Deposit, ping-pong operation, synchronous to carry out package processing, package process will fill in various header packet informations according to udp protocol, and fill in
Then the parameter information that PC host computers are appointed is filling in image data, each UDP package module data of this system agreement
The length of packet is 1074 bytes.
This system and the connection mode of Image Acquisition front end are more flexible, and common scheme is as follows：
By FPGA board directly with Image Acquisition front end, and when the driving of image collection chip (CMOS or CCD) is provided
Sequence and configuration order, the driver' s timing and configuration order of AD modulus conversion chips, and then the image that Image Acquisition front end is obtained
Data are introduced directly into FPGA.FPGA board with other one piece of circuit board is connected, image is driven by other one block of FPGA plate
Front end is acquired, image data and order are transmitted between two pieces of FPGA boards.
The present invention also provides the method that the communication of scientific grade CCD gigabit Ethernet is realized based on above system, processing orders
Process as shown in figure 4, acquisition image process as shown in figure 5, each function module method of operation includes the following steps；
1) the system reset time of 200ms after the power is turned on, is first maintained, this system enters netinit state later：
2) in netinit state, the working condition of PHY layer chip and MAC layer chip, PHY layer chip has mainly been configured
Include determining network connecting media (light or twisted-pair feeder cable) with the working condition of MAC layer chip, network operating rate,
MAC Address, setting transmitting-receiving flow control, initializes receiving module, sending module, the network transfer speeds of this system can basis
Actual conditions determine, under normal circumstances, can be arranged to the operating mode of 1000Mb, and the working method of MAC layer and PHY layer is complete double
Work communicates；
3) enter and intercept state；
If what is received is procotol, it is determined that is which kind of procotol, if ARP protocol, then by this system
MAC Address and IP address agreement deposit ARP data packets in, be sent to PC host computers, and record PC host computers MAC Address and
IP address enters intercept state later；
If ICMP agreements, then corresponding reply packets will be replied, and enter intercept state later, and return to corresponding UDP associations
View, then check the data packet length whether with the equal length for the command packet appointed in advance, and check the data packet
In whether have order flag bit；
If it is determined that being order, then enter parsing link, and the order is returned into PC host computers, be otherwise considered as not
It is order, it is without any processing, and the state of intercepting is kept, the order length of this system and PC host computers agreement is 50 words
Section, and arrange corresponding order flag bit；
4) when this system is not set up also with PC host computers to be connect, it is necessary to receive " connection " order, just carry out next step
Processing, others order can all fail, and after determining that PC host computers send " connection ", this system is responded, and remembers this first
The IP address and MAC Address of PC host computers are deposited into the corresponding position of EEPROM, and it is upper that the order then is returned to PC
Machine, this system can receive the various setting commands of the PC host computers later, and return in time；If other PC host computers are sent out
Setting command if, " refusal order " data packet can be returned；
5) when this system receives " acquisition " order of PC host computers, will start Image Acquisition front-end collection to image
Data are transferred to PC host computers；
When this system, by configuration order of the PC host computers to Image Acquisition front end, (such as time for exposure, AD gains, AD are touched
Hair delay etc.), then these orders are sent to the corresponding chip in Image Acquisition front end after piece image transmission output, and by this
A little configuration informations are stored into corresponding position in EEPROM, and the order is returned；
When this system receives " passive transmission " order of PC host computers, the image newly to arrive is first passed in SDRAM, no
It actively sends, only when host computers provide " transmission ", image just starts to transmit；
If PC host computers send ON- and OFF- command, and remove the command parameter stored in EEPROM, reenter and intercept shape
State waits for new PC host computers to connect.
6) network congestion in order to prevent, when PC host computers and this system are established after connection, this system can every 15 seconds to
PC host computers send heartbeat packet, and if network state is normal, PC host computers can reply rapidly to this system confirms packet, if
Confirmation packet is not received yet more than 2s, then this system sends heartbeat packet again, if not receiving confirmation packet yet, then it is assumed that network
It blocks, this system, which enters, intercepts state, does not retransmit image data, in order to avoid deteriorating network congestion state, loses into image data.
Claims (10)
1. a kind of scientific grade CCD gigabit Ethernet communication system based on AX88180, it is characterised in that：Including network communication electricity
Road plate and at least one piece of FPGA board；
The FPGA board includes fpga chip, eeprom chip and SDRAM chips, the fpga chip and eeprom chip
It is connected according to IIC agreements, the SDRAM chips connect the storage for carrying out data with fpga chip；
The network communications circuits plate includes sequentially connected MAC layer chip, PHY layer chip and RJ-45 interfaces, the MAC layer
Chip is AX88180, and the PHY layer chip is 88E1111；The data of fpga chip acquisition are transferred to MAC layer chip and PHY layer
Chip is transferred to PC host computers through RJ-45 interfaces；
The fpga chip inner function module includes netinit module, package unpacks module, network protocol module, order
Parsing module, control scheduler module, EEPROM parameter access modules；It is described control scheduler module respectively with netinit mould
Block, package unpack module, network protocol module, command analysis module and are connected with EEPROM parameter access modules, are responsible for coordinating each
The boot sequence and data of a module are transferred away to after electrification reset, control scheduler module is from EEPROM parameter access modules
Parameter information is read, and is allocated to netinit module, starts netinit module, the netinit module later
It is connect with MAC layer chip, PHY layer chip, function sends and receives for MAC layer chip, configuration PHY layer chip is configured, starts
Submodule；The network protocol module carries out the processing of procotol, and the procotol includes ICMP agreements and ARP protocol；
The network protocol module is connected with netinit module, is responsible for the data packet of processing ARP protocol and ICMP agreements；The envelope
Packet unpacks module and is connected with netinit module, and packaged image data is sent, the command analysis module and network
Initialization module is connected, and is responsible for the transmitting-receiving parsing of order, the command analysis module can parse order, by command area
Divide and each order is returned into PC host computers and form a winding.
2. the scientific grade CCD gigabit Ethernet communication system according to claim 1 based on AX88180, it is characterised in that：
The netinit module includes reset_mac modules, 88e1111_phy_initial modules, ax88180_mac_
Config modules, rec_pack modules, send_pack modules；
The reset_mac modules realize that the read-write to MAC layer chip register and the register setting to MAC layer chip are silent
Recognize initial value；
The 88e1111_phy_initial modules realize the read-write of PHY layer chip register, and confirm that the network hardware connects
Media type and PHY layer, the type of MAC-layer interface；
The link state configuration MAC layer chip deposit that the ax88180_mac_config modules are detected according to PHY layer chip
Device, while negotiate the working method at both ends；The ax88180_mac_config modules complete the configuration of MAC Address, determine to connect
The type of data packet is received, and opens the transmitting-receiving flow control function of MAC layer chip；
The rec_pack modules are directed toward the variation of the register RXCURT and RXBOUND of order caching by inquiry to receive
Data, and MAC Address, the IP address of PC host computers are obtained from the data packet of reception；
The send_pack modules are directed to the data to be sent of different length by configuration register TX_CMD transmission datas
Packet sends different configurations.
3. the scientific grade CCD gigabit Ethernet communication system according to claim 1 or 2 based on AX88180, feature exist
In：The package unpacks module and is packaged image data according to udp protocol, including unpacking module and UDP package modules.
4. the scientific grade CCD gigabit Ethernet communication system according to claim 3 based on AX88180, it is characterised in that：
The package unpacks module and includes two block RAM ping-pong buffer modules, data cached using ping-pong structure, synchronous to carry out at package
Reason.
5. the scientific grade CCD gigabit Ethernet communication system according to claim 4 based on AX88180, it is characterised in that：
The length of each UDP package module data packets is 1074 bytes.
6. based on the method that any systems of claim 1-5 realize the communication of scientific grade CCD gigabit Ethernet, feature exists
In including the following steps：
1) it powers on, into netinit state；
2) in netinit state, the working condition of PHY layer chip and MAC layer chip is configured；
3) enter and intercept state；
4) connection is established；After determining that PC host computers send " connection ", the IP address and MAC Address of the PC host computers are remembered, it will
It is stored in the corresponding position of EEPROM, and order then is returned to PC host computers；If the setting life that other PC host computers are sent out
If order, passback " refusal order " data packet；
5) " acquisition " order of PC host computers is received, starts the image data of Image Acquisition front-end collection being transferred to PC upper
Machine；
When receiving configuration order of the PC host computers to Image Acquisition front end, then configuration order is sent to figure after image output
As the corresponding chip in acquisition front end, configuration information is stored into corresponding position in EEPROM, and the order is returned；
When " passive transmission " order for receiving PC host computers, the image newly to arrive is first passed in SDRAM chips, is not sent out actively
It send, only when host computers provide " transmission ", image just starts to transmit；
When PC host computers send ON- and OFF- command, system reenters the state of intercepting, new PC host computers is waited for connect.
7. the method according to claim 6 for realizing the communication of scientific grade CCD gigabit Ethernet, it is characterised in that：It further includes
Step 6) fpga chip sent heartbeat packet every 15 seconds to PC host computers, if network state is normal, PC host computers are replied rapidly
Confirm packet, if it exceeds 2s does not receive confirmation packet yet, then fpga chip sends heartbeat packet again, if not receiving confirmation yet
Packet, then it is assumed that network blockage into state is intercepted, does not retransmit image data.
8. the method for the realization scientific grade CCD gigabit Ethernet communication described according to claim 6 or 7, it is characterised in that：Step
3) it is specially：
If what is received is procotol, it is determined that is which kind of procotol, if ARP protocol, then by the MAC of system
In location and IP address deposit ARP data packets, PC host computers are sent to, and record the MAC Address and IP address of PC host computers, later
Into intercepting state；
If ICMP agreements, then corresponding reply packets will be replied, and enter intercept state later, return to corresponding udp protocol,
Check data packet length whether the command packet equal length with agreement, and check whether there is order mark in data packet
Position；
If it is determined that being order, then enter parsing link, and order is returned into PC host computers, it is not life to be otherwise considered as
It enables, it is without any processing, and keep the state of intercepting.
9. the method according to claim 8 for realizing the communication of scientific grade CCD gigabit Ethernet, it is characterised in that：The PHY
The working condition of layer chip and MAC layer chip includes determining network connecting media, network operating rate, MAC Address, setting transmitting-receiving
Flow control, initialization receiving module, sending module.
10. the method according to claim 9 for realizing the communication of scientific grade CCD gigabit Ethernet, it is characterised in that：It is described to match
It puts order and includes time for exposure, AD gains, AD or Time delay.
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