CN113296708A - Storage device with double-FLASH mixed data parallel storage and error correction functions - Google Patents
Storage device with double-FLASH mixed data parallel storage and error correction functions Download PDFInfo
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Abstract
The invention discloses a storage device with double FLASH mixed data storage parallel storage and error correction functions and a corresponding storage reading method, and relates to the field of high-speed data acquisition and storage. Including a hardware portion and a software portion. The hardware part comprises a power panel and a main control panel, wherein the power panel consists of an EMI filter and a DC/DC power module, and the DC/DC power module inputs voltage into a power conversion chip of the main control panel; the power conversion chip converts the 5V voltage into the voltage required by the system, and two network transformers, two gigabit network PHYs, two LTM2881-3, an FPGA chip, an EEPROM and an FLASH array are arranged in the main control board; the software part is a control logic program in the FPGA chip and comprises a storage process and a reading process. The invention can simultaneously carry out high-speed data storage on mass data of various data sources at various speeds without losing the data, reduces the whole storage error rate, can flexibly modify the IP address and the port number of the gigabit Ethernet and provides great convenience for the existing data storage.
Description
Technical Field
The invention relates to the field of high-speed data acquisition and storage, in particular to a storage device with double FLASH mixed data parallel storage and error correction functions.
Background
With the development of image sensor technology, images acquired by an image sensor are clearer, so that the amount of data generated in unit time is larger and larger, and how to store the acquired massive image data in real time is still one of the hot spots of research of many research institutions in recent years. FLASH storage is widely applied to the storage of mass image data in the military and civil fields due to the characteristics of high speed, nonvolatility, high and low temperature resistance, impact resistance and low cost.
The prior art cannot simultaneously store high-speed data of mass data of various data sources with different rates, the last part of data of the data sources is lost, the whole storage error rate is high, and the IP address and the port number of the gigabit Ethernet cannot be flexibly modified. There is a need to improve existing memory devices to address the above-mentioned problems.
Disclosure of Invention
The invention provides a storage device with double FLASH mixed data parallel storage and error correction functions, aiming at solving the problems that high-speed data storage cannot be simultaneously carried out on mass data of multiple data sources with different rates, the last part of data of the data sources is lost, the whole storage error rate is higher, and the IP address and the port number of a gigabit Ethernet cannot be flexibly modified.
The invention is realized by the following technical scheme: a storage device with double FLASH hybrid data parallel storage and error correction functions comprises a hardware part and a software part. The hardware part comprises a power panel and a main control panel, wherein the input voltage of the power panel is 28V, the power panel is composed of an EMI filter and a DC/DC power module, the 28V power supply voltage is connected with the DC/DC power module through the EMI filter, the EMI filter is used for inhibiting electromagnetic interference, and the DC/DC power module converts the 28V voltage into 5V voltage and inputs the voltage into a power conversion chip of the main control panel; the power supply conversion chip converts 5V voltage into 3.3V voltage, 1.2V voltage and 2.5V voltage required by a system, two network transformers, two gigabit network PHYs, two LTM2881-3 chips, an FPGA chip, an EEPROM and a FLASH array are arranged in the main control board, the two network transformers are respectively a network transformer I and a network transformer II, the two gigabit network PHYs are respectively a gigabit network PHY I and a gigabit network PHY II, the two LTM2881-3 chips are respectively LTM 2881-3I and LTM2881-3 II, the FLASH array comprises two FLASH memories and respectively a FLASH I and a FLASH II, the network transformer I and the gigabit network PHY I are connected and used for receiving gigabit Ethernet interface data and transmitting the data to the FPGA chip, the LTM 2881-3I is controlled by the FPGA chip and used for receiving low-speed PCM data sent by a data storage device by adopting an RS485 protocol, and the LTM2881-3 is controlled by the FPGA chip, RS422 protocol is adopted to realize the input of configuration parameters and the output of system state of the storage device; the EEPROM is connected with the FPGA chip and used for storing the IP address and the port number of the gigabit network PHY 1; the FLASH array is used for storing gigabit network data and PCM data, and the network transformer II and the gigabit network PHY II are controlled by the FPGA chip to read back the data in the FLASH array to the computer. The software part is a control logic program in an FPGA chip, and comprises the following specific steps: the data received by the gigabit network port is added with a frame count and a frame mark in a data dividing module I by taking 1Kbyte as a unit, and the data is divided into network port data I and network port data II; the data received by the RS485 interface is divided into 485 data I and 485 data II by adding a frame count and a frame mark in a data division module II by taking 1Kbyte as a unit; the method comprises the steps that data are selected by a network port data I and 485 data I through a data merging module I and are stored into a FLASH I, data are selected by a network port data II and 485 data II through a data merging module II and are stored into a FLASH II, byte number judging programs are arranged in the data merging module I and the data merging module II, firstly, the data merging module I judges whether the data sent by a gigabit Ethernet port reach the specified byte number or not, if yes, the data are transmitted into an FIFO memory and are ready to be written into the FLASH I; if the number of bytes does not reach the specified number of bytes, judging whether the data sent by the RS485 interface reaches the specified number of bytes, if so, transmitting the data to an FIFO memory, and preparing to write in the FLASH I; if the number of the data is not reached, continuously judging the data at the gigabit Ethernet port end, and sequentially judging and sending the data until the end of writing the data into the FLASH I is reached; similarly, the data merging module II stores the data into the FLASH II by the same method; data from the FIFO memory behind the data merging module I and the data merging module II are subjected to Hamming code or BCH coding through the coding module in the process of storing the data into the FLASH I/II, and then the Hamming code or BCH code coding data are stored into the FLASH I/II; in the process of reading data, generating Hamming code or BCH code encoding data in an encoding module, and comparing the Hamming code or BCH code encoding data stored in the FLASH I/II in a decoding module to determine which bit of a specific group of data sends an error; the error correction module is responsible for transmitting the data error correction in the FIFO memory at the front side to the FIFO memory at the rear side, the data of the FLASH I and the FLASH II are read out and then enter the data merging module III after error correction, the data of the FLASH in the data merging module III sequentially and alternately enter the network port data sending module, and finally the data are transmitted out through the gigabit Ethernet interface.
The storage device with the double-FLASH mixed data parallel storage and error correction functions mainly adopts two FLASH memories, when data is written in, the two FLASH memories are simultaneously erased, then the data is received from a gigabit Ethernet interface or an RS485 interface, the data is parallelly and alternately stored in the two FLASH memories, when the data is read, the data of the two FLASH memories are sequentially read, and the data is transmitted to the outside through the other gigabit Ethernet. The specific operation steps are as follows:
firstly, a storage process:
1) when data is written, an ARP protocol request packet is sent to the data storage device, the data storage device returns an ARP protocol response packet to bind an MAC address and an IP address, then a UDP protocol is started to send a data packet, and the data storage device starts to receive and analyze the UDP protocol data packet;
2) receiving a FLASH data erasing command through an RS422 interface, carrying out FLASH erasing, carrying out bad block detection after the system is powered on and reset, storing bad block addresses into an RAM, then judging whether the erasing command exists, carrying out FLASH erasing if the erasing command is received, simultaneously erasing two blocks, returning an erasing completion mark after the erasing is completed, and entering a data writing state by the FLASH; then judging whether the first FLASH block is a bad block, if so, adding 1 to the block address and then continuously judging the next FLASH block; before receiving data through the gigabit network port, the FPGA acquires an IP address or a port number required by the PHY I of the gigabit network through the EEPROM, or the data in the EEPROM is modified by a user through an RS422 interface and then updated into the FPGA;
3) then receiving data through an RS485 interface and a gigabit network PHY I, alternately storing the data to two FLASH pieces by gigabit Ethernet interface data or RS485 interface data by taking 16KByte as a unit, if the judged data in the FLASH is not a bad block, judging whether the FIFO in front has 8KByte data, if the 8KByte data exists, writing the data and a Hamming code or BCH code generated by the data into one page of the FLASH, and if the 8KByte data does not exist, continuing to wait, and repeating the steps in a circulating manner until the whole FLASH is completely written; two targets in the single-chip FLASH carry out data writing in a pipeline mode, and LUNs in a single Target carry out data writing in a Multi-Plane method;
4) data through the RS485 interface is transmitted in 1024 bytes one frame, wherein 1021-; receiving data at the rate of 5Mbps or 10Mbps simultaneously in the receiving process of the RS485 interface data, if receiving 3-time frame synchronous codes when receiving the data at the rate of 5Mbps, starting to receive and store the RS485 interface data at the rate of 5Mbps, and if receiving 3-time frame synchronous codes when receiving the data at the rate of 10Mbps, starting to receive and store the RS485 interface data at the rate of 10 Mbps; this allows for automatic adaptation of the PCM data rate;
5) in the process of writing data into the FLASH, a Hamming code or BCH code error correction method is adopted for error correction, so that error codes caused by write interference are reduced;
6) in the process of writing data into the FLASH, the gigabit Ethernet interface data of 64Kbyte is automatically filled when the FLASH is full or the gigabit Ethernet interface data is not received within 3 seconds, and the RS485 interface data of 64Kbyte is automatically filled when the RS485 interface data is not received within 3 seconds, so that data is prevented from being remained in the FIFO and data loss caused by the fact that the FLASH memory cannot write the 16Kbyte data into the FLASH;
II, reading:
1) receiving a FLASH data reading command through an RS422 interface, carrying out bad block detection after power-on reset of a system, storing bad block addresses into an RAM, judging whether a first FLASH block is a bad block or not when the FLASH reading command is received, adding 1 to the block address if the first FLASH block is the bad block, continuously judging a next FLASH block, reading 8KByte data and a Hamming code check code/BCH check code in a page address if the first FLASH block is not the bad block, adding 1 to the page address if the page address is completely read, adding 1 to the block address if all pages in the block are completely read, circularly repeating the steps until the whole FLASH reading is completed, and sending the data after the FLASH data reading through another gigabit network PHY II; two targets in the single-chip FLASH adopt a pipeline mode to read data, and the LUN in a single Target adopts a Multi-Plane method to read data; then, the 8KByte is taken as a unit to be transmitted outwards alternately through the gigabit Ethernet port;
2) in the process of reading data from FLASH, a Hamming code or BCH code error correction method is adopted for error correction, so that error codes caused by reading interference are reduced;
3) in the process of reading data, if the two FLASH chips finish reading or receive a command of stopping reading data, stopping reading the data.
Compared with the prior art, the invention has the following beneficial effects: the storage device with the double-FLASH mixed data parallel storage and error correction functions can simultaneously carry out high-speed data storage on mass data of various data sources at various speeds, and the last part of the data source does not lose data due to the automatic filling of data, so that the overall storage error rate is greatly reduced, the IP address and the port number of the gigabit Ethernet can be flexibly modified, and great convenience is provided for the existing data storage.
Drawings
Fig. 1 is a schematic diagram of system device composition and test connection relationship of a storage device according to an embodiment of the present invention.
FIG. 2 is a hardware schematic diagram of a memory device according to an embodiment of the invention.
FIG. 3 is a schematic diagram of program logic according to an embodiment of the present invention.
FIG. 4 is a logic diagram of a writing and reading process involved in a memory device according to an embodiment of the present invention.
Detailed Description
The present invention is further illustrated by the following specific examples.
As shown in fig. 1, in order to implement a storage device with dual FLASH hybrid data storage and data error correction functions, a data storage device test bench needs to be developed, so as to construct a complete data storage and test system.
Specifically, the data storage device test bench comprises an AC/DC power supply module and a test bench main control board. The data storage device test station provides 28V to the data storage device and the portable computer sends commands to the data storage device test station through the USB interface to control communication and data transfer between the data storage device test station and the data storage device. The data storage device test bench controls the data storage device through the RS422 interface protocol, the data storage device returns the working state to the data storage device test bench through the RS422 interface protocol, and the data storage device test bench returns the working state of the data storage device to the upper computer software of the portable computer through the USB interface for displaying. The data storage device test bench generates data and transmits the data to the data storage device through the RS485 interface and the gigabit Ethernet interface. When the data needs to be read back, the portable computer reads the data in the data storage device through the gigabit Ethernet interface.
The storage device with the double-FLASH hybrid data parallel storage and error correction function in the figure 1 comprises a hardware part and a software part; hardware part is shown in fig. 2, and software structure is shown in fig. 3: the hardware part comprises a power panel and a main control panel, wherein the input voltage of the power panel is 28V, the power panel is composed of an EMI filter and a DC/DC power module, the 28V power supply voltage is connected with the DC/DC power module through the EMI filter, the EMI filter is used for inhibiting electromagnetic interference, and the DC/DC power module converts the 28V voltage into 5V voltage and inputs the voltage into a power conversion chip of the main control panel; the power supply conversion chip converts 5V voltage into 3.3V voltage, 1.2V voltage and 2.5V voltage required by a system, two network transformers, two gigabit network PHYs, two LTM2881-3 chips, an FPGA chip, an EEPROM and a FLASH array are arranged in the main control board, the two network transformers are respectively a network transformer I and a network transformer II, the two gigabit network PHYs are respectively a gigabit network PHY I and a gigabit network PHY II, the two LTM2881-3 chips are respectively LTM 2881-3I and LTM2881-3 II, the FLASH array comprises two FLASH memories and respectively a FLASH I and a FLASH II, the network transformer I and the gigabit network PHY I are connected and used for receiving gigabit Ethernet interface data and transmitting the data to the FPGA chip, the LTM 2881-3I is controlled by the FPGA chip and used for receiving low-speed PCM data sent by a data storage device by adopting an RS485 protocol, and the LTM2881-3 is controlled by the FPGA chip, RS422 protocol is adopted to realize the input of configuration parameters and the output of system state of the storage device; the EEPROM is connected with the FPGA chip and used for storing the IP address and the port number of the gigabit network PHY 1; the FLASH array is used for storing gigabit network data and PCM data, and the network transformer II and the gigabit network PHY II are controlled by the FPGA chip to read back the data in the FLASH array into the computer; the software part is a control logic program in an FPGA chip, and comprises the following specific steps: the data received by the gigabit network port is added with a frame count and a frame mark in a data dividing module I by taking 1Kbyte as a unit, and the data is divided into network port data I and network port data II; the data received by the RS485 interface is divided into 485 data I and 485 data II by adding a frame count and a frame mark in a data division module II by taking 1Kbyte as a unit; the method comprises the steps that data are selected by a network port data I and 485 data I through a data merging module I and are stored into a FLASH I, data are selected by a network port data II and 485 data II through a data merging module II and are stored into a FLASH II, byte number judging programs are arranged in the data merging module I and the data merging module II, firstly, the data merging module I judges whether the data sent by a gigabit Ethernet port reach the specified byte number or not, if yes, the data are transmitted into an FIFO memory and are ready to be written into the FLASH I; if the number of bytes does not reach the specified number of bytes, judging whether the data sent by the RS485 interface reaches the specified number of bytes, if so, transmitting the data to an FIFO memory, and preparing to write in the FLASH I; if the number of the data is not reached, continuously judging the data at the gigabit Ethernet port end, and sequentially judging and sending the data until the end of writing the data into the FLASH I is reached; similarly, the data merging module II stores the data into the FLASH II by the same method; data from the FIFO memory behind the data merging module I and the data merging module II are subjected to Hamming code or BCH coding through the coding module in the process of storing the data into the FLASH I/II, and then the Hamming code or BCH code coding data are stored into the FLASH I/II; in the process of reading data, generating Hamming code or BCH code encoding data in an encoding module, and comparing the Hamming code or BCH code encoding data stored in the FLASH I/II in a decoding module to determine which bit of a specific group of data sends an error; the error correction module is responsible for transmitting the data error correction in the FIFO memory at the front side to the FIFO memory at the rear side, the data of the FLASH I and the FLASH II are read out and then enter the data merging module III after error correction, the data of the FLASH in the data merging module III sequentially and alternately enter the network port data sending module, and finally the data are transmitted out through the gigabit Ethernet interface.
In this embodiment, the FLASH I and the FLASH II adopt NAND FLASH memories of magnesium light; the data merging module I judges whether the data sent by the gigabit Ethernet port reaches 16Kbyte or not, and if so, the data are transmitted to the FIFO memory to be written into the FLASH I; if the data does not reach 16KByte, judging whether the data sent by the RS485 interface reaches 16KByte, if so, transmitting the data to an FIFO memory to prepare to be written into FLASH I; if the number of the data is not reached, the data at the gigabit Ethernet port end is continuously judged, and the data are sequentially judged and sent until the end of writing the data into the FLASH I is reached.
The storage and reading method of the storage device with the double-FLASH mixed data parallel storage and error correction functions comprises the following steps:
firstly, a storage process:
1) when data is written, the test board of the data storage device firstly sends an ARP protocol request packet to the data storage device, the data storage device returns an ARP protocol response packet to bind an MAC address and an IP address, then starts to send a data packet by a UDP protocol, and the data storage device starts to receive and analyze the UDP protocol data packet;
2) receiving a FLASH data erasing command through an RS422 interface, carrying out FLASH erasing, carrying out bad block detection after power-on reset of a system, storing a bad block address into an RAM, then judging whether the erasing command exists, carrying out FLASH erasing if the erasing command is received, returning an erasing completion mark after the erasing is completed, and entering a data writing state by the FLASH; then judging whether the first FLASH block is a bad block, if so, adding 1 to the block address and then continuously judging the next FLASH block; before receiving data through a gigabit network port, the FPGA acquires an IP address or a port number required by a PHY I of the gigabit network through an EEPROM, a data storage device has the own IP address and port number, the EEPROM is adopted to store the IP address and the port number, and the data storage device is automatically read after being electrified every time; if the IP address and the port number of the data storage device are modified by a user through an RS422 interface, the modified IP address and the modified port number are stored in the EEPROM, and the FPGA automatically updates the current IP address and the port number through the EEPROM;
3) then receiving data through an RS485 interface and a gigabit network PHY I, alternately storing the data to two FLASH pieces by gigabit Ethernet interface data or RS485 interface data by taking 16KByte as a unit, if the judged data in the FLASH is not a bad block, judging whether the FIFO in front has 8KByte data, if the 8KByte data exists, writing the data and a Hamming code or BCH code generated by the data into one page of the FLASH, and if the 8KByte data does not exist, continuing to wait, and repeating the steps in a circulating manner until the whole FLASH is completely written; two targets in the single-chip FLASH carry out data writing in a pipeline mode, and LUNs in a single Target carry out data writing in a Multi-Plane method;
4) data through the RS485 interface is transmitted in 1024 bytes one frame, wherein 1021-; receiving data at the rate of 5Mbps or 10Mbps simultaneously in the receiving process of the RS485 interface data, if receiving 3-time frame synchronous codes when receiving the data at the rate of 5Mbps, starting to receive and store the RS485 interface data at the rate of 5Mbps, and if receiving 3-time frame synchronous codes when receiving the data at the rate of 10Mbps, starting to receive and store the RS485 interface data at the rate of 10 Mbps; this allows for automatic adaptation of the PCM data rate;
5) in the process of writing data into the FLASH, a Hamming code or BCH code error correction method is adopted for error correction, so that error codes caused by write interference are reduced; the error correction in the storage process is divided into single-bit error correction and multi-bit error correction, wherein the single-bit error correction adopts Hamming codes to carry out error correction, and the multi-bit error correction adopts BCH codes to carry out error correction, and the method specifically comprises the following steps:
when the method is concretely implemented, Hamming code coding is adopted to correct single bit error bits, each page of NAND FLASH of magnesium light has (8192 + 448) Byte storage space for storing data, the former 8192Byte space is used for storing data, the 8193Byte position is used for storing a bad block mark, and the 8194Byte-8577 Byte storage space is used for storing Hamming code coding data. 8192Byte data is divided into 128 groups, each group is 64 bytes, and each group generates 3Byte Hamming code coded data which is sequentially stored in the 8194Byte-8577 Byte storage position of the memory.
In specific implementation, when BCH coding is adopted, error correction can be performed on multiple-bit error bits, NAND FLASH pages of magnesium light each have (8192 + 448) Byte storage space which can be used for storing data, the former 8192Byte storage space is generally used for storing data, specifically, if 3-bit data bits are to be corrected in 16-bit data, the word length of a BCH code word needs to be 31 bits, and the error correction capability is stronger by adopting a BCH code error correction method, but the storage amount and the storage speed of FLASH are affected.
6) In the process of writing data into the FLASH, the gigabit Ethernet interface data of 64Kbyte is automatically filled when the FLASH is full or the gigabit Ethernet interface data is not received within 3 seconds, and the RS485 interface data of 64Kbyte is automatically filled when the RS485 interface data is not received within 3 seconds, so that data is prevented from being remained in the FIFO and data loss caused by the fact that the FLASH memory cannot write the 16Kbyte data into the FLASH;
II, reading:
1) receiving a FLASH data reading command through an RS422 interface, carrying out bad block detection after power-on reset of a system, storing bad block addresses into an RAM, judging whether a first FLASH block is a bad block or not when the FLASH reading command is received, adding 1 to the block address if the first FLASH block is the bad block, continuously judging a next FLASH block, reading 8KByte data and a Hamming code check code/BCH check code in a page address if the first FLASH block is not the bad block, adding 1 to the page address if the page address is completely read, adding 1 to the block address if all pages in the block are completely read, circularly repeating the steps until the whole FLASH reading is completed, and sending the data after the FLASH data reading through another gigabit network PHY II; two targets in the single-chip FLASH adopt a pipeline mode to read data, and the LUN in a single Target adopts a Multi-Plane method to read data; then, the 8KByte is taken as a unit to be transmitted outwards alternately through the gigabit Ethernet port;
2) in the process of reading data from FLASH, a Hamming code or BCH code error correction method is adopted for error correction, so that error codes caused by reading interference are reduced; the error correction in the reading process is also divided into single-bit error correction and multi-bit error correction, wherein the single-bit error correction adopts Hamming codes to carry out error correction, and the multi-bit error correction adopts BCH codes to carry out error correction.
3) In the process of reading data, if the two FLASH chips finish reading or receive a command of stopping reading data, stopping reading the data.
As shown in fig. 4, in order to control the program for erasing and reading data from the FLASH, the system performs bad block detection after power-on reset, and stores the bad block address in the RAM. Then judging whether an erasing or reading command exists, if the erasing command is received, carrying out FLASH erasing, judging whether a first FLASH block is a bad block after the erasing is finished, if the first FLASH block is the bad block, continuing to judge a next block after adding 1 to the block address, if the first FLASH block is not the bad block, judging whether 8KByte data exists in the FIFO in front, if the 8KByte data exists, writing the data and a Hamming code or BCH check code generated by the data into one page of the FLASH, if the 8KByte data does not exist, continuing to wait, and repeating in a circulating manner until the whole FLASH is completely written; if the received command is a reading command, judging whether the first block is a bad block, if the first block is the bad block, adding 1 to the block address, and then continuing to judge the next block, if the first block is not the bad block, reading 8KByte data and Hamming code check code/BCH check code in the page address, if the page address is read completely, adding 1 to the page address, if all pages in the block are read completely, adding 1 to the block address, and repeating the steps until the reading of the whole FLASH is completed.
The scope of the invention is not limited to the above embodiments, and various modifications and changes may be made by those skilled in the art, and any modifications, improvements and equivalents within the spirit and principle of the invention should be included in the scope of the invention.
Claims (8)
1. A storage device with double FLASH hybrid data parallel storage and error correction functions is characterized in that: comprises a hardware part and a software part;
the hardware part comprises a power panel and a main control panel, wherein the input voltage of the power panel is 28V, the power panel is composed of an EMI filter and a DC/DC power module, the 28V power supply voltage is connected with the DC/DC power module through the EMI filter, the EMI filter is used for inhibiting electromagnetic interference, and the DC/DC power module converts the 28V voltage into 5V voltage and inputs the voltage into a power conversion chip of the main control panel; the power supply conversion chip converts 5V voltage into 3.3V voltage, 1.2V voltage and 2.5V voltage required by a system, two network transformers, two gigabit network PHYs, two LTM2881-3 chips, an FPGA chip, an EEPROM and a FLASH array are arranged in the main control board, the two network transformers are respectively a network transformer I and a network transformer II, the two gigabit network PHYs are respectively a gigabit network PHY I and a gigabit network PHY II, the two LTM2881-3 chips are respectively LTM 2881-3I and LTM2881-3 II, the FLASH array comprises two FLASH memories and respectively a FLASH I and a FLASH II, the network transformer I and the gigabit network PHY I are connected and used for receiving gigabit Ethernet interface data and transmitting the data to the FPGA chip, the LTM 2881-3I is controlled by the FPGA chip and used for receiving low-speed PCM data sent by a data storage device by adopting an RS485 protocol, and the LTM2881-3 is controlled by the FPGA chip, RS422 protocol is adopted to realize the input of configuration parameters and the output of system state of the storage device; the EEPROM is connected with the FPGA chip and used for storing the IP address and the port number of the gigabit network PHY 1; the FLASH array is used for storing gigabit network data and PCM data, and the network transformer II and the gigabit network PHY II are controlled by the FPGA chip to read back the data in the FLASH array into the computer;
the software part is a control logic program in an FPGA chip, and comprises the following specific steps: the data received by the gigabit network port is added with a frame count and a frame mark in a data dividing module I by taking 1Kbyte as a unit, and the data is divided into network port data I and network port data II; the data received by the RS485 interface is divided into 485 data I and 485 data II by adding a frame count and a frame mark in a data division module II by taking 1Kbyte as a unit; the method comprises the steps that data are selected by a network port data I and 485 data I through a data merging module I and are stored into a FLASH I, data are selected by a network port data II and 485 data II through a data merging module II and are stored into a FLASH II, byte number judging programs are arranged in the data merging module I and the data merging module II, firstly, the data merging module I judges whether the data sent by a gigabit Ethernet port reach the specified byte number or not, if yes, the data are transmitted into an FIFO memory and are ready to be written into the FLASH I; if the number of bytes does not reach the specified number of bytes, judging whether the data sent by the RS485 interface reaches the specified number of bytes, if so, transmitting the data to an FIFO memory, and preparing to write in the FLASH I; if the number of the data is not reached, continuously judging the data at the gigabit Ethernet port end, and sequentially judging and sending the data until the end of writing the data into the FLASH I is reached; similarly, the data merging module II stores the data into the FLASH II by the same method; data from the FIFO memory behind the data merging module I and the data merging module II are subjected to Hamming code or BCH coding through the coding module in the process of storing the data into the FLASH I/II, and then the Hamming code or BCH code coding data are stored into the FLASH I/II; in the process of reading data, generating Hamming code or BCH code encoding data in an encoding module, and comparing the Hamming code or BCH code encoding data stored in the FLASH I/II in a decoding module to determine which bit of a specific group of data sends an error; the error correction module is responsible for transmitting the data error correction in the FIFO memory at the front side to the FIFO memory at the rear side, the data of the FLASH I and the FLASH II are read out and then enter the data merging module III after error correction, the data of the FLASH in the data merging module III sequentially and alternately enter the network port data sending module, and finally the data are transmitted out through the gigabit Ethernet interface.
2. The storage device with dual FLASH hybrid data parallel storage and error correction functions of claim 1, wherein: the FLASH I and the FLASH II adopt NAND FLASH memories of magnesium light.
3. The storage device with dual FLASH hybrid data parallel storage and error correction functions of claim 1, wherein: the data merging module I judges whether the data sent by the gigabit Ethernet port reaches 16Kbyte or not, if so, the data are transmitted to an FIFO memory to be written into FLASH I; if the data does not reach 16KByte, judging whether the data sent by the RS485 interface reaches 16KByte, if so, transmitting the data to an FIFO memory to prepare to be written into FLASH I; if the number of the data is not reached, the data at the gigabit Ethernet port end is continuously judged, and the data are sequentially judged and sent until the end of writing the data into the FLASH I is reached.
4. The storage and reading method of a storage device having a dual FLASH hybrid data parallel storage and error correction function of claim 1, wherein: the method comprises the following steps:
firstly, a storage process:
1) when data is written, an ARP protocol request packet is sent to the data storage device, the data storage device returns an ARP protocol response packet to bind an MAC address and an IP address, then a UDP protocol is started to send a data packet, and the data storage device starts to receive and analyze the UDP protocol data packet;
2) receiving a FLASH data erasing command through an RS422 interface, carrying out FLASH erasing, carrying out bad block detection after power-on reset of a system, storing a bad block address into an RAM, then judging whether the erasing command exists, carrying out FLASH erasing if the erasing command is received, returning an erasing completion mark after the erasing is completed, and entering a data writing state by the FLASH; then judging whether the first FLASH block is a bad block, if so, adding 1 to the block address and then continuously judging the next FLASH block; before receiving data through the gigabit network port, the FPGA acquires an IP address or a port number required by the PHY I of the gigabit network through the EEPROM, or the data in the EEPROM is modified by a user through an RS422 interface and then updated into the FPGA;
3) then receiving data through an RS485 interface and a gigabit network PHY I, alternately storing the data to two FLASH pieces by gigabit Ethernet interface data or RS485 interface data by taking 16KByte as a unit, if the judged data in the FLASH is not a bad block, judging whether the FIFO in front has 8KByte data, if the 8KByte data exists, writing the data and a Hamming code or BCH code generated by the data into one page of the FLASH, and if the 8KByte data does not exist, continuing to wait, and repeating the steps in a circulating manner until the whole FLASH is completely written; two targets in the single-chip FLASH carry out data writing in a pipeline mode, and LUNs in a single Target carry out data writing in a Multi-Plane method;
4) data through the RS485 interface is transmitted in 1024 bytes one frame, wherein 1021-; receiving data at the rate of 5Mbps or 10Mbps simultaneously in the receiving process of the RS485 interface data, if receiving 3-time frame synchronous codes when receiving the data at the rate of 5Mbps, starting to receive and store the RS485 interface data at the rate of 5Mbps, and if receiving 3-time frame synchronous codes when receiving the data at the rate of 10Mbps, starting to receive and store the RS485 interface data at the rate of 10 Mbps; this allows for automatic adaptation of the PCM data rate;
5) in the process of writing data into the FLASH, a Hamming code or BCH code error correction method is adopted for error correction, so that error codes caused by write interference are reduced;
6) in the process of writing data into the FLASH, the gigabit Ethernet interface data of 64Kbyte is automatically filled when the FLASH is full or the gigabit Ethernet interface data is not received within 3 seconds, and the RS485 interface data of 64Kbyte is automatically filled when the RS485 interface data is not received within 3 seconds, so that data is prevented from being remained in the FIFO and data loss caused by the fact that the FLASH memory cannot write the 16Kbyte data into the FLASH;
II, reading:
1) receiving a FLASH data reading command through an RS422 interface, carrying out bad block detection after power-on reset of a system, storing bad block addresses into an RAM, judging whether a first FLASH block is a bad block or not when the FLASH reading command is received, adding 1 to the block address if the first FLASH block is the bad block, continuously judging a next FLASH block, reading 8KByte data and a Hamming code check code/BCH check code in a page address if the first FLASH block is not the bad block, adding 1 to the page address if the page address is completely read, adding 1 to the block address if all pages in the block are completely read, circularly repeating the steps until the whole FLASH reading is completed, and sending the data after the FLASH data reading through another gigabit network PHY II; two targets in the single-chip FLASH adopt a pipeline mode to read data, and the LUN in a single Target adopts a Multi-Plane method to read data; then, the 8KByte is taken as a unit to be transmitted outwards alternately through the gigabit Ethernet port;
2) in the process of reading data from FLASH, a Hamming code or BCH code error correction method is adopted for error correction, so that error codes caused by reading interference are reduced;
3) in the process of reading data, if the two FLASH chips finish reading or receive a command of stopping reading data, stopping reading the data.
5. The storage and reading method of a storage device with dual FLASH hybrid data parallel storage and error correction functions as claimed in claim 4, wherein: the parallel storage of the double-FLASH mixed data in the step 3) of the storage process specifically comprises the following steps: the gigabit network PHY I writes data into two FLASH chips at a storage rate of 400 Mbps.
6. The storage and reading method of a storage device with dual FLASH hybrid data parallel storage and error correction functions as claimed in claim 4, wherein: the error correction in the storage and reading processes is divided into single-bit error correction and multi-bit error correction, wherein the single-bit error correction adopts Hamming codes to carry out error correction, and the multi-bit error correction adopts BCH codes to carry out error correction.
7. The storage and reading method of a storage device with dual FLASH hybrid data parallel storage and error correction functions as claimed in claim 4, wherein: in the step 2) of the storage process, the data storage device has an own IP address and port number, the IP address and the port number are stored by adopting an EEPROM (electrically erasable programmable read-only memory), and the data storage device is automatically read after being electrified every time; if the IP address and the port number of the data storage device are modified by a user through the RS422 interface, the modified IP address and the modified port number are stored in the EEPROM, and the FPGA automatically updates the current IP address and the port number through the EEPROM.
8. The storage and reading method of a storage device with dual FLASH hybrid data parallel storage and error correction functions as claimed in claim 4, wherein: the FLASH uses NAND FLASH memory of magnesium light.
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