CN111522588A - Chip operation interaction method and communication system based on SWD protocol - Google Patents
Chip operation interaction method and communication system based on SWD protocol Download PDFInfo
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- CN111522588A CN111522588A CN202010301374.2A CN202010301374A CN111522588A CN 111522588 A CN111522588 A CN 111522588A CN 202010301374 A CN202010301374 A CN 202010301374A CN 111522588 A CN111522588 A CN 111522588A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/1607—Details of the supervisory signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a chip operation interaction method and a communication system based on an SWD protocol, which ensure normal operation interaction of an upper computer and a CORTEX chip by presetting an address A, an address B, an address C and a corresponding storage space in the CORTEX chip and simultaneously adopting a specific command interaction mode, realize that the CORTEX chip can simultaneously receive data in the process of processing own transaction, avoid generating any extra expense due to the received data, ensure the integrity of data transmission and simplify the operation interaction process of the upper computer and the chip.
Description
Technical Field
The invention relates to the technical field of operation control of electronic circuits, in particular to a chip operation interaction method and a communication system based on an SWD protocol.
Background
The ARM company products after the classical processor ARM11 are named after Cortex and are divided into three categories A, R and M, which are intended to serve various markets. ARM CortexTM-A series of applicationsA type processor can provide a full range of solutions to devices hosting rich OS platforms and user applications, from ultra low cost cell phones, smart phones, mobile computing platforms, digital televisions, and set-top boxes to enterprise networks, printers, and server solutions. The ARM Cortex-R family of application-type processors are capable of real-time processors providing high performance computing solutions for embedded systems that require reliability, high availability, fault tolerance, maintainability, and real-time response. ARM CortexTMThe M-family application-type processors are a family of upwardly compatible, energy efficient, easy-to-use processors that are intended to help developers meet the needs of future embedded applications. These needs include providing more functionality at lower cost, increasing connectivity, improving code reuse, and improving energy efficiency.
Although the Cortex series chip has strong processing capability, if the Cortex chip receives data again in the process of processing own transaction, additional overhead is generated, and normal interaction between the upper computer and the Cortex chip is obviously influenced.
Disclosure of Invention
The invention aims to provide a chip operation interaction method based on an SWD protocol, and the mechanism can realize that CORTEX series chips can simultaneously receive data in the process of processing own transactions, does not generate any extra overhead due to data receiving, can ensure the integrity of data transmission, and simplifies the operation interaction process of an upper computer and the chips. The invention is realized by the following technical scheme:
a chip operation interaction mechanism based on SWD protocol is characterized in that:
the steps executed by the upper computer end comprise:
(1) initializing an SWD bus;
(2) taking out a command to be sent to a CORTEX chip;
(3) sending commands over the SWD bus, including:
(3-1) sending the write length and the command data content to a preset address A in the CORTEX chip;
(3-2) sending a command code to a preset address B in the CORTEX chip;
(4) after the CORTEX chip finishes processing the command, reading ACK response content stored in a preset address C in the CORTEX chip;
(5) repeating the step (2) to the step (4) until all commands of the upper computer are sent;
the CORTEX chip end executes the steps of:
initializing a CORTEX chip;
reading a command code in a preset address B;
reading the length in the preset address A and reading the data with the corresponding length;
fourthly, forming a complete command according to the data read in the second step and the third step, and executing the corresponding command;
after finishing executing the command, clearing the command code in the preset address B so as to receive the next command;
writing ACK response content into a preset address C;
seventhly, repeatedly executing the step (I) and the step (II).
As a specific technical scheme, in the step (4), if the ACK response content in the preset address C in the CORTEX chip cannot be read, the reading is repeatedly performed until the ACK response content is read.
As a specific technical scheme, in the second step, if the command code cannot be read from the preset address B in the CORTEX chip, the reading is repeated until the command code is read.
The invention also provides a communication system, which comprises an upper computer and a CORTEX chip, and is characterized in that: the upper computer and the CORTEX chip are matched to execute the chip operation interaction method based on the SWD protocol.
The invention has the beneficial effects that: the address A, the address B, the address C and the corresponding storage space are preset in the CORTEX chip, and a specific command interaction mode is adopted, so that the normal operation interaction between the upper computer and the CORTEX chip is ensured, the CORTEX chip can receive data simultaneously in the process of processing own transactions, any extra overhead caused by data receiving is avoided, the integrity of data transmission can be ensured, and the operation interaction process of the upper computer and the chip is simplified.
Drawings
Fig. 1 is a flowchart of a chip operation interaction mechanism based on an SWD protocol according to an embodiment of the present invention.
Detailed Description
According to the communication system provided by the embodiment, the upper computer is communicated with the CORTEX chip through the SWD protocol, and asynchronous data transmission can be realized through the SWD protocol communication, so that the normal operation interaction between the upper computer and the CORTEX chip can be ensured only by adopting a specific command interaction mode.
Referring to fig. 1, in the chip operation interaction method based on the SWD protocol provided in this embodiment, an address a, an address B, an address C, and a corresponding storage space are preset in the CORTEX chip. The following description is made from the upper computer end and the CORTEX chip end, respectively, as follows:
the steps executed by the upper computer end comprise:
(1) initializing an SWD bus;
(2) taking out a command to be sent to a CORTEX chip;
(3) sending commands over the SWD bus, including:
(3-1) sending the write length and the command data content to a preset address A in the CORTEX chip;
(3-2) sending a command code to a preset address B in the CORTEX chip;
(4) after the CORTEX chip finishes processing the command, reading ACK (Acknowledgement character) response content stored in a preset address C in the CORTEX chip; if the ACK response content stored in the preset address C in the CORTEX chip cannot be read, repeatedly reading;
(5) repeating the step (2) to the step (4) until all commands of the upper computer are sent;
the CORTEX chip end executes the steps of:
initializing a CORTEX chip;
reading the content in the preset address B, if a command code is read, executing the step III, otherwise, executing the step II;
reading the length in the preset address A and reading the data with the corresponding length;
fourthly, forming a complete command according to the data read in the second step and the third step, and executing the corresponding command;
after finishing executing the command, clearing the command code in the preset address B so as to receive the next command;
writing ACK response content into a preset address C;
seventhly, repeatedly executing the step (I) and the step (II).
The above embodiments are merely provided for full disclosure and not for limitation, and any replacement of equivalent technical features based on the gist of the present invention without creative efforts should be considered as the scope of the present disclosure.
Claims (4)
1. A chip operation interaction method based on SWD protocol is characterized in that:
the steps executed by the upper computer end comprise:
(1) initializing an SWD bus;
(2) taking out a command to be sent to a CORTEX chip;
(3) sending commands over the SWD bus, including:
(3-1) sending the write length and the command data content to a preset address A in the CORTEX chip;
(3-2) sending a command code to a preset address B in the CORTEX chip;
(4) after the CORTEX chip finishes processing the command, reading ACK response content stored in a preset address C in the CORTEX chip;
(5) repeating the step (2) to the step (4) until all commands of the upper computer are sent;
the CORTEX chip end executes the steps of:
initializing a CORTEX chip;
reading a command code in a preset address B;
reading the length in the preset address A and reading the data with the corresponding length;
fourthly, forming a complete command according to the data read in the second step and the third step, and executing the corresponding command;
after finishing executing the command, clearing the command code in the preset address B so as to receive the next command;
writing ACK response content into a preset address C;
seventhly, repeatedly executing the step (I) and the step (II).
2. The chip operation interaction method based on the SWD protocol of claim 1, wherein in the step (4), if the ACK response content in the preset address C in the CORTEX chip cannot be read, the reading is repeated until the ACK response content is read.
3. The chip operation interaction method based on the SWD protocol as claimed in claim 1, wherein in the step two, if the command code cannot be read from the preset address B in the CORTEX chip, the reading is repeated until the command code is read.
4. The utility model provides a communication system, includes host computer and CORTEX chip, its characterized in that: the upper computer and the CORTEX chip are matched to execute the chip operation interaction method based on the SWD protocol in any one of claims 1 to 3.
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2020
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