KR20050064409A - Zoom camera system with high-pixel - Google Patents

Abstract

Disclosed is a high-pixel zoom camera system capable of simultaneously transferring and storing a PC simultaneously with a monitor display of a camera image based on IEEE1394.

The high-pixel zoom camera system according to the present invention supports an RGB video monitor output and a PC transmission using IEEE1394 at the same time, and is equipped with an algorithm implemented to enable the IEEE1394 output of a high-pixel image in real time, and to store the image using the IEEE1394 on a PC. In addition to supporting camera control such as playback and playback, a long line can be adopted for camera installation, and various functions (Zoom, AF, AE, AWB, image inversion, black and white, and negative) for accurate determination of the subject can be adopted. As it supports simultaneous observation with PC and separate monitor, it is very effective when applied to medical, educational, industrial, and industrial zoom camera system.

Description

Zoom camera system with high-pixel

The present invention relates to a PC transmission high pixel zoom camera system, and more particularly, to a camera application, image processing, and IEEE1394 control-based high pixel camera application system capable of simultaneously displaying and displaying a camera image and transmitting and storing a PC.

Conventional high-pixel zoom camera systems display a camera image on a monitor while a convenient system for PC transmission and storage is not on the market and some similar products are in circulation, but there are problems of high price and low compatibility with general PCs.

In addition, the data transmission / reception structure for data transmission and reception is not standardized in the image processing functions such as image inversion, black and white, sound, etc., which makes it difficult to store data and process the image. There is no known technique for outputting digital data such that long lines are possible.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a high-pixel zoom camera system using IEEE1394 for camera application, image processing, and PC application that can simultaneously monitor and display a camera image and transmit and store a PC.

High pixel zoom camera system according to the present invention for achieving the above technical problem,

A zoom mechanism for driving the lens using a motor driver and a motor to collect an image from an object to be photographed and to capture an image by a CCD element;

An analog signal processor and a digital signal processor for signal processing including color correction and brightness correction in the image captured by the CCD device;

Bus control process to control setup, connect, and disconnect of 1394 bus, zoom control, focus control, brightness, and contrast of camera Camera control process that generates control data for control and sends it to camera, Link interface process that receives decoded data and makes transmission / reception data, Memory to store input data in memory and transmits data stored in link interface A microcomputer that controls the zoom mechanism, the analog signal processor, and the digital signal processor in a series of control processes including a control process;

A digital transmission format FPGA for converting the signal-processed image data into a format for transmission;

An IEEE 1394 physical layer interface that handles electrical and mechanical interfaces with a PC and converts data including signals for access communication and disconnection into signals compatible with the communication medium;

An IEEE 1394 link layer interface in charge of a protocol in a program that manages movement of data in and out of the IEEE 1394 physical layer interface;

A transmission unit for amplifying and transmitting a signal for transmission through buffering for transmission and a transmission line having a predetermined distance or more;

A receiver for buffering and receiving image data transmitted through a cable;

An image application FPGA converting the received data into image inversion, black and white, and negative and simultaneously transmitting image data to an RGB encoder and an IEEE1394 transmitting FPGA;

An RGB encoder for converting digital image data received from the image application FPGA into an analog image signal for monitor output;

An RGB signal amplifier for amplifying and transmitting the encoded analog image signal;

A monitor configured to receive an amplified analog image signal and display an image; And

It is characterized in that it comprises a; IEEE1394 transmission FPGA for transmitting the image of the high pixel to the PC when the transmission of the image is initiated in connection with the PC.

In addition, the image application FPGA,

A decoder for separating the frame synchronizing signal, the horizontal synchronizing signal, and the image data signal from the digital data transmitted from the camera;

A 1394 corresponding digital data transmission unit for converting and transmitting the decoded data to conform to the 1394 interface;

A frame rate converting unit for changing the frame rate of the camera image of approximately 15 Hz for the RGB monitor output to support writing and reading of data into the RAM;

A synchronization signal generator for generating frame raid conversion and timing signals of the entire system; And

And a color space converter for converting the camera image data of YCrCb into a 24-bit RGB signal.

In addition, the microcomputer,

A digital data input interface for receiving decoded data;

A link interface for generating transmit and receive data;

A memory controller which stores the input data in the memory and transmits the data stored in the link interface;

A bus control layer that controls setup, connect, and disconnect of the 1394 bus; And

And a camera control layer that generates and sends control data for zoom control, focus control, brightness, and contrast control of the camera to the camera.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a structure of a high-pixel zoom camera system for transmitting an image to a PC using IEEE 1394 according to an embodiment of the present invention. Referring to FIG. 1, a high pixel zoom camera system according to an exemplary embodiment of the present invention includes a zoom mechanism 10 composed of a zoom lens 102, a CCD element 106, and a motor driver 104, and an analog signal processor 122. , Digital signal processor 124, microcomputer 126, image application FPGA (128: Field Programmable Gate Array, hereinafter referred to as FPGA), IEEE 1394 link layer interface 130, IEEE 1394 physical layer interface ( 132 and the PC 134.

In the zoom mechanism 10, the zoom lens 102 is driven by the motor driver 104, and the collected light is picked up by the CCD element 106, and the analog signal processor 122 and the digital signal processor 124 are used. Signal processing is done. In addition, the microcomputer and the FPGA are designed to output a camera signal by an external synchronization signal (Trigger), and a signal processing process is described in more detail below.

Next, the IEEE 1394 physical layer interface 132 handles the electrical and mechanical interface with the PC 134, and converts data including a process for connection communication and disconnection into a signal compatible with a communication medium. This layer corresponds to the first of seven layers of the OSI model that define the communication protocol. The IEEE 1394 link layer interface 130 is responsible for a protocol in a program that manages the movement of data in and out through the IEEE 1394 physical layer interface 132. This layer corresponds to the second of seven layers of the OSI model that define the communication protocol.

2 is a block diagram illustrating a structure of a high pixel zoom camera system according to another exemplary embodiment of the present invention. 2, the PC transmission high-pixel zoom camera system using the IEEE1394 according to an embodiment of the present invention is configured to simultaneously output the camera image to the PC using RGB video and IEEE1394, including a progressive zoom camera 202 It comprises a zoom mechanism 20 and an IEEE 1394 controller 22 for outputting an image to the PC 232 and the monitor 230.

3a and 3b show the detailed structure of FIG. The zoom mechanism 30 drives the lens 302 using the motor driver 304 and the motor, controls the focus and brightness, and the collected light is captured by the CCD 306, and the analog signal processor 322 The digital signal processing unit 324 is in charge of signal processing including color correction and brightness correction in the image captured by the CCD 306. The microcomputer 326 is a bus control process for controlling setup, connection, and disconnection of the 1394 bus, zoom control, focus control, brightness, And a camera control process for generating control data for contrast control and sending it to a camera, a link interface process for receiving decoded data and receiving and transmitting data, storing the input data in a memory, and storing the data in a link interface. A series of control processes including a memory control process for transmitting data control the zoom mechanism 30, the analog signal processor 322, and the digital signal processor 324. The digital transmission format FPGA 328 converts the signal processed image data into a format that can be transmitted. The transmitter 330 amplifies a signal to transmit the data through buffering for transmission and 5 m or more transmission lines.

The receiver 332 buffers and receives the image data transmitted through the cable. The image application FPGA 340 converts the received data into image inversion, black and white, and negative according to a user's selection, and simultaneously transmits the image data to the RGB encoder 342 and the IEEE1394 transmitting FPGA 350 for monitor output. Here, various functions including auto focus (AF), auto enhancement (AE), and auto white balance (AWB), RGB conversion, image inversion, black and white, and negative are programmed, loaded onto the FPGA, It is operated by executing.

Next, the RGB encoder 342 converts the digital image data received from the image application FPGA 340 into an analog image signal for monitor output. The RGB signal amplifier 344 amplifies the encoded analog video signal and sends the same to the monitor 346. The monitor 346 receives the amplified analog video signal and displays the video on the screen. This enables simultaneous monitor output of RGB video and PC transfer using IEEE1394.

When the IEEE1394 transmission FPGA 350 is connected to the PC 356 and transmission of the image starts, the IEEE 1394 transmission FPGA 350 transmits a high pixel image to the PC 356. The IEEE 1394 link layer interface 352 is responsible for a protocol in a program that manages the movement of data in and out through the IEEE 1394 physical layer interface 354. This layer corresponds to the second of seven layers of the OSI model that define the communication protocol. The IEEE 1394 physical layer interface 354 handles the electrical and mechanical interface with the PC 356, and converts data including a process for connection communication and disconnection into a signal compatible with a communication medium. This layer corresponds to the first of seven layers of the OSI model that define the communication protocol. The above communication protocol layers should be understood as a control for a PC, a protocol for transmitting and receiving image data to and from the PC, and operate under the control of the CPU 36. The RSC-232C interface 362, the keyboard 364, and the remote controller 366 are for interfacing with the CPU 360 and will not be described.

4 is a detailed block diagram of the image application FPGA 340 of FIG. 3B. Referring to FIG. 4, the decoder 402 separates a frame sync signal, a horizontal sync signal, and an image data signal from digital data transmitted from a camera. The IEEE 1394 compatible digital data transmitter 406 converts and transmits the decoded data to conform to the IEEE 1394 interface.

The frame rate converter 410 changes the frame rate of the camera image of about 15 kHz for the RGB monitor output to support data writing and reading to the RAM. The synchronization signal generator 412 generates the frame raid conversion and timing signals (HD, VD, and memory change signals) of the entire system. The color space converter converts the color space of the camera image data of YCrCb into a 24-bit RGB signal.

FIG. 5 is a detailed block diagram illustrating the IEEE 1394 interface of FIG. 3B. Referring to FIG. 5, a part referred to by reference numeral 50 is a part implemented by software driving and corresponds to a part for interpreting and controlling the IEEE 1394 protocol. The protocol layer may be divided into a camera control layer, a bus control layer of IEEE 1394, and an application layer for image control. Bus control layer 504 controls the setup, connect, and disconnect of the 1394 bus. The camera control layer 502 generates and sends control data to the camera 502a for zoom control, focus control, brightness, and contrast control of the camera 502a. In charge. As described above, by configuring the control process in the microcomputer for each protocol layer, it is possible to mount an algorithm implemented to enable the IEEE 1394 output of a high pixel image in real time.

In FIG. 5, the remaining part is a digital data input interface 420 for receiving decoded data as a H / W part, a memory controller 524 for storing the input data in a memory and transmitting the data stored in the link interface 530. And a link interface 530 for transmitting and receiving data, and an IEEE 1394 physical layer interface 332 for transmitting and receiving with an IEEE 1394 cable.

The high pixel zoom camera system as described above can simultaneously output the monitor output of RGB video and the PC transmission using IEEE1394.

In addition, it is equipped with an algorithm that enables IEEE1394 output of high-pixel images in real time, and supports not only camera control such as video storage and playback using IEEE1394 from a PC, but also a long length line can be adopted for camera installation. It supports various functions (Zoom, AF, AE, AWB, image reversal, black and white, negative) for accurate judgment of the image, so it can be simultaneously observed with a PC and a separate monitor, so it can be applied to medical, industrial and industrial zoom camera systems. Very effective.

The above embodiments are illustrative for the purpose of understanding the present invention and various modifications and variations are possible within the scope of the invention as defined by the appended claims. Accordingly, the scope of rights of the high pixel zoom camera system according to the present invention is not limited to the above embodiment.

As described above, the system according to the present invention supports the monitor output of RGB video and PC transmission using IEEE1394 at the same time, and is equipped with an algorithm implemented to enable the IEEE1394 output of high-pixel video in real time, and the image using IEEE1394 in the PC. In addition to supporting camera control such as recording and playback, a long line can be adopted for camera installation, and various functions for accurate judgment of the subject (Zoom, AF, AE, AWB, video inversion, black and white, negative) Simultaneous observation with a PC and a separate monitor enables the application to medical, educational, industrial, and industrial zoom camera systems or for industrial and industrial applications requiring an integrated high-pixel zoom camera operated by IEEE1394 and external synchronous signals. effective.

1 is a block diagram showing the structure of an IEEE1394 integrated high-pixel zoom camera system according to an embodiment of the present invention.

2 is a block diagram showing the structure of an IEEE1394 system separated from a high pixel zoom camera according to another embodiment of the present invention;

3A and 3B are block diagrams showing the detailed structure of FIG.

4 is a detailed block diagram of the image application FPGA of FIG. 3B.

5 is a block diagram illustrating in detail the 1394 interface of FIG. 3B.

Claims (3)

A zoom mechanism for driving the lens using a motor driver and a motor to collect an image from an object to be photographed and to capture an image by a CCD element; An analog signal processor and a digital signal processor for signal processing including color correction and brightness correction in the image captured by the CCD device; Bus control process to control setup, connect, and disconnect of 1394 bus, zoom control, focus control, brightness, and contrast of camera Camera control process that generates control data for control and sends it to camera, Link interface process that receives decoded data and makes transmission / reception data, Memory to store input data in memory and transmits data stored in link interface A microcomputer that controls the zoom mechanism, the analog signal processor, and the digital signal processor in a series of control processes including a control process; A digital transmission format FPGA for converting the signal-processed image data into a format for transmission; An IEEE 1394 physical layer interface that handles electrical and mechanical interfaces with a PC and converts data including signals for access communication and disconnection into signals compatible with the communication medium; An IEEE 1394 link layer interface in charge of a protocol in a program that manages movement of data in and out of the IEEE 1394 physical layer interface; A transmission unit for amplifying and transmitting a signal for transmission through buffering for transmission and a transmission line having a predetermined distance or more; A receiver for buffering and receiving image data transmitted through a cable; An image application FPGA converting the received data into image inversion, black and white, and negative and simultaneously transmitting image data to an RGB encoder and an IEEE1394 transmitting FPGA; An RGB encoder for converting digital image data received from the image application FPGA into an analog image signal for monitor output; An RGB signal amplifier for amplifying and transmitting the encoded analog image signal; A monitor configured to receive an amplified analog image signal and display an image; And an IEEE1394 transmission FPGA for transmitting an image of a high pixel to the PC when the image transmission is started by being connected to a PC. The method of claim 1, wherein the image application FPGA, A decoder for separating the frame synchronizing signal, the horizontal synchronizing signal, and the image data signal from the digital data transmitted from the camera; A 1394 corresponding digital data transmission unit for converting and transmitting the decoded data to conform to the 1394 interface; A frame rate converting unit for changing the frame rate of the camera image of approximately 15 Hz for the RGB monitor output to support writing and reading of data into the RAM; A synchronization signal generator for generating frame raid conversion and timing signals of the entire system; And And a color space conversion unit for converting the camera image data of YCrCb into a 24-bit RGB signal. The method of claim 1, wherein the microcomputer A digital data input interface for receiving decoded data; A link interface for generating transmit and receive data; A memory controller which stores the input data in the memory and transmits the data stored in the link interface; A bus control layer that controls setup, connect, and disconnect of the 1394 bus; And And a camera control layer that generates and sends control data for zoom control, focus control, brightness, and contrast control of the camera to the camera. High pixel zoom camera system.