CN112202740A

CN112202740A - FPGA-based awakenable UDP transmission protocol implementation method and system

Info

Publication number: CN112202740A
Application number: CN202010996159.9A
Authority: CN
Inventors: 鲁斌; 林定君; 洪红; 陈钱; 钱进
Original assignee: Shanghai Institute of Microwave Technology CETC 50 Research Institute
Current assignee: Shanghai Institute of Microwave Technology CETC 50 Research Institute
Priority date: 2020-09-21
Filing date: 2020-09-21
Publication date: 2021-01-08

Abstract

The invention provides a method and a system for realizing an awakenable UDP transmission protocol based on FPGA, comprising the following steps: building an Ethernet communication system of an FPGA end and a host machine from the FPGA, the PHY chip, the RJ45, the network cable and the host machine; realizing UDP protocol communication transmission in the FPGA according to a UDP/IP frame structure; compiling a module in the FPGA, polling a physical layer connection state through an SMI interface of a PHY chip, and monitoring the connection condition of the Ethernet; triggering the UDP communication module to restart after the physical layer is monitored to be disconnected and reconnected; and when the network connection state register is detected to be recovered to be normal after a period of time, the awakening function of UDP transmission is completed. The invention can rapidly and automatically awaken the Ethernet communication between the FPGA end and the host, avoids the complex operation of disassembling and assembling the shell and pressing the reset key of the signal processing board or manually closing the switch of the signal processing board and reconnecting, and has rapid awakening and simple means.

Description

FPGA-based awakenable UDP transmission protocol implementation method and system

Technical Field

The invention relates to the technical field of embedded network communication, in particular to a method and a system for realizing a UDP transmission protocol capable of being awakened based on an FPGA. In particular, it relates to a method for implementing network communication interruption and then wake-up caused by the host entering sleep mode in the transmission process of UDP.

Background

The FPGA and the field programmable gate array are semi-customized general devices, can be used for realizing circuits with any functions, and are widely applied to the fields of communication, industrial control, medical equipment, high-end security, aerospace, military industry and the like.

With the popularization of multimedia technology, the requirement of data transmission is higher and higher, and network transmission is particularly widely applied to data transmission. The use frequency of TCP and UDP in the network communication transmission layer protocol is the most, and UDP is suitable for communication or broadcast communication with higher high-speed transmission and real-time performance because of simple structure, less required system resources and higher working efficiency than TCP.

Udp (user Datagram protocol) is a connectionless, unreliable protocol, and each Datagram is a separate message located at the transport layer of the OSI. The UDP protocol is not divided into a client and a server, and only distributes a sending end and a receiving end. UDP does not require a connection to be established and therefore does not introduce a delay in establishing a connection. UDP packet header overhead is smaller, TCP has a 20 byte header overhead, while UDP has only an 8 byte header overhead.

UDP is often used for network applications and multimedia applications (e.g., IP telephony, real-time video conferencing, streaming media, etc.) that transmit relatively small data at a time, and network latency is more important than reliable data transmission. UDP is a best-effort delivery, i.e. does not guarantee a reliable delivery, but does not mean that the application's requirements for data are not reliable, and therefore the effort to maintain transmission reliability is left to the user at the application layer.

When the host is in sleep, the working state of the host is converted into a waiting state, all the work of the system can be stored in the hard disk, and meanwhile, the power supply of all the devices except the memory, including the network card, is turned off. The sleep mode of the host is mainly used for energy conservation, and the host can be awakened from the sleep mode to enter a working state by pressing a start key, a space key, an enter key and the like.

The network of the host and the FPGA end is disconnected due to the sleep mode, the host and the FPGA end are in data communication through UDP, the UDP is a connectionless and unreliable protocol, and the host cannot inform the FPGA end when entering the sleep mode.

When the FPGA is used for realizing UDP communication, the signal board can be found to be started before the host, or the host is awakened after entering the sleep mode, and the signal board and the host can not be used for UDP communication.

The UDP network interruption caused by the sleep of the host is generally solved by pressing a reset button of the signal processing board or manually turning off a switch of the signal processing board and reconnecting, and the disadvantages of the method mainly include:

1. the signal processing board is generally installed inside the electronic product, and the reset key does not lead out the casing, and the pressing of the reset key requires complex operations such as dismounting the casing.

2. The power supply of the signal processing board is generally provided by a power supply board, the switch of the signal processing board needs to be developed for the whole electronic product, many electronic products are provided with sensitive elements, and the electronic products need to be sensitive for a long time after power failure and restart so as to be stable, and then work normally, so that the use of the electronic products is influenced to a great extent.

Therefore, a more convenient and automatic method is needed to be found, so that the FPGA side can quickly resume network communication when the host sleeps or sleeps during communication with the host.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method and a system for realizing a UDP transmission protocol capable of waking up based on an FPGA.

The invention provides a realization method of a UDP transmission protocol capable of being awakened based on an FPGA, which comprises the following steps:

step S1: FPGA, PHY chip and RJ45 establish the ethernet communication system of FPGA end and host computer through net twine and host computer on the signal processing board, include: an application layer, a transport layer, a network layer, a data link layer and a physical layer;

step S2: realizing UDP protocol communication transmission in the FPGA according to a UDP/IP frame structure;

step S3: compiling a module in the FPGA, polling the connection state of the data link layer through an SMI interface of the PHY chip, and monitoring the connection condition of the Ethernet;

step S4: when the physical layer is monitored to be disconnected and reconnected, triggering the UDP communication module to be restarted, wherein the UDP communication module comprises a UDP sending and receiving module;

step S5: when the network connection state register is monitored to be recovered to be normal after a period of time, the awakening function of UDP transmission is completed;

the physical layer is connected with the signal processing board and the host through a 5-type or 6-type network cable and is used for transmitting binary information;

the data link layer is implemented by a physical layer chip for error, traffic and link control;

the transmission layer and the network layer are realized by an Ethernet communication module in the FPGA and are respectively used for sending and unpacking an IP protocol and sending and unpacking a UDP protocol;

the application layer is realized by other modules in the FPGA, and the awakenable function is realized in the application layer and is used for monitoring the network connection state and restarting the transmission of a network layer protocol and a transmission layer protocol.

Preferably, the UDP/IP frame in step S2 includes an ethernet header, a UDP header, an IP header, and a packet and an unpack of the user data.

Preferably, the SMI in step S3 is compatible with the IEEE802.3 protocol, and can read and write the control and status registers.

Preferably, the physical layer in step S4 is disconnected and reconnected, and after the corresponding host enters a sleep or hibernation mode, the host wakes up again to enter a standby state.

Preferably, the network connection status of step S5 has some initial instability, and needs to wait for a certain period of time.

The invention provides a system for realizing a UDP transmission protocol capable of waking up based on an FPGA, which is characterized by comprising the following steps:

module S1: FPGA, PHY chip and RJ45 establish the ethernet communication system of FPGA end and host computer through net twine and host computer on the signal processing board, include: an application layer, a transport layer, a network layer, a data link layer and a physical layer;

module S2: realizing UDP protocol communication transmission in the FPGA according to a UDP/IP frame structure;

module S3: compiling a module in the FPGA, polling the connection state of the data link layer through an SMI interface of the PHY chip, and monitoring the connection condition of the Ethernet;

module S4: when the physical layer is monitored to be disconnected and reconnected, triggering the UDP communication module to be restarted, wherein the UDP communication module comprises a UDP sending and receiving module;

module S5: when the network connection state register is monitored to be recovered to be normal after a period of time, the awakening function of UDP transmission is completed;

Preferably, the UDP/IP frame described by said module S2 includes an ethernet header, a UDP header, an IP header and a packet and an unpack of the user data.

Preferably, the SMI of the module S3 is compatible with the IEEE802.3 protocol, and can read and write the control and status registers.

Preferably, the physical layer in the module S4 is disconnected and reconnected, and after the corresponding host enters the sleep or hibernation mode, the host wakes up again to enter the standby state.

Preferably, the network connection status of the module S5 is initially unstable and needs to wait for a certain period of time.

Compared with the prior art, the invention has the following beneficial effects:

1. the method provided by the invention can quickly recover the UDP network transceiving communication between the FPGA end and the host, realizes the automation of the full recovery process and does not need to additionally add any equipment.

2. The invention has strong universality and is suitable for UDP communication between various FPGA and PHY chips and a host.

3. The invention can rapidly and automatically awaken the Ethernet communication between the FPGA end and the host, avoids the complex operation of adopting to disassemble and assemble the shell and press the reset key of the signal processing board or manually close the switch of the signal processing board and reconnect, and has rapid awakening and simple means

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic diagram of a method for implementing an FPGA-based UDP transport protocol.

Fig. 2 is a schematic diagram of a hardware transmission system according to the present invention.

Fig. 3 is a schematic diagram of an ethernet frame structure provided in the present invention.

Fig. 4 is a schematic diagram of an ethernet header structure provided in the present invention.

Fig. 5 is a schematic diagram of an IP header structure provided in the present invention.

Fig. 6 is a schematic diagram of the UDP header data format provided in the present invention.

Fig. 7 is a schematic diagram of a UDP transport structure provided in the present invention.

Fig. 8 is a schematic diagram of a sending module jump provided by the present invention.

Fig. 9 is a schematic diagram of a receiver module jump provided in the present invention.

Fig. 10 is a schematic diagram of simulation results provided by the present invention.

Fig. 11 is a schematic view of a reading sequence of the SMI interface provided in the present invention.

Fig. 12 is a schematic diagram of a write timing of the SMI interface according to the present invention.

Fig. 13 is a schematic diagram of an SMI wakeup determination process according to the present invention.

Fig. 14 is a schematic diagram of a wake-on-lan operation flow provided by the present invention.

Fig. 15 is a schematic diagram of a wake-on-lan operation flow provided by the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

A specific embodiment of the method for implementing the FPGA-based UDP transport protocol will be described in detail with reference to fig. 1.

Step 1, a hardware transmission system is built, as shown in fig. 2.

The signal processing board is connected with the host through a network cable, the FPGA serves as a controller, and an Ethernet hardware transmission system is constructed with the host through the physical layer chip PHY and the crystal plug RJ 45.

Step 2, realizing UDP network communication function in FPGA

In the hardware transmission system, a physical link layer of data of network communication is realized by a physical layer chip PHY, a transmission layer and a network layer are realized by a UDP transmission module in FPGA, and an application layer is realized by other modules in FPGA.

The structure of an ethernet frame based on the UDP/IP protocol is shown in fig. 3;

user data is transmitted through the ethernet, and information such as an ethernet header, an IP header, and a UDP header needs to be added.

Wherein the ethernet header structure is shown in fig. 4.

The ethernet header contains three contents of a destination address, a source address, and a type. The length of the subsequent data of the complete Ethernet data frame is 46-1500 bytes.

The IP header structure is shown in fig. 5.

A normal IP header is 20 bytes long and contains information such as version number, IP header length, etc., unless an option field is included.

The UDP header structure is shown in fig. 6.

The UDP header contains the source port number, the destination port number, the UDP length, and the UDP checksum.

The schematic diagram of the structure of implementing UDP by FPGA is shown in fig. 7.

In fig. 7, the user interface is some signals provided by the data upload module to the UDP transport module, such as a clock signal, a reset signal, a send related control signal, and an accept related control signal. The most important of UDP transmission is a sending module and a receiving module, which respectively realize the sending and receiving with external data through a GMII interface.

The state transition diagram of the sending module is shown in fig. 8.

The state machine of the sending module consists of 9 states. After the system is reset, S0 jumps to S1 and detects the carrier sense signal, i.e., the channel idle/busy state. When the channel is idle, S1 jumps to S2, and after waiting for one interframe space, S2 jumps to S3. At S3, the sending module will detect the carrier sense signal and the sending request of the host interface, and if the host requests sending, S3 jumps to S4. After transmitting the preamble (7 0x55), S4 jumps to S5, transmits the start frame delimiter 0xD5, and S5 jumps to S6. At S6, the sending module will jump to S7 or S8 according to the length of the frame, and when the frame length is smaller than the shortest frame, S6 jumps to S7, and then add padding code after the frame data, i.e., S7 jumps to S8. After the CRC value is transmitted, S8 jumps to S1 to wait for a request for the next frame to transmit data.

The state transition diagram of the receiving module is shown in fig. 9.

The receiving module consists of 7 states. After the system is reset, S0 jumps to S1. After the receiving module detects the data valid signal, the state machine will proceed to S2. When the preamble (7 0x55) is received, S2 jumps to S3. S3 receives a one-byte start frame delimiter (0xd5), and S3 jumps to S4. At S4, the receiving module puts the PHY received data into the FIFO, and after the data is received, the state machine jumps to S5. At S5, the time interval is judged according to the counter, and if the interval is greater than the minimum value (96bit time), S5 jumps to S1; if the time determined by the counter is less than the minimum value, S5 jumps to S6 until the end of the data valid, S6 jumps to S1.

After the design program is written, simulation is performed, and the related results are shown in fig. 10.

As can be seen from fig. 10, when the O _ txen is valid, the O _ txd sequentially outputs 0x55 and 0x55 …, and completely meets the requirement of preamble information in the normal UDP format, the O _ rgmii _ txd is used for DDR processing of the O _ txd, and the subsequent transmission is completed by the PHY chip, and the simulation result meets the system requirement.

Step 3, realizing SMI interface communication in FPGA

The Serial Management Interface (SMI) of the physical layer chip is compatible with IEEE802.3 protocol, and can be used to connect the control and status registers of the physical layer chip, including two pins, MDC and MDIO. The design utilizes the register information such as the physical layer connection state in the physical layer chip to realize the network awakening function.

The read sequence of the SMI interface is shown in fig. 11.

The write timing of the SMI interface is shown in fig. 12.

Step 4, FPGA realizes network awakening judgment

When the host enters the sleep mode, the network connection state register is OFF, then the host exits the sleep mode, the network connection state register is ON, and the FPGA accesses the change of the network connection state register through the SMI interface to realize judgment triggering of network awakening.

The specific flow is schematically shown in fig. 13.

Step 5, the FPGA realizes network awakening operation

After determining that wake-on-lan is required, a wake-on-lan operation is performed, and the specific flow is shown in fig. 14 and 15.

The wake-on-lan operation is divided into two parts, an SMI register operation and a UDP communication operation. Specifically, SMI register operation includes writing the XX register, UDP communication operation includes receiving clock management unit reset, sending module counter reset, etc.

As can be seen from the steps 1 to 5, the measurement method of the invention can realize the awakening of the UDP transmission protocol, and has the advantages of high awakening speed and simple means.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A realization method of awakenable UDP transmission protocol based on FPGA is characterized in that: the method comprises the following steps:

2. The method for implementing FPGA-based UDP transport protocol of claim 1 wherein the UDP/IP frame of step S2 includes an ethernet header, a UDP header, an IP header, and a packet and an unpack of user data.

3. The method for implementing a wake-up UDP transport protocol based on FPGA of claim 1, wherein the SMI of step S3 is compatible with IEEE802.3 protocol, and can read and write the control and status registers.

4. The method for implementing an FPGA-based UDP transport protocol according to claim 1, wherein the physical layer in step S4 is disconnected from reconnection, and the host wakes up again after the host enters a sleep or hibernation mode to enter a standby state.

5. The method for implementing an FPGA-based UDP transport protocol of claim 1, wherein the network connection status of step S5 initially has some instability, and needs to wait for a period of time.

6. A realization system of awakenable UDP transmission protocol based on FPGA is characterized in that: the method comprises the following steps:

7. The FPGA-based awakenable UDP transport protocol implementation system as claimed in claim 6, wherein the UDP/IP frame of the module S2 comprises an Ethernet header, a UDP header, an IP header and a packet and an unpack of the user data.

8. The system according to claim 6, wherein the SMI in the module S3 is compatible with IEEE802.3 protocol, and can read and write the control and status registers.

9. The system according to claim 6, wherein the physical layer of the module S4 disconnects reconnection, and the host wakes up again after entering a sleep or hibernation mode to enter a standby state.

10. The system according to claim 6, wherein the network connection status of the module S5 has some initial instability and needs to wait for a period of time.